CSIRX_ErrorIrqs Struct Reference

Detailed Description

Datapath error interrupt status. Provides information about data path errors. The host processor can read the interrupt status register to identify the root cause of the event, typically after that the CSIRX_ErrIrq interrupt line is raised

Data Fields
uint8_t	fifoOverflowIrq [CSIRX_MAX_NUM_OF_STREAMS]
uint8_t	spInvalidRcvdIrq
uint8_t	invalidAccessIrq
uint8_t	dataIdIrq
uint8_t	headerCorrectedEccIrq
uint8_t	headerEccIrq
uint8_t	payloadCrcIrq
uint8_t	frontFifoOverflowIrq

Field Documentation

fifoOverflowIrq

uint8_t CSIRX_ErrorIrqs::fifoOverflowIrq[CSIRX_MAX_NUM_OF_STREAMS]

Overflow of the Stream FIFO detected

spInvalidRcvdIrq

uint8_t CSIRX_ErrorIrqs::spInvalidRcvdIrq

A reserved or invalid short packet has been received

invalidAccessIrq

uint8_t CSIRX_ErrorIrqs::invalidAccessIrq

Invalid access to the configuration register space.

dataIdIrq

uint8_t CSIRX_ErrorIrqs::dataIdIrq

Data ID error has been detected in the header packet

headerCorrectedEccIrq

uint8_t CSIRX_ErrorIrqs::headerCorrectedEccIrq

ECC error has been detected and corrected.

headerEccIrq

uint8_t CSIRX_ErrorIrqs::headerEccIrq

Unrecoverable ECC error has been detected.

payloadCrcIrq

uint8_t CSIRX_ErrorIrqs::payloadCrcIrq

CRC error has been detected.

frontFifoOverflowIrq

uint8_t CSIRX_ErrorIrqs::frontFifoOverflowIrq

Overflow detected in resynchronization FIFO between DPHY Lane Management and Protocol blocks. This will occur if SysClk is not fast enough and should be increased since the byte clock frequency is fixed