5.1.3.1.1. CSL ADC Singleshot Example

This example application illustrates the functionality of an ADC (Analog to Digital Convertor) in Single shot mode. The application parses the analog voltage provided in ADC connector. It uses SYNTIMER32k for timing calculations and the following steps are enabled -

Step ID

Input from Channel

2

1

3

3

4

4

5

5

6

6

5.1.3.1.1.1. Building ADC example

To build the ADC example app in PDK, use the following command:

$ make -s -j8 csl_adc_singleshot_test_app BOARD=<BOARD> CORE=<CORE>

The example app binary file can be found at the following location:

<pdk>/packages/ti/binary/csl_adc_singleshot_test_app/bin/<BOARD>/csl_adc_singleshot_test_app_<CORE>_release.xer5f

This command will build the ADC example app (csl_adc_singleshot_test_app) on baremetal. Adjust the command according to your specific requirements, such as selecting a different board or core if needed. By default, the release mode is built. You can specify build mode by adding BUILD_PROFILE=debug in the instruction.

5.1.3.1.1.2. Supported SOCs

  • j721e

  • j7200

5.1.3.1.1.3. Supported cores

  • mcu1_0

5.1.3.1.1.4. Hardware Connections

  • none

5.1.3.1.1.5. Running ADC example

After building the example, follow the given steps to run the test:

  • Launch a CCS debug session, load and run csl_adc_singleshot_test_app_<CORE>_release.xer5f binary file to the respective core for which the binary is built. Alternatively, the example application can be loaded using any other boot method such as MMC/SD.

  • Logs will be printed on the CCS console, Main UART port 0 or MCU UART port 1 based on which core you are running the example. Below is an example of the log when running csl_adc_singleshot_test_app on J721E on mcu1_0 core:

    Binary: <pdk>/packages/ti/binary/csl_adc_singleshot_test_app/bin/<BOARD>/csl_adc_singleshot_test_app_<CORE>_release.xer5f

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    Starting application...
ADC Revision ID:
Scheme            :0x1
Functional number :0x9c0
RTL revision      :0x7
Major revision    :0x1
Minor revision    :0x0
Custom revision   :0x0

In ISR...
End of sequence interrupt occurred.
Number of samples in FIFO:5
FIFO Data:
Step ID:2
Voltage Level:1278mV
Step ID:3
Voltage Level:1453mV
Step ID:4
Voltage Level:1470mV
Step ID:5
Voltage Level:1469mV
Step ID:6
Voltage Level:1499mV

Application is completed.

All tests have passed.
adc_app.c:678:test_csl_adc_singleshot_test_app:PASS

-----------------------
1 Tests 0 Failures 0 Ignored
OK