Introduction

Data Structures
struct	CSL_RTIRegs

Macros
#define	RTI_RTIGCTRL (0x0U)

#define	RTI_RTITBCTRL (0x4U)

#define	RTI_RTICAPCTRL (0x8U)

#define	RTI_RTICOMPCTRL (0xcU)

#define	RTI_RTIFRC0 (0x10U)

#define	RTI_RTIUC0 (0x14U)

#define	RTI_RTICPUC0 (0x18U)

#define	RTI_RTICAFRC0 (0x20U)

#define	RTI_RTICAUC0 (0x24U)

#define	RTI_RTIFRC1 (0x30U)

#define	RTI_RTIUC1 (0x34U)

#define	RTI_RTICPUC1 (0x38U)

#define	RTI_RTICAFRC1 (0x40U)

#define	RTI_RTICAUC1 (0x44U)

#define	RTI_RTICOMP0 (0x50U)

#define	RTI_RTIUDCP0 (0x54U)

#define	RTI_RTICOMP1 (0x58U)

#define	RTI_RTIUDCP1 (0x5cU)

#define	RTI_RTICOMP2 (0x60U)

#define	RTI_RTIUDCP2 (0x64U)

#define	RTI_RTICOMP3 (0x68U)

#define	RTI_RTIUDCP3 (0x6cU)

#define	RTI_RTITBLCOMP (0x70U)

#define	RTI_RTITBHCOMP (0x74U)

#define	RTI_RTISETINT (0x80U)

#define	RTI_RTICLEARINT (0x84U)

#define	RTI_RTIINTFLAG (0x88U)

#define	RTI_RTIDWDCTRL (0x90U)

#define	RTI_RTIDWDPRLD (0x94U)

#define	RTI_RTIWDSTATUS (0x98U)

#define	RTI_RTIWDKEY (0x9cU)

#define	RTI_RTIDWDCNTR (0xa0U)

#define	RTI_RTIDWWDRXNCTRL (0xa4U)

#define	RTI_RTIDWWDSIZECTRL (0xa8U)

#define	RTI_RTIINTCLRENABLE (0xacU)

#define	RTI_RTICOMP0CLR (0xb0U)

#define	RTI_RTICOMP1CLR (0xb4U)

#define	RTI_RTICOMP2CLR (0xb8U)

#define	RTI_RTICOMP3CLR (0xbcU)

#define	RTI_RTIGCTRL_CNT0EN_SHIFT (0U)

#define	RTI_RTIGCTRL_CNT0EN_MASK (0x00000001U)

#define	RTI_RTIGCTRL_CNT1EN_SHIFT (1U)

#define	RTI_RTIGCTRL_CNT1EN_MASK (0x00000002U)

#define	RTI_RTIGCTRL_COS_SHIFT (15U)

#define	RTI_RTIGCTRL_COS_MASK (0x00008000U)

#define	RTI_RTIGCTRL_COS_STOPPED (0x0U)

#define	RTI_RTIGCTRL_COS_RUNNING (0x1U)

#define	RTI_RTIGCTRL_NTUSEL_SHIFT (16U)

#define	RTI_RTIGCTRL_NTUSEL_MASK (0x000f0000U)

#define	RTI_RTITBCTRL_TBEXT_SHIFT (0U)

#define	RTI_RTITBCTRL_TBEXT_MASK (0x00000001U)

#define	RTI_RTITBCTRL_INC_SHIFT (1U)

#define	RTI_RTITBCTRL_INC_MASK (0x00000002U)

#define	RTI_RTICAPCTRL_CAPCNTR0_SHIFT (0U)

#define	RTI_RTICAPCTRL_CAPCNTR0_MASK (0x00000001U)

#define	RTI_RTICAPCTRL_CAPCNTR1_SHIFT (1U)

#define	RTI_RTICAPCTRL_CAPCNTR1_MASK (0x00000002U)

#define	RTI_RTICOMPCTRL_COMPSEL0_SHIFT (0U)

#define	RTI_RTICOMPCTRL_COMPSEL0_MASK (0x00000001U)

#define	RTI_RTICOMPCTRL_COMPSEL1_SHIFT (4U)

#define	RTI_RTICOMPCTRL_COMPSEL1_MASK (0x00000010U)

#define	RTI_RTICOMPCTRL_COMPSEL2_SHIFT (8U)

#define	RTI_RTICOMPCTRL_COMPSEL2_MASK (0x00000100U)

#define	RTI_RTICOMPCTRL_COMPSEL3_SHIFT (12U)

#define	RTI_RTICOMPCTRL_COMPSEL3_MASK (0x00001000U)

#define	RTI_RTIFRC0_FRC0_SHIFT (0U)

#define	RTI_RTIFRC0_FRC0_MASK (0xffffffffU)

#define	RTI_RTIUC0_UC0_SHIFT (0U)

#define	RTI_RTIUC0_UC0_MASK (0xffffffffU)

#define	RTI_RTICPUC0_CPUC0_SHIFT (0U)

#define	RTI_RTICPUC0_CPUC0_MASK (0xffffffffU)

#define	RTI_RTICAFRC0_CAFRC0_SHIFT (0U)

#define	RTI_RTICAFRC0_CAFRC0_MASK (0xffffffffU)

#define	RTI_RTICAUC0_CAUC0_SHIFT (0U)

#define	RTI_RTICAUC0_CAUC0_MASK (0xffffffffU)

#define	RTI_RTIFRC1_FRC1_SHIFT (0U)

#define	RTI_RTIFRC1_FRC1_MASK (0xffffffffU)

#define	RTI_RTIUC1_UC1_SHIFT (0U)

#define	RTI_RTIUC1_UC1_MASK (0xffffffffU)

#define	RTI_RTICPUC1_CPUC1_SHIFT (0U)

#define	RTI_RTICPUC1_CPUC1_MASK (0xffffffffU)

#define	RTI_RTICAFRC1_CAFRC1_SHIFT (0U)

#define	RTI_RTICAFRC1_CAFRC1_MASK (0xffffffffU)

#define	RTI_RTICAUC1_CAUC1_SHIFT (0U)

#define	RTI_RTICAUC1_CAUC1_MASK (0xffffffffU)

#define	RTI_RTICOMP0_COMP0_SHIFT (0U)

#define	RTI_RTICOMP0_COMP0_MASK (0xffffffffU)

#define	RTI_RTIUDCP0_UDCP0_SHIFT (0U)

#define	RTI_RTIUDCP0_UDCP0_MASK (0xffffffffU)

#define	RTI_RTICOMP1_COMP1_SHIFT (0U)

#define	RTI_RTICOMP1_COMP1_MASK (0xffffffffU)

#define	RTI_RTIUDCP1_UDCP1_SHIFT (0U)

#define	RTI_RTIUDCP1_UDCP1_MASK (0xffffffffU)

#define	RTI_RTICOMP2_COMP2_SHIFT (0U)

#define	RTI_RTICOMP2_COMP2_MASK (0xffffffffU)

#define	RTI_RTIUDCP2_UDCP2_SHIFT (0U)

#define	RTI_RTIUDCP2_UDCP2_MASK (0xffffffffU)

#define	RTI_RTICOMP3_COMP3_SHIFT (0U)

#define	RTI_RTICOMP3_COMP3_MASK (0xffffffffU)

#define	RTI_RTIUDCP3_UDCP3_SHIFT (0U)

#define	RTI_RTIUDCP3_UDCP3_MASK (0xffffffffU)

#define	RTI_RTITBLCOMP_TBLCOMP_SHIFT (0U)

#define	RTI_RTITBLCOMP_TBLCOMP_MASK (0xffffffffU)

#define	RTI_RTITBHCOMP_TBHCOMP_SHIFT (0U)

#define	RTI_RTITBHCOMP_TBHCOMP_MASK (0xffffffffU)

#define	RTI_RTISETINT_SETINT0_SHIFT (0U)

#define	RTI_RTISETINT_SETINT0_MASK (0x00000001U)

#define	RTI_RTISETINT_SETINT1_SHIFT (1U)

#define	RTI_RTISETINT_SETINT1_MASK (0x00000002U)

#define	RTI_RTISETINT_SETINT2_SHIFT (2U)

#define	RTI_RTISETINT_SETINT2_MASK (0x00000004U)

#define	RTI_RTISETINT_SETINT3_SHIFT (3U)

#define	RTI_RTISETINT_SETINT3_MASK (0x00000008U)

#define	RTI_RTISETINT_SETDMA0_SHIFT (8U)

#define	RTI_RTISETINT_SETDMA0_MASK (0x00000100U)

#define	RTI_RTISETINT_SETDMA1_SHIFT (9U)

#define	RTI_RTISETINT_SETDMA1_MASK (0x00000200U)

#define	RTI_RTISETINT_SETDMA2_SHIFT (10U)

#define	RTI_RTISETINT_SETDMA2_MASK (0x00000400U)

#define	RTI_RTISETINT_SETDMA3_SHIFT (11U)

#define	RTI_RTISETINT_SETDMA3_MASK (0x00000800U)

#define	RTI_RTISETINT_SETTBINT_SHIFT (16U)

#define	RTI_RTISETINT_SETTBINT_MASK (0x00010000U)

#define	RTI_RTISETINT_SETOVL0INT_SHIFT (17U)

#define	RTI_RTISETINT_SETOVL0INT_MASK (0x00020000U)

#define	RTI_RTISETINT_SETOVL1INT_SHIFT (18U)

#define	RTI_RTISETINT_SETOVL1INT_MASK (0x00040000U)

#define	RTI_RTICLEARINT_CLEARINT0_SHIFT (0U)

#define	RTI_RTICLEARINT_CLEARINT0_MASK (0x00000001U)

#define	RTI_RTICLEARINT_CLEARINT1_SHIFT (1U)

#define	RTI_RTICLEARINT_CLEARINT1_MASK (0x00000002U)

#define	RTI_RTICLEARINT_CLEARINT2_SHIFT (2U)

#define	RTI_RTICLEARINT_CLEARINT2_MASK (0x00000004U)

#define	RTI_RTICLEARINT_CLEARINT3_SHIFT (3U)

#define	RTI_RTICLEARINT_CLEARINT3_MASK (0x00000008U)

#define	RTI_RTICLEARINT_CLEARDMA0_SHIFT (8U)

#define	RTI_RTICLEARINT_CLEARDMA0_MASK (0x00000100U)

#define	RTI_RTICLEARINT_CLEARDMA1_SHIFT (9U)

#define	RTI_RTICLEARINT_CLEARDMA1_MASK (0x00000200U)

#define	RTI_RTICLEARINT_CLEARDMA2_SHIFT (10U)

#define	RTI_RTICLEARINT_CLEARDMA2_MASK (0x00000400U)

#define	RTI_RTICLEARINT_CLEARDMA3_SHIFT (11U)

#define	RTI_RTICLEARINT_CLEARDMA3_MASK (0x00000800U)

#define	RTI_RTICLEARINT_CLEARTBINT_SHIFT (16U)

#define	RTI_RTICLEARINT_CLEARTBINT_MASK (0x00010000U)

#define	RTI_RTICLEARINT_CLEAROVL0INT_SHIFT (17U)

#define	RTI_RTICLEARINT_CLEAROVL0INT_MASK (0x00020000U)

#define	RTI_RTICLEARINT_CLEAROVL1INT_SHIFT (18U)

#define	RTI_RTICLEARINT_CLEAROVL1INT_MASK (0x00040000U)

#define	RTI_RTIINTFLAG_INT0_SHIFT (0U)

#define	RTI_RTIINTFLAG_INT0_MASK (0x00000001U)

#define	RTI_RTIINTFLAG_INT1_SHIFT (1U)

#define	RTI_RTIINTFLAG_INT1_MASK (0x00000002U)

#define	RTI_RTIINTFLAG_INT2_SHIFT (2U)

#define	RTI_RTIINTFLAG_INT2_MASK (0x00000004U)

#define	RTI_RTIINTFLAG_INT3_SHIFT (3U)

#define	RTI_RTIINTFLAG_INT3_MASK (0x00000008U)

#define	RTI_RTIINTFLAG_TBINT_SHIFT (16U)

#define	RTI_RTIINTFLAG_TBINT_MASK (0x00010000U)

#define	RTI_RTIINTFLAG_OVL0INT_SHIFT (17U)

#define	RTI_RTIINTFLAG_OVL0INT_MASK (0x00020000U)

#define	RTI_RTIINTFLAG_OVL1INT_SHIFT (18U)

#define	RTI_RTIINTFLAG_OVL1INT_MASK (0x00040000U)

#define	RTI_RTIDWDCTRL_DWDCTRL_15_0_SHIFT (0U)

#define	RTI_RTIDWDCTRL_DWDCTRL_15_0_MASK (0x0000ffffU)

#define	RTI_RTIDWDCTRL_DWDCTRL_31_16_SHIFT (16U)

#define	RTI_RTIDWDCTRL_DWDCTRL_31_16_MASK (0xffff0000U)

#define	RTI_RTIDWDCTRL_DWDCTRL_DISABLE (0x5312ACEDU)

#define	RTI_RTIDWDCTRL_DWDCTRL_ENABLE (0xA98559DAU)

#define	RTI_RTIDWDPRLD_DWDPRLD_SHIFT (0U)

#define	RTI_RTIDWDPRLD_DWDPRLD_MASK (0x00000fffU)

#define	RTI_RTIDWDPRLD_DWDPRLD_MAX (0x0FFFU)

#define	RTI_RTIWDSTATUS_AWDST_SHIFT (0U)

#define	RTI_RTIWDSTATUS_AWDST_MASK (0x00000001U)

#define	RTI_RTIWDSTATUS_DWDST_SHIFT (1U)

#define	RTI_RTIWDSTATUS_DWDST_MASK (0x00000002U)

#define	RTI_RTIWDSTATUS_KEYST_SHIFT (2U)

#define	RTI_RTIWDSTATUS_KEYST_MASK (0x00000004U)

#define	RTI_RTIWDSTATUS_KEYST_CORRECT_KEY (0x00000000U)

#define	RTI_RTIWDSTATUS_KEYST_INCORRECT_KEY (0x00000001U)

#define	RTI_RTIWDSTATUS_START_TIME_VIOL_SHIFT (3U)

#define	RTI_RTIWDSTATUS_START_TIME_VIOL_MASK (0x00000008U)

#define	RTI_RTIWDSTATUS_END_TIME_VIOL_SHIFT (4U)

#define	RTI_RTIWDSTATUS_END_TIME_VIOL_MASK (0x00000010U)

#define	RTI_RTIWDSTATUS_DWWD_ST_SHIFT (5U)

#define	RTI_RTIWDSTATUS_DWWD_ST_MASK (0x00000020U)

#define	RTI_RTIWDKEY_WDKEY_SHIFT (0U)

#define	RTI_RTIWDKEY_WDKEY_MASK (0x0000ffffU)

#define	RTI_RTIWDKEY_WDKEY_FIRST_WRITE (0x0000E51AU)

#define	RTI_RTIWDKEY_WDKEY_SECOND_WRITE (0x0000A35CU)

#define	RTI_RTIDWDCNTR_DWDCNTR_15_0_SHIFT (0U)

#define	RTI_RTIDWDCNTR_DWDCNTR_15_0_MASK (0x0000ffffU)

#define	RTI_RTIDWDCNTR_DWDCNTR_24_16_SHIFT (16U)

#define	RTI_RTIDWDCNTR_DWDCNTR_24_16_MASK (0x01ff0000U)

#define	RTI_RTIDWWDRXNCTRL_DWWDRXN_SHIFT (0U)

#define	RTI_RTIDWWDRXNCTRL_DWWDRXN_MASK (0x0000000fU)

#define	RTI_RTIDWWDRXNCTRL_DWWDRXN_RESET (0x5U)

#define	RTI_RTIDWWDRXNCTRL_DWWDRXN_INTERRUPT (0xAU)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_SHIFT (0U)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_MASK (0x00ffffffU)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_100_PERCENT (0x00000005U)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_100_PERCENT_SHIFT (0x0)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_50_PERCENT (0x00000050U)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_50_PERCENT_SHIFT (0x1)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_25_PERCENT (0x00000500U)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_25_PERCENT_SHIFT (0x2)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_12_5_PERCENT (0x00005000U)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_12_5_PERCENT_SHIFT (0x3)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_6_25_PERCENT (0x00050000U)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_6_25_PERCENT_SHIFT (0x4)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_3_125_PERCENT (0x00500000U)

#define	RTI_RTIDWWDSIZECTRL_DWWDSIZE_3_125_PERCENT_SHIFT (0x5)

#define	RTI_RTIINTCLRENABLE_INTCLRENABLE0_SHIFT (0U)

#define	RTI_RTIINTCLRENABLE_INTCLRENABLE0_MASK (0x0000000fU)

#define	RTI_RTIINTCLRENABLE_INTCLRENABLE1_SHIFT (8U)

#define	RTI_RTIINTCLRENABLE_INTCLRENABLE1_MASK (0x00000f00U)

#define	RTI_RTIINTCLRENABLE_INTCLRENABLE2_SHIFT (16U)

#define	RTI_RTIINTCLRENABLE_INTCLRENABLE2_MASK (0x000f0000U)

#define	RTI_RTIINTCLRENABLE_INTCLRENABLE3_SHIFT (24U)

#define	RTI_RTIINTCLRENABLE_INTCLRENABLE3_MASK (0x0f000000U)

#define	RTI_RTICOMP0CLR_COMP0CLR_SHIFT (0U)

#define	RTI_RTICOMP0CLR_COMP0CLR_MASK (0xffffffffU)

#define	RTI_RTICOMP1CLR_COMP1CLR_SHIFT (0U)

#define	RTI_RTICOMP1CLR_COMP1CLR_MASK (0xffffffffU)

#define	RTI_RTICOMP2CLR_COMP2CLR_SHIFT (0U)

#define	RTI_RTICOMP2CLR_COMP2CLR_MASK (0xffffffffU)

#define	RTI_RTICOMP3CLR_COMP3CLR_SHIFT (0U)

#define	RTI_RTICOMP3CLR_COMP3CLR_MASK (0xffffffffU)

Macro Definition Documentation

◆ RTI_RTIGCTRL

#define RTI_RTIGCTRL (0x0U)

◆ RTI_RTITBCTRL

#define RTI_RTITBCTRL (0x4U)

◆ RTI_RTICAPCTRL

#define RTI_RTICAPCTRL (0x8U)

◆ RTI_RTICOMPCTRL

#define RTI_RTICOMPCTRL (0xcU)

◆ RTI_RTIFRC0

#define RTI_RTIFRC0 (0x10U)

◆ RTI_RTIUC0

#define RTI_RTIUC0 (0x14U)

◆ RTI_RTICPUC0

#define RTI_RTICPUC0 (0x18U)

◆ RTI_RTICAFRC0

#define RTI_RTICAFRC0 (0x20U)

◆ RTI_RTICAUC0

#define RTI_RTICAUC0 (0x24U)

◆ RTI_RTIFRC1

#define RTI_RTIFRC1 (0x30U)

◆ RTI_RTIUC1

#define RTI_RTIUC1 (0x34U)

◆ RTI_RTICPUC1

#define RTI_RTICPUC1 (0x38U)

◆ RTI_RTICAFRC1

#define RTI_RTICAFRC1 (0x40U)

◆ RTI_RTICAUC1

#define RTI_RTICAUC1 (0x44U)

◆ RTI_RTICOMP0

#define RTI_RTICOMP0 (0x50U)

◆ RTI_RTIUDCP0

#define RTI_RTIUDCP0 (0x54U)

◆ RTI_RTICOMP1

#define RTI_RTICOMP1 (0x58U)

◆ RTI_RTIUDCP1

#define RTI_RTIUDCP1 (0x5cU)

◆ RTI_RTICOMP2

#define RTI_RTICOMP2 (0x60U)

◆ RTI_RTIUDCP2

#define RTI_RTIUDCP2 (0x64U)

◆ RTI_RTICOMP3

#define RTI_RTICOMP3 (0x68U)

◆ RTI_RTIUDCP3

#define RTI_RTIUDCP3 (0x6cU)

◆ RTI_RTITBLCOMP

#define RTI_RTITBLCOMP (0x70U)

◆ RTI_RTITBHCOMP

#define RTI_RTITBHCOMP (0x74U)

◆ RTI_RTISETINT

#define RTI_RTISETINT (0x80U)

◆ RTI_RTICLEARINT

#define RTI_RTICLEARINT (0x84U)

◆ RTI_RTIINTFLAG

#define RTI_RTIINTFLAG (0x88U)

◆ RTI_RTIDWDCTRL

#define RTI_RTIDWDCTRL (0x90U)

◆ RTI_RTIDWDPRLD

#define RTI_RTIDWDPRLD (0x94U)

◆ RTI_RTIWDSTATUS

#define RTI_RTIWDSTATUS (0x98U)

◆ RTI_RTIWDKEY

#define RTI_RTIWDKEY (0x9cU)

◆ RTI_RTIDWDCNTR

#define RTI_RTIDWDCNTR (0xa0U)

◆ RTI_RTIDWWDRXNCTRL

#define RTI_RTIDWWDRXNCTRL (0xa4U)

◆ RTI_RTIDWWDSIZECTRL

#define RTI_RTIDWWDSIZECTRL (0xa8U)

◆ RTI_RTIINTCLRENABLE

#define RTI_RTIINTCLRENABLE (0xacU)

◆ RTI_RTICOMP0CLR

#define RTI_RTICOMP0CLR (0xb0U)

◆ RTI_RTICOMP1CLR

#define RTI_RTICOMP1CLR (0xb4U)

◆ RTI_RTICOMP2CLR

#define RTI_RTICOMP2CLR (0xb8U)

◆ RTI_RTICOMP3CLR

#define RTI_RTICOMP3CLR (0xbcU)

◆ RTI_RTIGCTRL_CNT0EN_SHIFT

#define RTI_RTIGCTRL_CNT0EN_SHIFT (0U)

◆ RTI_RTIGCTRL_CNT0EN_MASK

#define RTI_RTIGCTRL_CNT0EN_MASK (0x00000001U)

◆ RTI_RTIGCTRL_CNT1EN_SHIFT

#define RTI_RTIGCTRL_CNT1EN_SHIFT (1U)

◆ RTI_RTIGCTRL_CNT1EN_MASK

#define RTI_RTIGCTRL_CNT1EN_MASK (0x00000002U)

◆ RTI_RTIGCTRL_COS_SHIFT

#define RTI_RTIGCTRL_COS_SHIFT (15U)

◆ RTI_RTIGCTRL_COS_MASK

#define RTI_RTIGCTRL_COS_MASK (0x00008000U)

◆ RTI_RTIGCTRL_COS_STOPPED

#define RTI_RTIGCTRL_COS_STOPPED (0x0U)

◆ RTI_RTIGCTRL_COS_RUNNING

#define RTI_RTIGCTRL_COS_RUNNING (0x1U)

◆ RTI_RTIGCTRL_NTUSEL_SHIFT

#define RTI_RTIGCTRL_NTUSEL_SHIFT (16U)

◆ RTI_RTIGCTRL_NTUSEL_MASK

#define RTI_RTIGCTRL_NTUSEL_MASK (0x000f0000U)

◆ RTI_RTITBCTRL_TBEXT_SHIFT

#define RTI_RTITBCTRL_TBEXT_SHIFT (0U)

◆ RTI_RTITBCTRL_TBEXT_MASK

#define RTI_RTITBCTRL_TBEXT_MASK (0x00000001U)

◆ RTI_RTITBCTRL_INC_SHIFT

#define RTI_RTITBCTRL_INC_SHIFT (1U)

◆ RTI_RTITBCTRL_INC_MASK

#define RTI_RTITBCTRL_INC_MASK (0x00000002U)

◆ RTI_RTICAPCTRL_CAPCNTR0_SHIFT

#define RTI_RTICAPCTRL_CAPCNTR0_SHIFT (0U)

◆ RTI_RTICAPCTRL_CAPCNTR0_MASK

#define RTI_RTICAPCTRL_CAPCNTR0_MASK (0x00000001U)

◆ RTI_RTICAPCTRL_CAPCNTR1_SHIFT

#define RTI_RTICAPCTRL_CAPCNTR1_SHIFT (1U)

◆ RTI_RTICAPCTRL_CAPCNTR1_MASK

#define RTI_RTICAPCTRL_CAPCNTR1_MASK (0x00000002U)

◆ RTI_RTICOMPCTRL_COMPSEL0_SHIFT

#define RTI_RTICOMPCTRL_COMPSEL0_SHIFT (0U)

◆ RTI_RTICOMPCTRL_COMPSEL0_MASK

#define RTI_RTICOMPCTRL_COMPSEL0_MASK (0x00000001U)

◆ RTI_RTICOMPCTRL_COMPSEL1_SHIFT

#define RTI_RTICOMPCTRL_COMPSEL1_SHIFT (4U)

◆ RTI_RTICOMPCTRL_COMPSEL1_MASK

#define RTI_RTICOMPCTRL_COMPSEL1_MASK (0x00000010U)

◆ RTI_RTICOMPCTRL_COMPSEL2_SHIFT

#define RTI_RTICOMPCTRL_COMPSEL2_SHIFT (8U)

◆ RTI_RTICOMPCTRL_COMPSEL2_MASK

#define RTI_RTICOMPCTRL_COMPSEL2_MASK (0x00000100U)

◆ RTI_RTICOMPCTRL_COMPSEL3_SHIFT

#define RTI_RTICOMPCTRL_COMPSEL3_SHIFT (12U)

◆ RTI_RTICOMPCTRL_COMPSEL3_MASK

#define RTI_RTICOMPCTRL_COMPSEL3_MASK (0x00001000U)

◆ RTI_RTIFRC0_FRC0_SHIFT

#define RTI_RTIFRC0_FRC0_SHIFT (0U)

◆ RTI_RTIFRC0_FRC0_MASK

#define RTI_RTIFRC0_FRC0_MASK (0xffffffffU)

◆ RTI_RTIUC0_UC0_SHIFT

#define RTI_RTIUC0_UC0_SHIFT (0U)

◆ RTI_RTIUC0_UC0_MASK

#define RTI_RTIUC0_UC0_MASK (0xffffffffU)

◆ RTI_RTICPUC0_CPUC0_SHIFT

#define RTI_RTICPUC0_CPUC0_SHIFT (0U)

◆ RTI_RTICPUC0_CPUC0_MASK

#define RTI_RTICPUC0_CPUC0_MASK (0xffffffffU)

◆ RTI_RTICAFRC0_CAFRC0_SHIFT

#define RTI_RTICAFRC0_CAFRC0_SHIFT (0U)

◆ RTI_RTICAFRC0_CAFRC0_MASK

#define RTI_RTICAFRC0_CAFRC0_MASK (0xffffffffU)

◆ RTI_RTICAUC0_CAUC0_SHIFT

#define RTI_RTICAUC0_CAUC0_SHIFT (0U)

◆ RTI_RTICAUC0_CAUC0_MASK

#define RTI_RTICAUC0_CAUC0_MASK (0xffffffffU)

◆ RTI_RTIFRC1_FRC1_SHIFT

#define RTI_RTIFRC1_FRC1_SHIFT (0U)

◆ RTI_RTIFRC1_FRC1_MASK

#define RTI_RTIFRC1_FRC1_MASK (0xffffffffU)

◆ RTI_RTIUC1_UC1_SHIFT

#define RTI_RTIUC1_UC1_SHIFT (0U)

◆ RTI_RTIUC1_UC1_MASK

#define RTI_RTIUC1_UC1_MASK (0xffffffffU)

◆ RTI_RTICPUC1_CPUC1_SHIFT

#define RTI_RTICPUC1_CPUC1_SHIFT (0U)

◆ RTI_RTICPUC1_CPUC1_MASK

#define RTI_RTICPUC1_CPUC1_MASK (0xffffffffU)

◆ RTI_RTICAFRC1_CAFRC1_SHIFT

#define RTI_RTICAFRC1_CAFRC1_SHIFT (0U)

◆ RTI_RTICAFRC1_CAFRC1_MASK

#define RTI_RTICAFRC1_CAFRC1_MASK (0xffffffffU)

◆ RTI_RTICAUC1_CAUC1_SHIFT

#define RTI_RTICAUC1_CAUC1_SHIFT (0U)

◆ RTI_RTICAUC1_CAUC1_MASK

#define RTI_RTICAUC1_CAUC1_MASK (0xffffffffU)

◆ RTI_RTICOMP0_COMP0_SHIFT

#define RTI_RTICOMP0_COMP0_SHIFT (0U)

◆ RTI_RTICOMP0_COMP0_MASK

#define RTI_RTICOMP0_COMP0_MASK (0xffffffffU)

◆ RTI_RTIUDCP0_UDCP0_SHIFT

#define RTI_RTIUDCP0_UDCP0_SHIFT (0U)

◆ RTI_RTIUDCP0_UDCP0_MASK

#define RTI_RTIUDCP0_UDCP0_MASK (0xffffffffU)

◆ RTI_RTICOMP1_COMP1_SHIFT

#define RTI_RTICOMP1_COMP1_SHIFT (0U)

◆ RTI_RTICOMP1_COMP1_MASK

#define RTI_RTICOMP1_COMP1_MASK (0xffffffffU)

◆ RTI_RTIUDCP1_UDCP1_SHIFT

#define RTI_RTIUDCP1_UDCP1_SHIFT (0U)

◆ RTI_RTIUDCP1_UDCP1_MASK

#define RTI_RTIUDCP1_UDCP1_MASK (0xffffffffU)

◆ RTI_RTICOMP2_COMP2_SHIFT

#define RTI_RTICOMP2_COMP2_SHIFT (0U)

◆ RTI_RTICOMP2_COMP2_MASK

#define RTI_RTICOMP2_COMP2_MASK (0xffffffffU)

◆ RTI_RTIUDCP2_UDCP2_SHIFT

#define RTI_RTIUDCP2_UDCP2_SHIFT (0U)

◆ RTI_RTIUDCP2_UDCP2_MASK

#define RTI_RTIUDCP2_UDCP2_MASK (0xffffffffU)

◆ RTI_RTICOMP3_COMP3_SHIFT

#define RTI_RTICOMP3_COMP3_SHIFT (0U)

◆ RTI_RTICOMP3_COMP3_MASK

#define RTI_RTICOMP3_COMP3_MASK (0xffffffffU)

◆ RTI_RTIUDCP3_UDCP3_SHIFT

#define RTI_RTIUDCP3_UDCP3_SHIFT (0U)

◆ RTI_RTIUDCP3_UDCP3_MASK

#define RTI_RTIUDCP3_UDCP3_MASK (0xffffffffU)

◆ RTI_RTITBLCOMP_TBLCOMP_SHIFT

#define RTI_RTITBLCOMP_TBLCOMP_SHIFT (0U)

◆ RTI_RTITBLCOMP_TBLCOMP_MASK

#define RTI_RTITBLCOMP_TBLCOMP_MASK (0xffffffffU)

◆ RTI_RTITBHCOMP_TBHCOMP_SHIFT

#define RTI_RTITBHCOMP_TBHCOMP_SHIFT (0U)

◆ RTI_RTITBHCOMP_TBHCOMP_MASK

#define RTI_RTITBHCOMP_TBHCOMP_MASK (0xffffffffU)

◆ RTI_RTISETINT_SETINT0_SHIFT

#define RTI_RTISETINT_SETINT0_SHIFT (0U)

◆ RTI_RTISETINT_SETINT0_MASK

#define RTI_RTISETINT_SETINT0_MASK (0x00000001U)

◆ RTI_RTISETINT_SETINT1_SHIFT

#define RTI_RTISETINT_SETINT1_SHIFT (1U)

◆ RTI_RTISETINT_SETINT1_MASK

#define RTI_RTISETINT_SETINT1_MASK (0x00000002U)

◆ RTI_RTISETINT_SETINT2_SHIFT

#define RTI_RTISETINT_SETINT2_SHIFT (2U)

◆ RTI_RTISETINT_SETINT2_MASK

#define RTI_RTISETINT_SETINT2_MASK (0x00000004U)

◆ RTI_RTISETINT_SETINT3_SHIFT

#define RTI_RTISETINT_SETINT3_SHIFT (3U)

◆ RTI_RTISETINT_SETINT3_MASK

#define RTI_RTISETINT_SETINT3_MASK (0x00000008U)

◆ RTI_RTISETINT_SETDMA0_SHIFT

#define RTI_RTISETINT_SETDMA0_SHIFT (8U)

◆ RTI_RTISETINT_SETDMA0_MASK

#define RTI_RTISETINT_SETDMA0_MASK (0x00000100U)

◆ RTI_RTISETINT_SETDMA1_SHIFT

#define RTI_RTISETINT_SETDMA1_SHIFT (9U)

◆ RTI_RTISETINT_SETDMA1_MASK

#define RTI_RTISETINT_SETDMA1_MASK (0x00000200U)

◆ RTI_RTISETINT_SETDMA2_SHIFT

#define RTI_RTISETINT_SETDMA2_SHIFT (10U)

◆ RTI_RTISETINT_SETDMA2_MASK

#define RTI_RTISETINT_SETDMA2_MASK (0x00000400U)

◆ RTI_RTISETINT_SETDMA3_SHIFT

#define RTI_RTISETINT_SETDMA3_SHIFT (11U)

◆ RTI_RTISETINT_SETDMA3_MASK

#define RTI_RTISETINT_SETDMA3_MASK (0x00000800U)

◆ RTI_RTISETINT_SETTBINT_SHIFT

#define RTI_RTISETINT_SETTBINT_SHIFT (16U)

◆ RTI_RTISETINT_SETTBINT_MASK

#define RTI_RTISETINT_SETTBINT_MASK (0x00010000U)

◆ RTI_RTISETINT_SETOVL0INT_SHIFT

#define RTI_RTISETINT_SETOVL0INT_SHIFT (17U)

◆ RTI_RTISETINT_SETOVL0INT_MASK

#define RTI_RTISETINT_SETOVL0INT_MASK (0x00020000U)

◆ RTI_RTISETINT_SETOVL1INT_SHIFT

#define RTI_RTISETINT_SETOVL1INT_SHIFT (18U)

◆ RTI_RTISETINT_SETOVL1INT_MASK

#define RTI_RTISETINT_SETOVL1INT_MASK (0x00040000U)

◆ RTI_RTICLEARINT_CLEARINT0_SHIFT

#define RTI_RTICLEARINT_CLEARINT0_SHIFT (0U)

◆ RTI_RTICLEARINT_CLEARINT0_MASK

#define RTI_RTICLEARINT_CLEARINT0_MASK (0x00000001U)

◆ RTI_RTICLEARINT_CLEARINT1_SHIFT

#define RTI_RTICLEARINT_CLEARINT1_SHIFT (1U)

◆ RTI_RTICLEARINT_CLEARINT1_MASK

#define RTI_RTICLEARINT_CLEARINT1_MASK (0x00000002U)

◆ RTI_RTICLEARINT_CLEARINT2_SHIFT

#define RTI_RTICLEARINT_CLEARINT2_SHIFT (2U)

◆ RTI_RTICLEARINT_CLEARINT2_MASK

#define RTI_RTICLEARINT_CLEARINT2_MASK (0x00000004U)

◆ RTI_RTICLEARINT_CLEARINT3_SHIFT

#define RTI_RTICLEARINT_CLEARINT3_SHIFT (3U)

◆ RTI_RTICLEARINT_CLEARINT3_MASK

#define RTI_RTICLEARINT_CLEARINT3_MASK (0x00000008U)

◆ RTI_RTICLEARINT_CLEARDMA0_SHIFT

#define RTI_RTICLEARINT_CLEARDMA0_SHIFT (8U)

◆ RTI_RTICLEARINT_CLEARDMA0_MASK

#define RTI_RTICLEARINT_CLEARDMA0_MASK (0x00000100U)

◆ RTI_RTICLEARINT_CLEARDMA1_SHIFT

#define RTI_RTICLEARINT_CLEARDMA1_SHIFT (9U)

◆ RTI_RTICLEARINT_CLEARDMA1_MASK

#define RTI_RTICLEARINT_CLEARDMA1_MASK (0x00000200U)

◆ RTI_RTICLEARINT_CLEARDMA2_SHIFT

#define RTI_RTICLEARINT_CLEARDMA2_SHIFT (10U)

◆ RTI_RTICLEARINT_CLEARDMA2_MASK

#define RTI_RTICLEARINT_CLEARDMA2_MASK (0x00000400U)

◆ RTI_RTICLEARINT_CLEARDMA3_SHIFT

#define RTI_RTICLEARINT_CLEARDMA3_SHIFT (11U)

◆ RTI_RTICLEARINT_CLEARDMA3_MASK

#define RTI_RTICLEARINT_CLEARDMA3_MASK (0x00000800U)

◆ RTI_RTICLEARINT_CLEARTBINT_SHIFT

#define RTI_RTICLEARINT_CLEARTBINT_SHIFT (16U)

◆ RTI_RTICLEARINT_CLEARTBINT_MASK

#define RTI_RTICLEARINT_CLEARTBINT_MASK (0x00010000U)

◆ RTI_RTICLEARINT_CLEAROVL0INT_SHIFT

#define RTI_RTICLEARINT_CLEAROVL0INT_SHIFT (17U)

◆ RTI_RTICLEARINT_CLEAROVL0INT_MASK

#define RTI_RTICLEARINT_CLEAROVL0INT_MASK (0x00020000U)

◆ RTI_RTICLEARINT_CLEAROVL1INT_SHIFT

#define RTI_RTICLEARINT_CLEAROVL1INT_SHIFT (18U)

◆ RTI_RTICLEARINT_CLEAROVL1INT_MASK

#define RTI_RTICLEARINT_CLEAROVL1INT_MASK (0x00040000U)

◆ RTI_RTIINTFLAG_INT0_SHIFT

#define RTI_RTIINTFLAG_INT0_SHIFT (0U)

◆ RTI_RTIINTFLAG_INT0_MASK

#define RTI_RTIINTFLAG_INT0_MASK (0x00000001U)

◆ RTI_RTIINTFLAG_INT1_SHIFT

#define RTI_RTIINTFLAG_INT1_SHIFT (1U)

◆ RTI_RTIINTFLAG_INT1_MASK

#define RTI_RTIINTFLAG_INT1_MASK (0x00000002U)

◆ RTI_RTIINTFLAG_INT2_SHIFT

#define RTI_RTIINTFLAG_INT2_SHIFT (2U)

◆ RTI_RTIINTFLAG_INT2_MASK

#define RTI_RTIINTFLAG_INT2_MASK (0x00000004U)

◆ RTI_RTIINTFLAG_INT3_SHIFT

#define RTI_RTIINTFLAG_INT3_SHIFT (3U)

◆ RTI_RTIINTFLAG_INT3_MASK

#define RTI_RTIINTFLAG_INT3_MASK (0x00000008U)

◆ RTI_RTIINTFLAG_TBINT_SHIFT

#define RTI_RTIINTFLAG_TBINT_SHIFT (16U)

◆ RTI_RTIINTFLAG_TBINT_MASK

#define RTI_RTIINTFLAG_TBINT_MASK (0x00010000U)

◆ RTI_RTIINTFLAG_OVL0INT_SHIFT

#define RTI_RTIINTFLAG_OVL0INT_SHIFT (17U)

◆ RTI_RTIINTFLAG_OVL0INT_MASK

#define RTI_RTIINTFLAG_OVL0INT_MASK (0x00020000U)

◆ RTI_RTIINTFLAG_OVL1INT_SHIFT

#define RTI_RTIINTFLAG_OVL1INT_SHIFT (18U)

◆ RTI_RTIINTFLAG_OVL1INT_MASK

#define RTI_RTIINTFLAG_OVL1INT_MASK (0x00040000U)

◆ RTI_RTIDWDCTRL_DWDCTRL_15_0_SHIFT

#define RTI_RTIDWDCTRL_DWDCTRL_15_0_SHIFT (0U)

◆ RTI_RTIDWDCTRL_DWDCTRL_15_0_MASK

#define RTI_RTIDWDCTRL_DWDCTRL_15_0_MASK (0x0000ffffU)

◆ RTI_RTIDWDCTRL_DWDCTRL_31_16_SHIFT

#define RTI_RTIDWDCTRL_DWDCTRL_31_16_SHIFT (16U)

◆ RTI_RTIDWDCTRL_DWDCTRL_31_16_MASK

#define RTI_RTIDWDCTRL_DWDCTRL_31_16_MASK (0xffff0000U)

◆ RTI_RTIDWDCTRL_DWDCTRL_DISABLE

#define RTI_RTIDWDCTRL_DWDCTRL_DISABLE (0x5312ACEDU)

◆ RTI_RTIDWDCTRL_DWDCTRL_ENABLE

#define RTI_RTIDWDCTRL_DWDCTRL_ENABLE (0xA98559DAU)

◆ RTI_RTIDWDPRLD_DWDPRLD_SHIFT

#define RTI_RTIDWDPRLD_DWDPRLD_SHIFT (0U)

◆ RTI_RTIDWDPRLD_DWDPRLD_MASK

#define RTI_RTIDWDPRLD_DWDPRLD_MASK (0x00000fffU)

◆ RTI_RTIDWDPRLD_DWDPRLD_MAX

#define RTI_RTIDWDPRLD_DWDPRLD_MAX (0x0FFFU)

◆ RTI_RTIWDSTATUS_AWDST_SHIFT

#define RTI_RTIWDSTATUS_AWDST_SHIFT (0U)

◆ RTI_RTIWDSTATUS_AWDST_MASK

#define RTI_RTIWDSTATUS_AWDST_MASK (0x00000001U)

◆ RTI_RTIWDSTATUS_DWDST_SHIFT

#define RTI_RTIWDSTATUS_DWDST_SHIFT (1U)

◆ RTI_RTIWDSTATUS_DWDST_MASK

#define RTI_RTIWDSTATUS_DWDST_MASK (0x00000002U)

◆ RTI_RTIWDSTATUS_KEYST_SHIFT

#define RTI_RTIWDSTATUS_KEYST_SHIFT (2U)

◆ RTI_RTIWDSTATUS_KEYST_MASK

#define RTI_RTIWDSTATUS_KEYST_MASK (0x00000004U)

◆ RTI_RTIWDSTATUS_KEYST_CORRECT_KEY

#define RTI_RTIWDSTATUS_KEYST_CORRECT_KEY (0x00000000U)

◆ RTI_RTIWDSTATUS_KEYST_INCORRECT_KEY

#define RTI_RTIWDSTATUS_KEYST_INCORRECT_KEY (0x00000001U)

◆ RTI_RTIWDSTATUS_START_TIME_VIOL_SHIFT

#define RTI_RTIWDSTATUS_START_TIME_VIOL_SHIFT (3U)

◆ RTI_RTIWDSTATUS_START_TIME_VIOL_MASK

#define RTI_RTIWDSTATUS_START_TIME_VIOL_MASK (0x00000008U)

◆ RTI_RTIWDSTATUS_END_TIME_VIOL_SHIFT

#define RTI_RTIWDSTATUS_END_TIME_VIOL_SHIFT (4U)

◆ RTI_RTIWDSTATUS_END_TIME_VIOL_MASK

#define RTI_RTIWDSTATUS_END_TIME_VIOL_MASK (0x00000010U)

◆ RTI_RTIWDSTATUS_DWWD_ST_SHIFT

#define RTI_RTIWDSTATUS_DWWD_ST_SHIFT (5U)

◆ RTI_RTIWDSTATUS_DWWD_ST_MASK

#define RTI_RTIWDSTATUS_DWWD_ST_MASK (0x00000020U)

◆ RTI_RTIWDKEY_WDKEY_SHIFT

#define RTI_RTIWDKEY_WDKEY_SHIFT (0U)

◆ RTI_RTIWDKEY_WDKEY_MASK

#define RTI_RTIWDKEY_WDKEY_MASK (0x0000ffffU)

◆ RTI_RTIWDKEY_WDKEY_FIRST_WRITE

#define RTI_RTIWDKEY_WDKEY_FIRST_WRITE (0x0000E51AU)

◆ RTI_RTIWDKEY_WDKEY_SECOND_WRITE

#define RTI_RTIWDKEY_WDKEY_SECOND_WRITE (0x0000A35CU)

◆ RTI_RTIDWDCNTR_DWDCNTR_15_0_SHIFT

#define RTI_RTIDWDCNTR_DWDCNTR_15_0_SHIFT (0U)

◆ RTI_RTIDWDCNTR_DWDCNTR_15_0_MASK

#define RTI_RTIDWDCNTR_DWDCNTR_15_0_MASK (0x0000ffffU)

◆ RTI_RTIDWDCNTR_DWDCNTR_24_16_SHIFT

#define RTI_RTIDWDCNTR_DWDCNTR_24_16_SHIFT (16U)

◆ RTI_RTIDWDCNTR_DWDCNTR_24_16_MASK

#define RTI_RTIDWDCNTR_DWDCNTR_24_16_MASK (0x01ff0000U)

◆ RTI_RTIDWWDRXNCTRL_DWWDRXN_SHIFT

#define RTI_RTIDWWDRXNCTRL_DWWDRXN_SHIFT (0U)

◆ RTI_RTIDWWDRXNCTRL_DWWDRXN_MASK

#define RTI_RTIDWWDRXNCTRL_DWWDRXN_MASK (0x0000000fU)

◆ RTI_RTIDWWDRXNCTRL_DWWDRXN_RESET

#define RTI_RTIDWWDRXNCTRL_DWWDRXN_RESET (0x5U)

◆ RTI_RTIDWWDRXNCTRL_DWWDRXN_INTERRUPT

#define RTI_RTIDWWDRXNCTRL_DWWDRXN_INTERRUPT (0xAU)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_SHIFT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_SHIFT (0U)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_MASK

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_MASK (0x00ffffffU)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_100_PERCENT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_100_PERCENT (0x00000005U)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_100_PERCENT_SHIFT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_100_PERCENT_SHIFT (0x0)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_50_PERCENT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_50_PERCENT (0x00000050U)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_50_PERCENT_SHIFT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_50_PERCENT_SHIFT (0x1)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_25_PERCENT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_25_PERCENT (0x00000500U)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_25_PERCENT_SHIFT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_25_PERCENT_SHIFT (0x2)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_12_5_PERCENT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_12_5_PERCENT (0x00005000U)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_12_5_PERCENT_SHIFT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_12_5_PERCENT_SHIFT (0x3)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_6_25_PERCENT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_6_25_PERCENT (0x00050000U)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_6_25_PERCENT_SHIFT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_6_25_PERCENT_SHIFT (0x4)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_3_125_PERCENT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_3_125_PERCENT (0x00500000U)

◆ RTI_RTIDWWDSIZECTRL_DWWDSIZE_3_125_PERCENT_SHIFT

#define RTI_RTIDWWDSIZECTRL_DWWDSIZE_3_125_PERCENT_SHIFT (0x5)

◆ RTI_RTIINTCLRENABLE_INTCLRENABLE0_SHIFT

#define RTI_RTIINTCLRENABLE_INTCLRENABLE0_SHIFT (0U)

◆ RTI_RTIINTCLRENABLE_INTCLRENABLE0_MASK

#define RTI_RTIINTCLRENABLE_INTCLRENABLE0_MASK (0x0000000fU)

◆ RTI_RTIINTCLRENABLE_INTCLRENABLE1_SHIFT

#define RTI_RTIINTCLRENABLE_INTCLRENABLE1_SHIFT (8U)

◆ RTI_RTIINTCLRENABLE_INTCLRENABLE1_MASK

#define RTI_RTIINTCLRENABLE_INTCLRENABLE1_MASK (0x00000f00U)

◆ RTI_RTIINTCLRENABLE_INTCLRENABLE2_SHIFT

#define RTI_RTIINTCLRENABLE_INTCLRENABLE2_SHIFT (16U)

◆ RTI_RTIINTCLRENABLE_INTCLRENABLE2_MASK

#define RTI_RTIINTCLRENABLE_INTCLRENABLE2_MASK (0x000f0000U)

◆ RTI_RTIINTCLRENABLE_INTCLRENABLE3_SHIFT

#define RTI_RTIINTCLRENABLE_INTCLRENABLE3_SHIFT (24U)

◆ RTI_RTIINTCLRENABLE_INTCLRENABLE3_MASK

#define RTI_RTIINTCLRENABLE_INTCLRENABLE3_MASK (0x0f000000U)

◆ RTI_RTICOMP0CLR_COMP0CLR_SHIFT

#define RTI_RTICOMP0CLR_COMP0CLR_SHIFT (0U)

◆ RTI_RTICOMP0CLR_COMP0CLR_MASK

#define RTI_RTICOMP0CLR_COMP0CLR_MASK (0xffffffffU)

◆ RTI_RTICOMP1CLR_COMP1CLR_SHIFT

#define RTI_RTICOMP1CLR_COMP1CLR_SHIFT (0U)

◆ RTI_RTICOMP1CLR_COMP1CLR_MASK

#define RTI_RTICOMP1CLR_COMP1CLR_MASK (0xffffffffU)

◆ RTI_RTICOMP2CLR_COMP2CLR_SHIFT

#define RTI_RTICOMP2CLR_COMP2CLR_SHIFT (0U)

◆ RTI_RTICOMP2CLR_COMP2CLR_MASK

#define RTI_RTICOMP2CLR_COMP2CLR_MASK (0xffffffffU)

◆ RTI_RTICOMP3CLR_COMP3CLR_SHIFT

#define RTI_RTICOMP3CLR_COMP3CLR_SHIFT (0U)

◆ RTI_RTICOMP3CLR_COMP3CLR_MASK

#define RTI_RTICOMP3CLR_COMP3CLR_MASK (0xffffffffU)