Introduction

UDMA Low Level Driver J721E SOC specific file.

Macros
#define	UDMA_RING_MODE_INVALID (CSL_RINGACC_RING_MODE_INVALID)
	Invalid Ring Mode. More...

#define	UDMA_NUM_MAPPED_TX_GROUP (0U)
	Number of Mapped TX Group. More...

#define	UDMA_NUM_MAPPED_RX_GROUP (0U)
	Number of Mapped RX Group. More...

#define	UDMA_NUM_UTC_INSTANCE (CSL_NAVSS_UTC_CNT)
	Number of UTC instance. More...

#define	UDMA_RM_NUM_SHARED_RES (4U)
	Total number of shared resources - Free_Flows/Global_Event/IR Intr/VINT. More...

#define	UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)
	Maximum no.of instances to split a shared resource. This should be max(UDMA_NUM_CORE,UDMA_NUM_INST_ID) More...

UDMA Instance ID
UDMA instance ID - Main/MCU NAVSS
#define	UDMA_INST_ID_MAIN_0 (UDMA_INST_ID_0)
	Main NAVSS UDMA instance. More...

#define	UDMA_INST_ID_MCU_0 (UDMA_INST_ID_1)
	MCU NAVSS UDMA instance. More...

#define	UDMA_INST_ID_UDMAP_START (UDMA_INST_ID_0)
	Start of UDMAP instance. More...

#define	UDMA_INST_ID_UDMAP_MAX (UDMA_INST_ID_1)
	Maximum number of UDMAP instance. More...

#define	UDMA_NUM_UDMAP_INST_ID (UDMA_INST_ID_UDMAP_MAX - UDMA_INST_ID_UDMAP_START + 1U)
	Total number of UDMAP instances. More...

#define	UDMA_NUM_BCDMA_INST_ID (0U)
	Total number of BCDMA instances. More...

#define	UDMA_NUM_PKTDMA_INST_ID (0U)
	Total number of PKTDMA instances. More...

#define	UDMA_INST_ID_START (UDMA_INST_ID_0)
	Start of UDMA instance. More...

#define	UDMA_INST_ID_MAX (UDMA_INST_ID_1)
	Maximum number of UDMA instance. More...

#define	UDMA_NUM_INST_ID (UDMA_NUM_UDMAP_INST_ID + UDMA_NUM_BCDMA_INST_ID + UDMA_NUM_PKTDMA_INST_ID)
	Total number of UDMA instances. More...

UDMA SOC Configuration
UDMA Soc Cfg - Flags to indicate the presnce of various SOC specific modules.
#define	UDMA_SOC_CFG_UDMAP_PRESENT (1U)
	Flag to indicate UDMAP module is present or not in the SOC. More...

#define	UDMA_SOC_CFG_BCDMA_PRESENT (0U)
	Flag to indicate BCDMA module is present or not in the SOC. More...

#define	UDMA_SOC_CFG_PKTDMA_PRESENT (0U)
	Flag to indicate PKTDMA module is present or not in the SOC. More...

#define	UDMA_SOC_CFG_PROXY_PRESENT (1U)
	Flag to indicate Proxy is present or not in the SOC. More...

#define	UDMA_SOC_CFG_INTR_ROUTER_PRESENT (1U)
	Flag to indicate Interrupt Router is present or not in the SOC. More...

#define	UDMA_SOC_CFG_CLEC_PRESENT (1U)
	Flag to indicate Clec is present or not in the SOC. More...

#define	UDMA_SOC_CFG_RA_NORMAL_PRESENT (1U)
	Flag to indicate Normal RA is present or not in the SOC. More...

#define	UDMA_SOC_CFG_RA_LCDMA_PRESENT (0U)
	Flag to indicate LCDMA RA is present or not in the SOC. More...

#define	UDMA_SOC_CFG_RING_MON_PRESENT (1U)
	Flag to indicate Ring Monitor is present or not in the SOC. More...

#define	UDMA_SOC_CFG_VPAC1_PRESENT (0U)
	Flag to indicate VPAC1 is present or not in the SOC. More...

#define	UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)
	Flag to indicate the SOC needs ring reset workaround. More...

#define	UDMA_LOCAL_C7X_DRU_PRESENT (0U)

UDMA Tx Channels FDEPTH
UDMA Tx Ch Fdepth - Fdepth of various types of channels present in the SOC.
#define	UDMA_TX_UHC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_UHC_CHANS_FDEPTH)
	Tx Ultra High Capacity Channel FDEPTH. More...

#define	UDMA_TX_HC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_HC_CHANS_FDEPTH)
	Tx High Capacity Channel FDEPTH. More...

#define	UDMA_TX_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_CHANS_FDEPTH)
	Tx Normal Channel FDEPTH. More...

UDMA Ringacc address select (asel) endpoint
List of all valid address select (asel) endpoints in the SOC.
#define	UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (0U)
	Physical address (normal) More...

Core ID specific to a SOC
List of all cores present in the SOC.
#define	UDMA_CORE_ID_MPU1_0 (0U)

#define	UDMA_CORE_ID_MCU2_0 (1U)

#define	UDMA_CORE_ID_MCU2_1 (2U)

#define	UDMA_NUM_MAIN_CORE (3U)

#define	UDMA_CORE_ID_MCU1_0 (UDMA_NUM_MAIN_CORE + 0U)

#define	UDMA_CORE_ID_MCU1_1 (UDMA_NUM_MAIN_CORE + 1U)

#define	UDMA_NUM_MCU_CORE (2U)

#define	UDMA_NUM_CORE (UDMA_NUM_MAIN_CORE + UDMA_NUM_MCU_CORE)

UDMA Resources ID
List of all UDMA Resources Id's.
#define	UDMA_RM_RES_ID_TX_UHC (0U)
	Ultra High Capacity TX and Block Copy Channels. More...

#define	UDMA_RM_RES_ID_TX_HC (1U)
	High Capacity TX and Block Copy Channels. More...

#define	UDMA_RM_RES_ID_TX (2U)
	Normal Capacity TX and Block Copy Channels. More...

#define	UDMA_RM_RES_ID_RX_UHC (3U)
	Ultra High Capacity RX Channels. More...

#define	UDMA_RM_RES_ID_RX_HC (4U)
	High Capacity RX Channels. More...

#define	UDMA_RM_RES_ID_RX (5U)
	Normal Capacity RX Channels. More...

#define	UDMA_RM_RES_ID_RX_FLOW (6U)
	Free Flows. More...

#define	UDMA_RM_RES_ID_RING (7U)
	Free Rings. More...

#define	UDMA_RM_RES_ID_GLOBAL_EVENT (8U)
	Global Event. More...

#define	UDMA_RM_RES_ID_VINTR (9U)
	Virtual Interrupts. More...

#define	UDMA_RM_RES_ID_IR_INTR (10U)
	Interrupt Router Interrupts. More...

#define	UDMA_RM_RES_ID_PROXY (11U)
	Proxy. More...

#define	UDMA_RM_RES_ID_RING_MON (12U)
	Ring Monitors. More...

#define	UDMA_RM_NUM_UDMAP_RES (13U)
	Total number of UDMAP resources. More...

#define	UDMA_RM_DEFAULT_BOARDCFG_NUM_RES (UDMA_RM_NUM_UDMAP_RES)
	Total number of resources for which the range need to be queried from default BoardCfg. More...

Main PSIL Channels
List of all Main PSIL channels and the corresponding counts
#define	UDMA_PSIL_CH_MAIN_CPSW5_TX (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILD_THREAD_OFFSET)

#define	UDMA_PSIL_CH_MAIN_CPSW5_RX (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILS_THREAD_OFFSET)

#define	UDMA_PSIL_CH_MAIN_CPSW5_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILD_THREAD_CNT)

#define	UDMA_PSIL_CH_MAIN_CPSW5_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILS_THREAD_CNT)

Mcu PSIL Channels
List of all Mcu PSIL channels and the corresponding counts
#define	UDMA_PSIL_CH_MCU_CPSW0_TX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET)

#define	UDMA_PSIL_CH_MCU_SAUL0_TX (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_OFFSET)

#define	UDMA_PSIL_CH_MCU_CPSW0_RX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_OFFSET)

#define	UDMA_PSIL_CH_MCU_SAUL0_RX (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_OFFSET)

#define	UDMA_PSIL_CH_MCU_CPSW0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_CNT)

#define	UDMA_PSIL_CH_MCU_SAUL0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_CNT)

#define	UDMA_PSIL_CH_MCU_CPSW0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_CNT)

#define	UDMA_PSIL_CH_MCU_SAUL0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_CNT)

Main TX PDMA Channels
List of all Main PDMA TX channels
#define	UDMA_PDMA_CH_MAIN_MCASP0_TX (CSL_PDMA_CH_MAIN_MCASP0_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCASP1_TX (CSL_PDMA_CH_MAIN_MCASP1_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCASP2_TX (CSL_PDMA_CH_MAIN_MCASP2_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART0_TX (CSL_PDMA_CH_MAIN_UART0_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART1_TX (CSL_PDMA_CH_MAIN_UART1_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART2_TX (CSL_PDMA_CH_MAIN_UART2_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART3_TX (CSL_PDMA_CH_MAIN_UART3_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART4_TX (CSL_PDMA_CH_MAIN_UART4_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART5_TX (CSL_PDMA_CH_MAIN_UART5_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART6_TX (CSL_PDMA_CH_MAIN_UART6_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART7_TX (CSL_PDMA_CH_MAIN_UART7_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART8_TX (CSL_PDMA_CH_MAIN_UART8_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_UART9_TX (CSL_PDMA_CH_MAIN_UART9_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI5_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI5_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI5_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI5_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI6_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI6_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI6_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI6_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI7_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI7_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI7_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCSPI7_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN0_CH0_TX (CSL_PDMA_CH_MAIN_MCAN0_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN0_CH1_TX (CSL_PDMA_CH_MAIN_MCAN0_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN0_CH2_TX (CSL_PDMA_CH_MAIN_MCAN0_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN1_CH0_TX (CSL_PDMA_CH_MAIN_MCAN1_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN1_CH1_TX (CSL_PDMA_CH_MAIN_MCAN1_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN1_CH2_TX (CSL_PDMA_CH_MAIN_MCAN1_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN2_CH0_TX (CSL_PDMA_CH_MAIN_MCAN2_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN2_CH1_TX (CSL_PDMA_CH_MAIN_MCAN2_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN2_CH2_TX (CSL_PDMA_CH_MAIN_MCAN2_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN3_CH0_TX (CSL_PDMA_CH_MAIN_MCAN3_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN3_CH1_TX (CSL_PDMA_CH_MAIN_MCAN3_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN3_CH2_TX (CSL_PDMA_CH_MAIN_MCAN3_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN4_CH0_TX (CSL_PDMA_CH_MAIN_MCAN4_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN4_CH1_TX (CSL_PDMA_CH_MAIN_MCAN4_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN4_CH2_TX (CSL_PDMA_CH_MAIN_MCAN4_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN5_CH0_TX (CSL_PDMA_CH_MAIN_MCAN5_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN5_CH1_TX (CSL_PDMA_CH_MAIN_MCAN5_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN5_CH2_TX (CSL_PDMA_CH_MAIN_MCAN5_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN6_CH0_TX (CSL_PDMA_CH_MAIN_MCAN6_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN6_CH1_TX (CSL_PDMA_CH_MAIN_MCAN6_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN6_CH2_TX (CSL_PDMA_CH_MAIN_MCAN6_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN7_CH0_TX (CSL_PDMA_CH_MAIN_MCAN7_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN7_CH1_TX (CSL_PDMA_CH_MAIN_MCAN7_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN7_CH2_TX (CSL_PDMA_CH_MAIN_MCAN7_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN8_CH0_TX (CSL_PDMA_CH_MAIN_MCAN8_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN8_CH1_TX (CSL_PDMA_CH_MAIN_MCAN8_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN8_CH2_TX (CSL_PDMA_CH_MAIN_MCAN8_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN9_CH0_TX (CSL_PDMA_CH_MAIN_MCAN9_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN9_CH1_TX (CSL_PDMA_CH_MAIN_MCAN9_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN9_CH2_TX (CSL_PDMA_CH_MAIN_MCAN9_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN10_CH0_TX (CSL_PDMA_CH_MAIN_MCAN10_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN10_CH1_TX (CSL_PDMA_CH_MAIN_MCAN10_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN10_CH2_TX (CSL_PDMA_CH_MAIN_MCAN10_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN11_CH0_TX (CSL_PDMA_CH_MAIN_MCAN11_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN11_CH1_TX (CSL_PDMA_CH_MAIN_MCAN11_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN11_CH2_TX (CSL_PDMA_CH_MAIN_MCAN11_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN12_CH0_TX (CSL_PDMA_CH_MAIN_MCAN12_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN12_CH1_TX (CSL_PDMA_CH_MAIN_MCAN12_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN12_CH2_TX (CSL_PDMA_CH_MAIN_MCAN12_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN13_CH0_TX (CSL_PDMA_CH_MAIN_MCAN13_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN13_CH1_TX (CSL_PDMA_CH_MAIN_MCAN13_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX (CSL_PDMA_CH_MAIN_MCAN13_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN14_CH0_TX (CSL_PDMA_CH_MAIN_MCAN14_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN14_CH1_TX (CSL_PDMA_CH_MAIN_MCAN14_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN14_CH2_TX (CSL_PDMA_CH_MAIN_MCAN14_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN15_CH0_TX (CSL_PDMA_CH_MAIN_MCAN15_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN15_CH1_TX (CSL_PDMA_CH_MAIN_MCAN15_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN15_CH2_TX (CSL_PDMA_CH_MAIN_MCAN15_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN16_CH0_TX (CSL_PDMA_CH_MAIN_MCAN16_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN16_CH1_TX (CSL_PDMA_CH_MAIN_MCAN16_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN16_CH2_TX (CSL_PDMA_CH_MAIN_MCAN16_CH2_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN17_CH0_TX (CSL_PDMA_CH_MAIN_MCAN17_CH0_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN17_CH1_TX (CSL_PDMA_CH_MAIN_MCAN17_CH1_TX)

#define	UDMA_PDMA_CH_MAIN_MCAN17_CH2_TX (CSL_PDMA_CH_MAIN_MCAN17_CH2_TX)

MCU TX PDMA Channels
List of all MCU PDMA TX channels
#define	UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX (CSL_PDMA_CH_MCU_MCSPI0_CH0_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI0_CH1_TX (CSL_PDMA_CH_MCU_MCSPI0_CH1_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI0_CH2_TX (CSL_PDMA_CH_MCU_MCSPI0_CH2_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI0_CH3_TX (CSL_PDMA_CH_MCU_MCSPI0_CH3_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI1_CH0_TX (CSL_PDMA_CH_MCU_MCSPI1_CH0_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI1_CH1_TX (CSL_PDMA_CH_MCU_MCSPI1_CH1_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI1_CH2_TX (CSL_PDMA_CH_MCU_MCSPI1_CH2_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI1_CH3_TX (CSL_PDMA_CH_MCU_MCSPI1_CH3_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI2_CH0_TX (CSL_PDMA_CH_MCU_MCSPI2_CH0_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI2_CH1_TX (CSL_PDMA_CH_MCU_MCSPI2_CH1_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI2_CH2_TX (CSL_PDMA_CH_MCU_MCSPI2_CH2_TX)

#define	UDMA_PDMA_CH_MCU_MCSPI2_CH3_TX (CSL_PDMA_CH_MCU_MCSPI2_CH3_TX)

#define	UDMA_PDMA_CH_MCU_MCAN0_CH0_TX (CSL_PDMA_CH_MCU_MCAN0_CH0_TX)

#define	UDMA_PDMA_CH_MCU_MCAN0_CH1_TX (CSL_PDMA_CH_MCU_MCAN0_CH1_TX)

#define	UDMA_PDMA_CH_MCU_MCAN0_CH2_TX (CSL_PDMA_CH_MCU_MCAN0_CH2_TX)

#define	UDMA_PDMA_CH_MCU_MCAN1_CH0_TX (CSL_PDMA_CH_MCU_MCAN1_CH0_TX)

#define	UDMA_PDMA_CH_MCU_MCAN1_CH1_TX (CSL_PDMA_CH_MCU_MCAN1_CH1_TX)

#define	UDMA_PDMA_CH_MCU_MCAN1_CH2_TX (CSL_PDMA_CH_MCU_MCAN1_CH2_TX)

#define	UDMA_PDMA_CH_MCU_UART0_TX (CSL_PDMA_CH_MCU_UART0_CH0_TX)

Main RX PDMA Channels
List of all Main PDMA RX channels
#define	UDMA_PDMA_CH_MAIN_MCASP0_RX (CSL_PDMA_CH_MAIN_MCASP0_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCASP1_RX (CSL_PDMA_CH_MAIN_MCASP1_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCASP2_RX (CSL_PDMA_CH_MAIN_MCASP2_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART0_RX (CSL_PDMA_CH_MAIN_UART0_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART1_RX (CSL_PDMA_CH_MAIN_UART1_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART2_RX (CSL_PDMA_CH_MAIN_UART2_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART3_RX (CSL_PDMA_CH_MAIN_UART3_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART4_RX (CSL_PDMA_CH_MAIN_UART4_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART5_RX (CSL_PDMA_CH_MAIN_UART5_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART6_RX (CSL_PDMA_CH_MAIN_UART6_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART7_RX (CSL_PDMA_CH_MAIN_UART7_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART8_RX (CSL_PDMA_CH_MAIN_UART8_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_UART9_RX (CSL_PDMA_CH_MAIN_UART9_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI5_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI5_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI5_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI5_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI6_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI6_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI6_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI6_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI7_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI7_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI7_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCSPI7_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN0_CH0_RX (CSL_PDMA_CH_MAIN_MCAN0_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN0_CH1_RX (CSL_PDMA_CH_MAIN_MCAN0_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN0_CH2_RX (CSL_PDMA_CH_MAIN_MCAN0_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN1_CH0_RX (CSL_PDMA_CH_MAIN_MCAN1_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN1_CH1_RX (CSL_PDMA_CH_MAIN_MCAN1_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN1_CH2_RX (CSL_PDMA_CH_MAIN_MCAN1_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN2_CH0_RX (CSL_PDMA_CH_MAIN_MCAN2_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN2_CH1_RX (CSL_PDMA_CH_MAIN_MCAN2_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN2_CH2_RX (CSL_PDMA_CH_MAIN_MCAN2_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN3_CH0_RX (CSL_PDMA_CH_MAIN_MCAN3_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN3_CH1_RX (CSL_PDMA_CH_MAIN_MCAN3_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN3_CH2_RX (CSL_PDMA_CH_MAIN_MCAN3_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN4_CH0_RX (CSL_PDMA_CH_MAIN_MCAN4_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN4_CH1_RX (CSL_PDMA_CH_MAIN_MCAN4_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN4_CH2_RX (CSL_PDMA_CH_MAIN_MCAN4_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN5_CH0_RX (CSL_PDMA_CH_MAIN_MCAN5_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN5_CH1_RX (CSL_PDMA_CH_MAIN_MCAN5_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN5_CH2_RX (CSL_PDMA_CH_MAIN_MCAN5_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN6_CH0_RX (CSL_PDMA_CH_MAIN_MCAN6_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN6_CH1_RX (CSL_PDMA_CH_MAIN_MCAN6_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN6_CH2_RX (CSL_PDMA_CH_MAIN_MCAN6_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN7_CH0_RX (CSL_PDMA_CH_MAIN_MCAN7_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN7_CH1_RX (CSL_PDMA_CH_MAIN_MCAN7_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN7_CH2_RX (CSL_PDMA_CH_MAIN_MCAN7_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN8_CH0_RX (CSL_PDMA_CH_MAIN_MCAN8_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN8_CH1_RX (CSL_PDMA_CH_MAIN_MCAN8_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN8_CH2_RX (CSL_PDMA_CH_MAIN_MCAN8_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN9_CH0_RX (CSL_PDMA_CH_MAIN_MCAN9_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN9_CH1_RX (CSL_PDMA_CH_MAIN_MCAN9_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN9_CH2_RX (CSL_PDMA_CH_MAIN_MCAN9_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN10_CH0_RX (CSL_PDMA_CH_MAIN_MCAN10_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN10_CH1_RX (CSL_PDMA_CH_MAIN_MCAN10_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN10_CH2_RX (CSL_PDMA_CH_MAIN_MCAN10_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN11_CH0_RX (CSL_PDMA_CH_MAIN_MCAN11_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN11_CH1_RX (CSL_PDMA_CH_MAIN_MCAN11_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN11_CH2_RX (CSL_PDMA_CH_MAIN_MCAN11_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN12_CH0_RX (CSL_PDMA_CH_MAIN_MCAN12_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN12_CH1_RX (CSL_PDMA_CH_MAIN_MCAN12_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN12_CH2_RX (CSL_PDMA_CH_MAIN_MCAN12_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN13_CH0_RX (CSL_PDMA_CH_MAIN_MCAN13_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN13_CH1_RX (CSL_PDMA_CH_MAIN_MCAN13_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX (CSL_PDMA_CH_MAIN_MCAN13_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN14_CH0_RX (CSL_PDMA_CH_MAIN_MCAN14_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN14_CH1_RX (CSL_PDMA_CH_MAIN_MCAN14_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN14_CH2_RX (CSL_PDMA_CH_MAIN_MCAN14_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN15_CH0_RX (CSL_PDMA_CH_MAIN_MCAN15_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN15_CH1_RX (CSL_PDMA_CH_MAIN_MCAN15_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN15_CH2_RX (CSL_PDMA_CH_MAIN_MCAN15_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN16_CH0_RX (CSL_PDMA_CH_MAIN_MCAN16_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN16_CH1_RX (CSL_PDMA_CH_MAIN_MCAN16_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN16_CH2_RX (CSL_PDMA_CH_MAIN_MCAN16_CH2_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN17_CH0_RX (CSL_PDMA_CH_MAIN_MCAN17_CH0_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN17_CH1_RX (CSL_PDMA_CH_MAIN_MCAN17_CH1_RX)

#define	UDMA_PDMA_CH_MAIN_MCAN17_CH2_RX (CSL_PDMA_CH_MAIN_MCAN17_CH2_RX)

MCU RX PDMA Channels
List of all MCU PDMA RX channels
#define	UDMA_PDMA_CH_MCU_ADC0_CH0_RX (CSL_PDMA_CH_MCU_ADC0_CH0_RX)

#define	UDMA_PDMA_CH_MCU_ADC0_CH1_RX (CSL_PDMA_CH_MCU_ADC0_CH1_RX)

#define	UDMA_PDMA_CH_MCU_ADC1_CH0_RX (CSL_PDMA_CH_MCU_ADC1_CH0_RX)

#define	UDMA_PDMA_CH_MCU_ADC1_CH1_RX (CSL_PDMA_CH_MCU_ADC1_CH1_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI0_CH0_RX (CSL_PDMA_CH_MCU_MCSPI0_CH0_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI0_CH1_RX (CSL_PDMA_CH_MCU_MCSPI0_CH1_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI0_CH2_RX (CSL_PDMA_CH_MCU_MCSPI0_CH2_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI0_CH3_RX (CSL_PDMA_CH_MCU_MCSPI0_CH3_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI1_CH0_RX (CSL_PDMA_CH_MCU_MCSPI1_CH0_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI1_CH1_RX (CSL_PDMA_CH_MCU_MCSPI1_CH1_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI1_CH2_RX (CSL_PDMA_CH_MCU_MCSPI1_CH2_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI1_CH3_RX (CSL_PDMA_CH_MCU_MCSPI1_CH3_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI2_CH0_RX (CSL_PDMA_CH_MCU_MCSPI2_CH0_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI2_CH1_RX (CSL_PDMA_CH_MCU_MCSPI2_CH1_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI2_CH2_RX (CSL_PDMA_CH_MCU_MCSPI2_CH2_RX)

#define	UDMA_PDMA_CH_MCU_MCSPI2_CH3_RX (CSL_PDMA_CH_MCU_MCSPI2_CH3_RX)

#define	UDMA_PDMA_CH_MCU_MCAN0_CH0_RX (CSL_PDMA_CH_MCU_MCAN0_CH0_RX)

#define	UDMA_PDMA_CH_MCU_MCAN0_CH1_RX (CSL_PDMA_CH_MCU_MCAN0_CH1_RX)

#define	UDMA_PDMA_CH_MCU_MCAN0_CH2_RX (CSL_PDMA_CH_MCU_MCAN0_CH2_RX)

#define	UDMA_PDMA_CH_MCU_MCAN1_CH0_RX (CSL_PDMA_CH_MCU_MCAN1_CH0_RX)

#define	UDMA_PDMA_CH_MCU_MCAN1_CH1_RX (CSL_PDMA_CH_MCU_MCAN1_CH1_RX)

#define	UDMA_PDMA_CH_MCU_MCAN1_CH2_RX (CSL_PDMA_CH_MCU_MCAN1_CH2_RX)

#define	UDMA_PDMA_CH_MCU_UART0_RX (CSL_PDMA_CH_MCU_UART0_CH0_RX)

Functions
uint32_t	Udma_getCoreId (void)
	Returns the core ID. More...

uint16_t	Udma_getCoreSciDevId (void)
	Returns the core tisci device ID. More...

uint32_t	Udma_isCacheCoherent (void)
	Returns TRUE if the memory is cache coherent. More...

Macro Definition Documentation

◆ UDMA_INST_ID_MAIN_0

#define UDMA_INST_ID_MAIN_0 (UDMA_INST_ID_0)

Main NAVSS UDMA instance.

◆ UDMA_INST_ID_MCU_0

#define UDMA_INST_ID_MCU_0 (UDMA_INST_ID_1)

MCU NAVSS UDMA instance.

◆ UDMA_INST_ID_UDMAP_START

#define UDMA_INST_ID_UDMAP_START (UDMA_INST_ID_0)

Start of UDMAP instance.

◆ UDMA_INST_ID_UDMAP_MAX

#define UDMA_INST_ID_UDMAP_MAX (UDMA_INST_ID_1)

Maximum number of UDMAP instance.

◆ UDMA_NUM_UDMAP_INST_ID

#define UDMA_NUM_UDMAP_INST_ID (UDMA_INST_ID_UDMAP_MAX - UDMA_INST_ID_UDMAP_START + 1U)

Total number of UDMAP instances.

◆ UDMA_NUM_BCDMA_INST_ID

#define UDMA_NUM_BCDMA_INST_ID (0U)

Total number of BCDMA instances.

◆ UDMA_NUM_PKTDMA_INST_ID

#define UDMA_NUM_PKTDMA_INST_ID (0U)

Total number of PKTDMA instances.

◆ UDMA_INST_ID_START

#define UDMA_INST_ID_START (UDMA_INST_ID_0)

Start of UDMA instance.

◆ UDMA_INST_ID_MAX

#define UDMA_INST_ID_MAX (UDMA_INST_ID_1)

Maximum number of UDMA instance.

◆ UDMA_NUM_INST_ID

#define UDMA_NUM_INST_ID (UDMA_NUM_UDMAP_INST_ID + UDMA_NUM_BCDMA_INST_ID + UDMA_NUM_PKTDMA_INST_ID)

Total number of UDMA instances.

◆ UDMA_SOC_CFG_UDMAP_PRESENT

#define UDMA_SOC_CFG_UDMAP_PRESENT (1U)

Flag to indicate UDMAP module is present or not in the SOC.

◆ UDMA_SOC_CFG_BCDMA_PRESENT

#define UDMA_SOC_CFG_BCDMA_PRESENT (0U)

Flag to indicate BCDMA module is present or not in the SOC.

◆ UDMA_SOC_CFG_PKTDMA_PRESENT

#define UDMA_SOC_CFG_PKTDMA_PRESENT (0U)

Flag to indicate PKTDMA module is present or not in the SOC.

◆ UDMA_SOC_CFG_PROXY_PRESENT

#define UDMA_SOC_CFG_PROXY_PRESENT (1U)

Flag to indicate Proxy is present or not in the SOC.

◆ UDMA_SOC_CFG_INTR_ROUTER_PRESENT

#define UDMA_SOC_CFG_INTR_ROUTER_PRESENT (1U)

Flag to indicate Interrupt Router is present or not in the SOC.

◆ UDMA_SOC_CFG_CLEC_PRESENT

#define UDMA_SOC_CFG_CLEC_PRESENT (1U)

Flag to indicate Clec is present or not in the SOC.

◆ UDMA_SOC_CFG_RA_NORMAL_PRESENT

#define UDMA_SOC_CFG_RA_NORMAL_PRESENT (1U)

Flag to indicate Normal RA is present or not in the SOC.

◆ UDMA_SOC_CFG_RA_LCDMA_PRESENT

#define UDMA_SOC_CFG_RA_LCDMA_PRESENT (0U)

Flag to indicate LCDMA RA is present or not in the SOC.

◆ UDMA_SOC_CFG_RING_MON_PRESENT

#define UDMA_SOC_CFG_RING_MON_PRESENT (1U)

Flag to indicate Ring Monitor is present or not in the SOC.

◆ UDMA_SOC_CFG_VPAC1_PRESENT

#define UDMA_SOC_CFG_VPAC1_PRESENT (0U)

Flag to indicate VPAC1 is present or not in the SOC.

◆ UDMA_SOC_CFG_APPLY_RING_WORKAROUND

#define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)

Flag to indicate the SOC needs ring reset workaround.

◆ UDMA_LOCAL_C7X_DRU_PRESENT

#define UDMA_LOCAL_C7X_DRU_PRESENT (0U)

◆ UDMA_TX_UHC_CHANS_FDEPTH

#define UDMA_TX_UHC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_UHC_CHANS_FDEPTH)

Tx Ultra High Capacity Channel FDEPTH.

◆ UDMA_TX_HC_CHANS_FDEPTH

#define UDMA_TX_HC_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_HC_CHANS_FDEPTH)

Tx High Capacity Channel FDEPTH.

◆ UDMA_TX_CHANS_FDEPTH

#define UDMA_TX_CHANS_FDEPTH (CSL_NAVSS_UDMAP_TX_CHANS_FDEPTH)

Tx Normal Channel FDEPTH.

◆ UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR

#define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR (0U)

Physical address (normal)

◆ UDMA_RING_MODE_INVALID

#define UDMA_RING_MODE_INVALID (CSL_RINGACC_RING_MODE_INVALID)

Invalid Ring Mode.

◆ UDMA_NUM_MAPPED_TX_GROUP

#define UDMA_NUM_MAPPED_TX_GROUP (0U)

Number of Mapped TX Group.

◆ UDMA_NUM_MAPPED_RX_GROUP

#define UDMA_NUM_MAPPED_RX_GROUP (0U)

Number of Mapped RX Group.

◆ UDMA_NUM_UTC_INSTANCE

#define UDMA_NUM_UTC_INSTANCE (CSL_NAVSS_UTC_CNT)

Number of UTC instance.

◆ UDMA_CORE_ID_MPU1_0

#define UDMA_CORE_ID_MPU1_0 (0U)

◆ UDMA_CORE_ID_MCU2_0

#define UDMA_CORE_ID_MCU2_0 (1U)

◆ UDMA_CORE_ID_MCU2_1

#define UDMA_CORE_ID_MCU2_1 (2U)

◆ UDMA_NUM_MAIN_CORE

#define UDMA_NUM_MAIN_CORE (3U)

◆ UDMA_CORE_ID_MCU1_0

#define UDMA_CORE_ID_MCU1_0 (UDMA_NUM_MAIN_CORE + 0U)

◆ UDMA_CORE_ID_MCU1_1

#define UDMA_CORE_ID_MCU1_1 (UDMA_NUM_MAIN_CORE + 1U)

◆ UDMA_NUM_MCU_CORE

#define UDMA_NUM_MCU_CORE (2U)

◆ UDMA_NUM_CORE

#define UDMA_NUM_CORE (UDMA_NUM_MAIN_CORE + UDMA_NUM_MCU_CORE)

◆ UDMA_RM_RES_ID_TX_UHC

#define UDMA_RM_RES_ID_TX_UHC (0U)

Ultra High Capacity TX and Block Copy Channels.

◆ UDMA_RM_RES_ID_TX_HC

#define UDMA_RM_RES_ID_TX_HC (1U)

High Capacity TX and Block Copy Channels.

◆ UDMA_RM_RES_ID_TX

#define UDMA_RM_RES_ID_TX (2U)

Normal Capacity TX and Block Copy Channels.

◆ UDMA_RM_RES_ID_RX_UHC

#define UDMA_RM_RES_ID_RX_UHC (3U)

Ultra High Capacity RX Channels.

◆ UDMA_RM_RES_ID_RX_HC

#define UDMA_RM_RES_ID_RX_HC (4U)

High Capacity RX Channels.

◆ UDMA_RM_RES_ID_RX

#define UDMA_RM_RES_ID_RX (5U)

Normal Capacity RX Channels.

◆ UDMA_RM_RES_ID_RX_FLOW

#define UDMA_RM_RES_ID_RX_FLOW (6U)

Free Flows.

◆ UDMA_RM_RES_ID_RING

#define UDMA_RM_RES_ID_RING (7U)

Free Rings.

◆ UDMA_RM_RES_ID_GLOBAL_EVENT

#define UDMA_RM_RES_ID_GLOBAL_EVENT (8U)

Global Event.

◆ UDMA_RM_RES_ID_VINTR

#define UDMA_RM_RES_ID_VINTR (9U)

Virtual Interrupts.

◆ UDMA_RM_RES_ID_IR_INTR

#define UDMA_RM_RES_ID_IR_INTR (10U)

Interrupt Router Interrupts.

◆ UDMA_RM_RES_ID_PROXY

#define UDMA_RM_RES_ID_PROXY (11U)

Proxy.

◆ UDMA_RM_RES_ID_RING_MON

#define UDMA_RM_RES_ID_RING_MON (12U)

Ring Monitors.

◆ UDMA_RM_NUM_UDMAP_RES

#define UDMA_RM_NUM_UDMAP_RES (13U)

Total number of UDMAP resources.

◆ UDMA_RM_DEFAULT_BOARDCFG_NUM_RES

#define UDMA_RM_DEFAULT_BOARDCFG_NUM_RES (UDMA_RM_NUM_UDMAP_RES)

Total number of resources for which the range need to be queried from default BoardCfg.

◆ UDMA_RM_NUM_SHARED_RES

#define UDMA_RM_NUM_SHARED_RES (4U)

Total number of shared resources - Free_Flows/Global_Event/IR Intr/VINT.

◆ UDMA_RM_SHARED_RES_MAX_INST

#define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)

Maximum no.of instances to split a shared resource. This should be max(UDMA_NUM_CORE,UDMA_NUM_INST_ID)

◆ UDMA_PSIL_CH_MAIN_CPSW5_TX

#define UDMA_PSIL_CH_MAIN_CPSW5_TX (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILD_THREAD_OFFSET)

◆ UDMA_PSIL_CH_MAIN_CPSW5_RX

#define UDMA_PSIL_CH_MAIN_CPSW5_RX (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILS_THREAD_OFFSET)

◆ UDMA_PSIL_CH_MAIN_CPSW5_TX_CNT

#define UDMA_PSIL_CH_MAIN_CPSW5_TX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILD_THREAD_CNT)

◆ UDMA_PSIL_CH_MAIN_CPSW5_RX_CNT

#define UDMA_PSIL_CH_MAIN_CPSW5_RX_CNT (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILS_THREAD_CNT)

◆ UDMA_PSIL_CH_MCU_CPSW0_TX

#define UDMA_PSIL_CH_MCU_CPSW0_TX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_OFFSET)

◆ UDMA_PSIL_CH_MCU_SAUL0_TX

#define UDMA_PSIL_CH_MCU_SAUL0_TX (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_OFFSET)

◆ UDMA_PSIL_CH_MCU_CPSW0_RX

#define UDMA_PSIL_CH_MCU_CPSW0_RX (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_OFFSET)

◆ UDMA_PSIL_CH_MCU_SAUL0_RX

#define UDMA_PSIL_CH_MCU_SAUL0_RX (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_OFFSET)

◆ UDMA_PSIL_CH_MCU_CPSW0_TX_CNT

#define UDMA_PSIL_CH_MCU_CPSW0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILD_THREAD_CNT)

◆ UDMA_PSIL_CH_MCU_SAUL0_TX_CNT

#define UDMA_PSIL_CH_MCU_SAUL0_TX_CNT (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILD_THREAD_CNT)

◆ UDMA_PSIL_CH_MCU_CPSW0_RX_CNT

#define UDMA_PSIL_CH_MCU_CPSW0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_CPSW0_PSILS_THREAD_CNT)

◆ UDMA_PSIL_CH_MCU_SAUL0_RX_CNT

#define UDMA_PSIL_CH_MCU_SAUL0_RX_CNT (CSL_PSILCFG_NAVSS_MCU_SAUL0_PSILS_THREAD_CNT)

◆ UDMA_PDMA_CH_MAIN_MCASP0_TX

#define UDMA_PDMA_CH_MAIN_MCASP0_TX (CSL_PDMA_CH_MAIN_MCASP0_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCASP1_TX

#define UDMA_PDMA_CH_MAIN_MCASP1_TX (CSL_PDMA_CH_MAIN_MCASP1_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCASP2_TX

#define UDMA_PDMA_CH_MAIN_MCASP2_TX (CSL_PDMA_CH_MAIN_MCASP2_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART0_TX

#define UDMA_PDMA_CH_MAIN_UART0_TX (CSL_PDMA_CH_MAIN_UART0_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART1_TX

#define UDMA_PDMA_CH_MAIN_UART1_TX (CSL_PDMA_CH_MAIN_UART1_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART2_TX

#define UDMA_PDMA_CH_MAIN_UART2_TX (CSL_PDMA_CH_MAIN_UART2_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART3_TX

#define UDMA_PDMA_CH_MAIN_UART3_TX (CSL_PDMA_CH_MAIN_UART3_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART4_TX

#define UDMA_PDMA_CH_MAIN_UART4_TX (CSL_PDMA_CH_MAIN_UART4_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART5_TX

#define UDMA_PDMA_CH_MAIN_UART5_TX (CSL_PDMA_CH_MAIN_UART5_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART6_TX

#define UDMA_PDMA_CH_MAIN_UART6_TX (CSL_PDMA_CH_MAIN_UART6_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART7_TX

#define UDMA_PDMA_CH_MAIN_UART7_TX (CSL_PDMA_CH_MAIN_UART7_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART8_TX

#define UDMA_PDMA_CH_MAIN_UART8_TX (CSL_PDMA_CH_MAIN_UART8_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_UART9_TX

#define UDMA_PDMA_CH_MAIN_UART9_TX (CSL_PDMA_CH_MAIN_UART9_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI0_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI0_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI0_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI0_CH3_TX

#define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI1_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI1_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI1_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI1_CH3_TX

#define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI2_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI2_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI2_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI2_CH3_TX

#define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI3_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI3_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI3_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI3_CH3_TX

#define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI4_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI4_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI4_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI4_CH3_TX

#define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI5_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCSPI5_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI5_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCSPI5_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI5_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCSPI5_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI5_CH3_TX

#define UDMA_PDMA_CH_MAIN_MCSPI5_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI6_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCSPI6_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI6_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCSPI6_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI6_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCSPI6_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI6_CH3_TX

#define UDMA_PDMA_CH_MAIN_MCSPI6_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI7_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCSPI7_CH0_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI7_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCSPI7_CH1_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI7_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCSPI7_CH2_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCSPI7_CH3_TX

#define UDMA_PDMA_CH_MAIN_MCSPI7_CH3_TX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN0_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN0_CH0_TX (CSL_PDMA_CH_MAIN_MCAN0_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN0_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN0_CH1_TX (CSL_PDMA_CH_MAIN_MCAN0_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN0_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN0_CH2_TX (CSL_PDMA_CH_MAIN_MCAN0_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN1_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN1_CH0_TX (CSL_PDMA_CH_MAIN_MCAN1_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN1_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN1_CH1_TX (CSL_PDMA_CH_MAIN_MCAN1_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN1_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN1_CH2_TX (CSL_PDMA_CH_MAIN_MCAN1_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN2_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN2_CH0_TX (CSL_PDMA_CH_MAIN_MCAN2_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN2_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN2_CH1_TX (CSL_PDMA_CH_MAIN_MCAN2_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN2_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN2_CH2_TX (CSL_PDMA_CH_MAIN_MCAN2_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN3_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN3_CH0_TX (CSL_PDMA_CH_MAIN_MCAN3_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN3_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN3_CH1_TX (CSL_PDMA_CH_MAIN_MCAN3_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN3_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN3_CH2_TX (CSL_PDMA_CH_MAIN_MCAN3_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN4_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN4_CH0_TX (CSL_PDMA_CH_MAIN_MCAN4_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN4_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN4_CH1_TX (CSL_PDMA_CH_MAIN_MCAN4_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN4_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN4_CH2_TX (CSL_PDMA_CH_MAIN_MCAN4_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN5_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN5_CH0_TX (CSL_PDMA_CH_MAIN_MCAN5_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN5_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN5_CH1_TX (CSL_PDMA_CH_MAIN_MCAN5_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN5_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN5_CH2_TX (CSL_PDMA_CH_MAIN_MCAN5_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN6_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN6_CH0_TX (CSL_PDMA_CH_MAIN_MCAN6_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN6_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN6_CH1_TX (CSL_PDMA_CH_MAIN_MCAN6_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN6_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN6_CH2_TX (CSL_PDMA_CH_MAIN_MCAN6_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN7_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN7_CH0_TX (CSL_PDMA_CH_MAIN_MCAN7_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN7_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN7_CH1_TX (CSL_PDMA_CH_MAIN_MCAN7_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN7_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN7_CH2_TX (CSL_PDMA_CH_MAIN_MCAN7_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN8_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN8_CH0_TX (CSL_PDMA_CH_MAIN_MCAN8_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN8_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN8_CH1_TX (CSL_PDMA_CH_MAIN_MCAN8_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN8_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN8_CH2_TX (CSL_PDMA_CH_MAIN_MCAN8_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN9_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN9_CH0_TX (CSL_PDMA_CH_MAIN_MCAN9_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN9_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN9_CH1_TX (CSL_PDMA_CH_MAIN_MCAN9_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN9_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN9_CH2_TX (CSL_PDMA_CH_MAIN_MCAN9_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN10_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN10_CH0_TX (CSL_PDMA_CH_MAIN_MCAN10_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN10_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN10_CH1_TX (CSL_PDMA_CH_MAIN_MCAN10_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN10_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN10_CH2_TX (CSL_PDMA_CH_MAIN_MCAN10_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN11_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN11_CH0_TX (CSL_PDMA_CH_MAIN_MCAN11_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN11_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN11_CH1_TX (CSL_PDMA_CH_MAIN_MCAN11_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN11_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN11_CH2_TX (CSL_PDMA_CH_MAIN_MCAN11_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN12_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN12_CH0_TX (CSL_PDMA_CH_MAIN_MCAN12_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN12_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN12_CH1_TX (CSL_PDMA_CH_MAIN_MCAN12_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN12_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN12_CH2_TX (CSL_PDMA_CH_MAIN_MCAN12_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN13_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN13_CH0_TX (CSL_PDMA_CH_MAIN_MCAN13_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN13_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN13_CH1_TX (CSL_PDMA_CH_MAIN_MCAN13_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX (CSL_PDMA_CH_MAIN_MCAN13_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN14_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN14_CH0_TX (CSL_PDMA_CH_MAIN_MCAN14_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN14_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN14_CH1_TX (CSL_PDMA_CH_MAIN_MCAN14_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN14_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN14_CH2_TX (CSL_PDMA_CH_MAIN_MCAN14_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN15_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN15_CH0_TX (CSL_PDMA_CH_MAIN_MCAN15_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN15_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN15_CH1_TX (CSL_PDMA_CH_MAIN_MCAN15_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN15_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN15_CH2_TX (CSL_PDMA_CH_MAIN_MCAN15_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN16_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN16_CH0_TX (CSL_PDMA_CH_MAIN_MCAN16_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN16_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN16_CH1_TX (CSL_PDMA_CH_MAIN_MCAN16_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN16_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN16_CH2_TX (CSL_PDMA_CH_MAIN_MCAN16_CH2_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN17_CH0_TX

#define UDMA_PDMA_CH_MAIN_MCAN17_CH0_TX (CSL_PDMA_CH_MAIN_MCAN17_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN17_CH1_TX

#define UDMA_PDMA_CH_MAIN_MCAN17_CH1_TX (CSL_PDMA_CH_MAIN_MCAN17_CH1_TX)

◆ UDMA_PDMA_CH_MAIN_MCAN17_CH2_TX

#define UDMA_PDMA_CH_MAIN_MCAN17_CH2_TX (CSL_PDMA_CH_MAIN_MCAN17_CH2_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX

#define UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX (CSL_PDMA_CH_MCU_MCSPI0_CH0_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI0_CH1_TX

#define UDMA_PDMA_CH_MCU_MCSPI0_CH1_TX (CSL_PDMA_CH_MCU_MCSPI0_CH1_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI0_CH2_TX

#define UDMA_PDMA_CH_MCU_MCSPI0_CH2_TX (CSL_PDMA_CH_MCU_MCSPI0_CH2_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI0_CH3_TX

#define UDMA_PDMA_CH_MCU_MCSPI0_CH3_TX (CSL_PDMA_CH_MCU_MCSPI0_CH3_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI1_CH0_TX

#define UDMA_PDMA_CH_MCU_MCSPI1_CH0_TX (CSL_PDMA_CH_MCU_MCSPI1_CH0_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI1_CH1_TX

#define UDMA_PDMA_CH_MCU_MCSPI1_CH1_TX (CSL_PDMA_CH_MCU_MCSPI1_CH1_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI1_CH2_TX

#define UDMA_PDMA_CH_MCU_MCSPI1_CH2_TX (CSL_PDMA_CH_MCU_MCSPI1_CH2_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI1_CH3_TX

#define UDMA_PDMA_CH_MCU_MCSPI1_CH3_TX (CSL_PDMA_CH_MCU_MCSPI1_CH3_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI2_CH0_TX

#define UDMA_PDMA_CH_MCU_MCSPI2_CH0_TX (CSL_PDMA_CH_MCU_MCSPI2_CH0_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI2_CH1_TX

#define UDMA_PDMA_CH_MCU_MCSPI2_CH1_TX (CSL_PDMA_CH_MCU_MCSPI2_CH1_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI2_CH2_TX

#define UDMA_PDMA_CH_MCU_MCSPI2_CH2_TX (CSL_PDMA_CH_MCU_MCSPI2_CH2_TX)

◆ UDMA_PDMA_CH_MCU_MCSPI2_CH3_TX

#define UDMA_PDMA_CH_MCU_MCSPI2_CH3_TX (CSL_PDMA_CH_MCU_MCSPI2_CH3_TX)

◆ UDMA_PDMA_CH_MCU_MCAN0_CH0_TX

#define UDMA_PDMA_CH_MCU_MCAN0_CH0_TX (CSL_PDMA_CH_MCU_MCAN0_CH0_TX)

◆ UDMA_PDMA_CH_MCU_MCAN0_CH1_TX

#define UDMA_PDMA_CH_MCU_MCAN0_CH1_TX (CSL_PDMA_CH_MCU_MCAN0_CH1_TX)

◆ UDMA_PDMA_CH_MCU_MCAN0_CH2_TX

#define UDMA_PDMA_CH_MCU_MCAN0_CH2_TX (CSL_PDMA_CH_MCU_MCAN0_CH2_TX)

◆ UDMA_PDMA_CH_MCU_MCAN1_CH0_TX

#define UDMA_PDMA_CH_MCU_MCAN1_CH0_TX (CSL_PDMA_CH_MCU_MCAN1_CH0_TX)

◆ UDMA_PDMA_CH_MCU_MCAN1_CH1_TX

#define UDMA_PDMA_CH_MCU_MCAN1_CH1_TX (CSL_PDMA_CH_MCU_MCAN1_CH1_TX)

◆ UDMA_PDMA_CH_MCU_MCAN1_CH2_TX

#define UDMA_PDMA_CH_MCU_MCAN1_CH2_TX (CSL_PDMA_CH_MCU_MCAN1_CH2_TX)

◆ UDMA_PDMA_CH_MCU_UART0_TX

#define UDMA_PDMA_CH_MCU_UART0_TX (CSL_PDMA_CH_MCU_UART0_CH0_TX)

◆ UDMA_PDMA_CH_MAIN_MCASP0_RX

#define UDMA_PDMA_CH_MAIN_MCASP0_RX (CSL_PDMA_CH_MAIN_MCASP0_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCASP1_RX

#define UDMA_PDMA_CH_MAIN_MCASP1_RX (CSL_PDMA_CH_MAIN_MCASP1_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCASP2_RX

#define UDMA_PDMA_CH_MAIN_MCASP2_RX (CSL_PDMA_CH_MAIN_MCASP2_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART0_RX

#define UDMA_PDMA_CH_MAIN_UART0_RX (CSL_PDMA_CH_MAIN_UART0_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART1_RX

#define UDMA_PDMA_CH_MAIN_UART1_RX (CSL_PDMA_CH_MAIN_UART1_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART2_RX

#define UDMA_PDMA_CH_MAIN_UART2_RX (CSL_PDMA_CH_MAIN_UART2_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART3_RX

#define UDMA_PDMA_CH_MAIN_UART3_RX (CSL_PDMA_CH_MAIN_UART3_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART4_RX

#define UDMA_PDMA_CH_MAIN_UART4_RX (CSL_PDMA_CH_MAIN_UART4_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART5_RX

#define UDMA_PDMA_CH_MAIN_UART5_RX (CSL_PDMA_CH_MAIN_UART5_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART6_RX

#define UDMA_PDMA_CH_MAIN_UART6_RX (CSL_PDMA_CH_MAIN_UART6_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART7_RX

#define UDMA_PDMA_CH_MAIN_UART7_RX (CSL_PDMA_CH_MAIN_UART7_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART8_RX

#define UDMA_PDMA_CH_MAIN_UART8_RX (CSL_PDMA_CH_MAIN_UART8_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_UART9_RX

#define UDMA_PDMA_CH_MAIN_UART9_RX (CSL_PDMA_CH_MAIN_UART9_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI0_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCSPI0_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI0_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCSPI0_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI0_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCSPI0_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI0_CH3_RX

#define UDMA_PDMA_CH_MAIN_MCSPI0_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI0_CH3_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI1_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCSPI1_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI1_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCSPI1_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI1_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCSPI1_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI1_CH3_RX

#define UDMA_PDMA_CH_MAIN_MCSPI1_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI1_CH3_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI2_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCSPI2_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI2_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCSPI2_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI2_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCSPI2_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI2_CH3_RX

#define UDMA_PDMA_CH_MAIN_MCSPI2_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI2_CH3_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI3_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCSPI3_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI3_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCSPI3_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI3_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCSPI3_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI3_CH3_RX

#define UDMA_PDMA_CH_MAIN_MCSPI3_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI3_CH3_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI4_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCSPI4_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI4_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCSPI4_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI4_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCSPI4_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI4_CH3_RX

#define UDMA_PDMA_CH_MAIN_MCSPI4_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI4_CH3_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI5_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCSPI5_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI5_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCSPI5_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI5_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCSPI5_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI5_CH3_RX

#define UDMA_PDMA_CH_MAIN_MCSPI5_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI5_CH3_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI6_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCSPI6_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI6_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCSPI6_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI6_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCSPI6_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI6_CH3_RX

#define UDMA_PDMA_CH_MAIN_MCSPI6_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI6_CH3_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI7_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCSPI7_CH0_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI7_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCSPI7_CH1_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI7_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCSPI7_CH2_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCSPI7_CH3_RX

#define UDMA_PDMA_CH_MAIN_MCSPI7_CH3_RX (CSL_PDMA_CH_MAIN_MCSPI7_CH3_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN0_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN0_CH0_RX (CSL_PDMA_CH_MAIN_MCAN0_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN0_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN0_CH1_RX (CSL_PDMA_CH_MAIN_MCAN0_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN0_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN0_CH2_RX (CSL_PDMA_CH_MAIN_MCAN0_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN1_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN1_CH0_RX (CSL_PDMA_CH_MAIN_MCAN1_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN1_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN1_CH1_RX (CSL_PDMA_CH_MAIN_MCAN1_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN1_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN1_CH2_RX (CSL_PDMA_CH_MAIN_MCAN1_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN2_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN2_CH0_RX (CSL_PDMA_CH_MAIN_MCAN2_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN2_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN2_CH1_RX (CSL_PDMA_CH_MAIN_MCAN2_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN2_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN2_CH2_RX (CSL_PDMA_CH_MAIN_MCAN2_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN3_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN3_CH0_RX (CSL_PDMA_CH_MAIN_MCAN3_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN3_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN3_CH1_RX (CSL_PDMA_CH_MAIN_MCAN3_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN3_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN3_CH2_RX (CSL_PDMA_CH_MAIN_MCAN3_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN4_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN4_CH0_RX (CSL_PDMA_CH_MAIN_MCAN4_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN4_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN4_CH1_RX (CSL_PDMA_CH_MAIN_MCAN4_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN4_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN4_CH2_RX (CSL_PDMA_CH_MAIN_MCAN4_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN5_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN5_CH0_RX (CSL_PDMA_CH_MAIN_MCAN5_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN5_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN5_CH1_RX (CSL_PDMA_CH_MAIN_MCAN5_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN5_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN5_CH2_RX (CSL_PDMA_CH_MAIN_MCAN5_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN6_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN6_CH0_RX (CSL_PDMA_CH_MAIN_MCAN6_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN6_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN6_CH1_RX (CSL_PDMA_CH_MAIN_MCAN6_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN6_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN6_CH2_RX (CSL_PDMA_CH_MAIN_MCAN6_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN7_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN7_CH0_RX (CSL_PDMA_CH_MAIN_MCAN7_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN7_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN7_CH1_RX (CSL_PDMA_CH_MAIN_MCAN7_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN7_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN7_CH2_RX (CSL_PDMA_CH_MAIN_MCAN7_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN8_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN8_CH0_RX (CSL_PDMA_CH_MAIN_MCAN8_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN8_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN8_CH1_RX (CSL_PDMA_CH_MAIN_MCAN8_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN8_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN8_CH2_RX (CSL_PDMA_CH_MAIN_MCAN8_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN9_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN9_CH0_RX (CSL_PDMA_CH_MAIN_MCAN9_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN9_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN9_CH1_RX (CSL_PDMA_CH_MAIN_MCAN9_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN9_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN9_CH2_RX (CSL_PDMA_CH_MAIN_MCAN9_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN10_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN10_CH0_RX (CSL_PDMA_CH_MAIN_MCAN10_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN10_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN10_CH1_RX (CSL_PDMA_CH_MAIN_MCAN10_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN10_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN10_CH2_RX (CSL_PDMA_CH_MAIN_MCAN10_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN11_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN11_CH0_RX (CSL_PDMA_CH_MAIN_MCAN11_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN11_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN11_CH1_RX (CSL_PDMA_CH_MAIN_MCAN11_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN11_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN11_CH2_RX (CSL_PDMA_CH_MAIN_MCAN11_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN12_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN12_CH0_RX (CSL_PDMA_CH_MAIN_MCAN12_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN12_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN12_CH1_RX (CSL_PDMA_CH_MAIN_MCAN12_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN12_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN12_CH2_RX (CSL_PDMA_CH_MAIN_MCAN12_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN13_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN13_CH0_RX (CSL_PDMA_CH_MAIN_MCAN13_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN13_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN13_CH1_RX (CSL_PDMA_CH_MAIN_MCAN13_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX (CSL_PDMA_CH_MAIN_MCAN13_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN14_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN14_CH0_RX (CSL_PDMA_CH_MAIN_MCAN14_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN14_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN14_CH1_RX (CSL_PDMA_CH_MAIN_MCAN14_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN14_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN14_CH2_RX (CSL_PDMA_CH_MAIN_MCAN14_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN15_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN15_CH0_RX (CSL_PDMA_CH_MAIN_MCAN15_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN15_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN15_CH1_RX (CSL_PDMA_CH_MAIN_MCAN15_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN15_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN15_CH2_RX (CSL_PDMA_CH_MAIN_MCAN15_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN16_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN16_CH0_RX (CSL_PDMA_CH_MAIN_MCAN16_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN16_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN16_CH1_RX (CSL_PDMA_CH_MAIN_MCAN16_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN16_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN16_CH2_RX (CSL_PDMA_CH_MAIN_MCAN16_CH2_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN17_CH0_RX

#define UDMA_PDMA_CH_MAIN_MCAN17_CH0_RX (CSL_PDMA_CH_MAIN_MCAN17_CH0_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN17_CH1_RX

#define UDMA_PDMA_CH_MAIN_MCAN17_CH1_RX (CSL_PDMA_CH_MAIN_MCAN17_CH1_RX)

◆ UDMA_PDMA_CH_MAIN_MCAN17_CH2_RX

#define UDMA_PDMA_CH_MAIN_MCAN17_CH2_RX (CSL_PDMA_CH_MAIN_MCAN17_CH2_RX)

◆ UDMA_PDMA_CH_MCU_ADC0_CH0_RX

#define UDMA_PDMA_CH_MCU_ADC0_CH0_RX (CSL_PDMA_CH_MCU_ADC0_CH0_RX)

◆ UDMA_PDMA_CH_MCU_ADC0_CH1_RX

#define UDMA_PDMA_CH_MCU_ADC0_CH1_RX (CSL_PDMA_CH_MCU_ADC0_CH1_RX)

◆ UDMA_PDMA_CH_MCU_ADC1_CH0_RX

#define UDMA_PDMA_CH_MCU_ADC1_CH0_RX (CSL_PDMA_CH_MCU_ADC1_CH0_RX)

◆ UDMA_PDMA_CH_MCU_ADC1_CH1_RX

#define UDMA_PDMA_CH_MCU_ADC1_CH1_RX (CSL_PDMA_CH_MCU_ADC1_CH1_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI0_CH0_RX

#define UDMA_PDMA_CH_MCU_MCSPI0_CH0_RX (CSL_PDMA_CH_MCU_MCSPI0_CH0_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI0_CH1_RX

#define UDMA_PDMA_CH_MCU_MCSPI0_CH1_RX (CSL_PDMA_CH_MCU_MCSPI0_CH1_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI0_CH2_RX

#define UDMA_PDMA_CH_MCU_MCSPI0_CH2_RX (CSL_PDMA_CH_MCU_MCSPI0_CH2_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI0_CH3_RX

#define UDMA_PDMA_CH_MCU_MCSPI0_CH3_RX (CSL_PDMA_CH_MCU_MCSPI0_CH3_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI1_CH0_RX

#define UDMA_PDMA_CH_MCU_MCSPI1_CH0_RX (CSL_PDMA_CH_MCU_MCSPI1_CH0_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI1_CH1_RX

#define UDMA_PDMA_CH_MCU_MCSPI1_CH1_RX (CSL_PDMA_CH_MCU_MCSPI1_CH1_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI1_CH2_RX

#define UDMA_PDMA_CH_MCU_MCSPI1_CH2_RX (CSL_PDMA_CH_MCU_MCSPI1_CH2_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI1_CH3_RX

#define UDMA_PDMA_CH_MCU_MCSPI1_CH3_RX (CSL_PDMA_CH_MCU_MCSPI1_CH3_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI2_CH0_RX

#define UDMA_PDMA_CH_MCU_MCSPI2_CH0_RX (CSL_PDMA_CH_MCU_MCSPI2_CH0_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI2_CH1_RX

#define UDMA_PDMA_CH_MCU_MCSPI2_CH1_RX (CSL_PDMA_CH_MCU_MCSPI2_CH1_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI2_CH2_RX

#define UDMA_PDMA_CH_MCU_MCSPI2_CH2_RX (CSL_PDMA_CH_MCU_MCSPI2_CH2_RX)

◆ UDMA_PDMA_CH_MCU_MCSPI2_CH3_RX

#define UDMA_PDMA_CH_MCU_MCSPI2_CH3_RX (CSL_PDMA_CH_MCU_MCSPI2_CH3_RX)

◆ UDMA_PDMA_CH_MCU_MCAN0_CH0_RX

#define UDMA_PDMA_CH_MCU_MCAN0_CH0_RX (CSL_PDMA_CH_MCU_MCAN0_CH0_RX)

◆ UDMA_PDMA_CH_MCU_MCAN0_CH1_RX

#define UDMA_PDMA_CH_MCU_MCAN0_CH1_RX (CSL_PDMA_CH_MCU_MCAN0_CH1_RX)

◆ UDMA_PDMA_CH_MCU_MCAN0_CH2_RX

#define UDMA_PDMA_CH_MCU_MCAN0_CH2_RX (CSL_PDMA_CH_MCU_MCAN0_CH2_RX)

◆ UDMA_PDMA_CH_MCU_MCAN1_CH0_RX

#define UDMA_PDMA_CH_MCU_MCAN1_CH0_RX (CSL_PDMA_CH_MCU_MCAN1_CH0_RX)

◆ UDMA_PDMA_CH_MCU_MCAN1_CH1_RX

#define UDMA_PDMA_CH_MCU_MCAN1_CH1_RX (CSL_PDMA_CH_MCU_MCAN1_CH1_RX)

◆ UDMA_PDMA_CH_MCU_MCAN1_CH2_RX

#define UDMA_PDMA_CH_MCU_MCAN1_CH2_RX (CSL_PDMA_CH_MCU_MCAN1_CH2_RX)

◆ UDMA_PDMA_CH_MCU_UART0_RX

#define UDMA_PDMA_CH_MCU_UART0_RX (CSL_PDMA_CH_MCU_UART0_CH0_RX)

Function Documentation

◆ Udma_getCoreId()

uint32_t Udma_getCoreId ( void )

Returns the core ID.

Returns: Core ID Udma_CoreId

◆ Udma_getCoreSciDevId()

uint16_t Udma_getCoreSciDevId ( void )

Returns the core tisci device ID.

Returns: Core tisci Dev ID

◆ Udma_isCacheCoherent()

uint32_t Udma_isCacheCoherent ( void )

Returns TRUE if the memory is cache coherent.

Returns: TRUE/FALSE