MCUSW
CDD Ipc Configuration

Introduction

This files defines CDD Ipc configuration structures

Functions

void Cdd_IpcNewMessageNotify (uint32 comId)
 New Message notification function. More...
 
void Cdd_IpcNewCtrlMessageNotify (uint32 remoteProcId)
 New Control Message notification function. More...
 
 ISR (Cdd_IpcIrqMbxFromMcu_20)
 A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is used determine presence of data from the remote core in the vring. More...
 
 ISR (Cdd_IpcIrqMbxFromMcu_21)
 ISR for New Message, from MCU 2 1. More...
 

Variables

const uint32 IPC_Mailbox_BasePhyAddr [IPC_MAILBOX_CLUSTER_CNT]
 
Ipc_ProcInfo g_Ipc_mp_procInfo [IPC_MAX_PROCS]
 Processor IDs to name mapping for all processor in Jacinto7. More...
 
Ipc_MailboxInfo g_IPC_MailboxInfo [IPC_MAX_PROCS][IPC_MAX_PROCS]
 
const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC
 
uint8 Cdd_IpcDrvVertIoObj [CDD_IPC_VERTIO_OBJECT_SIZE]
 Communication Channels configured. More...
 

Macros

#define CDD_IPC_PRE_COMPILE_VARIANT   (STD_ON)
 Pre-Compile Build Variant flag. STD_ON for VariantPreCompile / STD_OFF for VariantPostBuild. More...
 
#define CDD_IPC_DEV_ERROR_DETECT   (STD_ON)
 Enable/disable CDD Ipc dev detect error. More...
 
#define CDD_IPC_ISR_TYPE   (CDD_IPC_ISR_CAT2)
 ISR type. More...
 
#define CDD_IPC_NEW_MSG_NTFY_FXN   Cdd_IpcNewMessageNotify
 
#define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN   Cdd_IpcNewCtrlMessageNotify
 

Pre-Compile Switches for API Services

#define CDD_IPC_VERSION_INFO_API   (STD_ON)
 Enable/disable version info API. More...
 
#define CDD_IPC_DEINIT_API   (STD_ON)
 Enable/disable De Initialization API. More...
 
#define CDD_IPC_ANNOUNCE_API   (STD_ON)
 Enable/disable Service Announcement API. More...
 
#define CDD_IPC_REGISTER_READBACK_API   (STD_ON)
 Enable/disable Critical Register read back API. More...
 
#define CDD_IPC_SAFETY_DIAGNOSTIC_API   (STD_ON)
 Enable/disable safety diagnostics API. More...
 
#define CDD_IPC_IS_INIT_DONE_API   (STD_ON)
 Enable/disable Cdd_IpcIsInitDone API. More...
 
#define CDD_IPC_GET_MAX_MSG_SIZE_API   (STD_ON)
 Enable/disable Cdd_IpcGetMaxMsgSize API. More...
 

Dependency configurations

#define CDD_IPC_OS_COUNTER_ID   ((CounterType)OsCounter_0)
 Counter ID for counter used to count wait ticks. More...
 

Cdd Ipc DEM Error codes to report

Pre-compile switches for enabling/disabling DEM events

#define DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT   (0xFFFFU)
 
#define CDD_IPC_DEM_NO_EVENT   DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT
 
#define CDD_IPC_E_HARDWARE_ERROR   (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)
 Hardware failed. More...
 

CORE Names

#define CDD_IPC_CORE_MCU1_0   (1U)
 
#define CDD_IPC_CORE_MCU1_1   (2U)
 
#define CDD_IPC_CORE_MCU2_0   (3U)
 
#define CDD_IPC_CORE_MCU2_1   (4U)
 
#define CDD_IPC_CORE_MCU3_0   (5U)
 
#define CDD_IPC_CORE_MCU3_1   (6U)
 
#define CDD_IPC_CORE_C66X_1   (7U)
 
#define CDD_IPC_CORE_C66X_2   (8U)
 
#define CDD_IPC_CORE_C7X_1   (9U)
 
#define CDD_IPC_CORE_MAX_PROCS   (11U)
 
#define CDD_IPC_OWN_CORE_ID   (CDD_IPC_CORE_MCU1_0)
 Used core identifiers. More...
 
#define CDD_IPC_REMOTE_CORE_MCU2_0_USED
 
#define CDD_IPC_REMOTE_CORE_MCU2_1_USED
 

VirtIO Object

#define CDD_IPC_VERTIO_OBJECT_SIZE   (0x1000U)
 

Communication Channel ID & Configured Buffer sizes

#define CddIpcConf_IpcComChanId_Cdd_IpcMcu20   (0U)
 
#define CddIpcConf_IpcComChanId_Cdd_IpcMcu21   (1U)
 
#define CDD_IPC_RPMSG_OBJ_SIZE   (256U)
 
#define CDD_IPC_CH_0_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
 
#define CDD_IPC_CH_1_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
 
#define CDD_IPC_MAX_CHANNEL_CFG   (2U)
 
#define IPC_VRING_BUFFER_SIZE   (0x1C00000U)
 VRing Buffer Size required for all core combinations. More...
 
#define IPC_MPU1_0   (0U)
 Core definitions. More...
 
#define IPC_MCU1_0   (1U)
 
#define IPC_MCU1_1   (2U)
 
#define IPC_MCU2_0   (3U)
 
#define IPC_MCU2_1   (4U)
 
#define IPC_MCU3_0   (5U)
 
#define IPC_MCU3_1   (6U)
 
#define IPC_C66X_1   (7U)
 
#define IPC_C66X_2   (8U)
 
#define IPC_C7X_1   (9U)
 
#define IPC_MPU1_1   (10U)
 
#define IPC_MAX_PROCS   (11U)
 
#define CDD_IPC_CORE_ID_MAX   (11U)
 IPC maximum possible core ID. More...
 
#define IPC_MAILBOX_CLUSTER_CNT   (12U)
 

Macro Definition Documentation

◆ CDD_IPC_PRE_COMPILE_VARIANT

#define CDD_IPC_PRE_COMPILE_VARIANT   (STD_ON)

Pre-Compile Build Variant flag. STD_ON for VariantPreCompile / STD_OFF for VariantPostBuild.

◆ CDD_IPC_DEV_ERROR_DETECT

#define CDD_IPC_DEV_ERROR_DETECT   (STD_ON)

Enable/disable CDD Ipc dev detect error.

◆ CDD_IPC_ISR_TYPE

#define CDD_IPC_ISR_TYPE   (CDD_IPC_ISR_CAT2)

ISR type.

◆ CDD_IPC_VERSION_INFO_API

#define CDD_IPC_VERSION_INFO_API   (STD_ON)

Enable/disable version info API.

◆ CDD_IPC_DEINIT_API

#define CDD_IPC_DEINIT_API   (STD_ON)

Enable/disable De Initialization API.

◆ CDD_IPC_ANNOUNCE_API

#define CDD_IPC_ANNOUNCE_API   (STD_ON)

Enable/disable Service Announcement API.

◆ CDD_IPC_REGISTER_READBACK_API

#define CDD_IPC_REGISTER_READBACK_API   (STD_ON)

Enable/disable Critical Register read back API.

◆ CDD_IPC_SAFETY_DIAGNOSTIC_API

#define CDD_IPC_SAFETY_DIAGNOSTIC_API   (STD_ON)

Enable/disable safety diagnostics API.

◆ CDD_IPC_IS_INIT_DONE_API

#define CDD_IPC_IS_INIT_DONE_API   (STD_ON)

Enable/disable Cdd_IpcIsInitDone API.

◆ CDD_IPC_GET_MAX_MSG_SIZE_API

#define CDD_IPC_GET_MAX_MSG_SIZE_API   (STD_ON)

Enable/disable Cdd_IpcGetMaxMsgSize API.

◆ CDD_IPC_OS_COUNTER_ID

#define CDD_IPC_OS_COUNTER_ID   ((CounterType)OsCounter_0)

Counter ID for counter used to count wait ticks.

◆ DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT

#define DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT   (0xFFFFU)

◆ CDD_IPC_DEM_NO_EVENT

#define CDD_IPC_DEM_NO_EVENT   DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT

◆ CDD_IPC_E_HARDWARE_ERROR

#define CDD_IPC_E_HARDWARE_ERROR   (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)

Hardware failed.

◆ CDD_IPC_CORE_MCU1_0

#define CDD_IPC_CORE_MCU1_0   (1U)

ARM MCU R5F - core0

◆ CDD_IPC_CORE_MCU1_1

#define CDD_IPC_CORE_MCU1_1   (2U)

ARM MCU R5F - core1

◆ CDD_IPC_CORE_MCU2_0

#define CDD_IPC_CORE_MCU2_0   (3U)

ARM Main R5F - core0

◆ CDD_IPC_CORE_MCU2_1

#define CDD_IPC_CORE_MCU2_1   (4U)

ARM Main R5F - core1

◆ CDD_IPC_CORE_MCU3_0

#define CDD_IPC_CORE_MCU3_0   (5U)

ARM Main R5F - core2

◆ CDD_IPC_CORE_MCU3_1

#define CDD_IPC_CORE_MCU3_1   (6U)

ARM Main R5F - core3

◆ CDD_IPC_CORE_C66X_1

#define CDD_IPC_CORE_C66X_1   (7U)

DSP C66x - core0

◆ CDD_IPC_CORE_C66X_2

#define CDD_IPC_CORE_C66X_2   (8U)

DSP C66x - core1

◆ CDD_IPC_CORE_C7X_1

#define CDD_IPC_CORE_C7X_1   (9U)

DSP C7x - core0

◆ CDD_IPC_CORE_MAX_PROCS

#define CDD_IPC_CORE_MAX_PROCS   (11U)

MAX processors

◆ CDD_IPC_OWN_CORE_ID

#define CDD_IPC_OWN_CORE_ID   (CDD_IPC_CORE_MCU1_0)

Used core identifiers.

Own core ID

◆ CDD_IPC_REMOTE_CORE_MCU2_0_USED

#define CDD_IPC_REMOTE_CORE_MCU2_0_USED

Remote core MCU 2 0 is being used

◆ CDD_IPC_REMOTE_CORE_MCU2_1_USED

#define CDD_IPC_REMOTE_CORE_MCU2_1_USED

Remote core MCU 2 1 is being used

◆ CDD_IPC_VERTIO_OBJECT_SIZE

#define CDD_IPC_VERTIO_OBJECT_SIZE   (0x1000U)

◆ CddIpcConf_IpcComChanId_Cdd_IpcMcu20

#define CddIpcConf_IpcComChanId_Cdd_IpcMcu20   (0U)

Channel identifiers

◆ CddIpcConf_IpcComChanId_Cdd_IpcMcu21

#define CddIpcConf_IpcComChanId_Cdd_IpcMcu21   (1U)

Channel identifiers

◆ CDD_IPC_RPMSG_OBJ_SIZE

#define CDD_IPC_RPMSG_OBJ_SIZE   (256U)

Size of RP Message Object

◆ CDD_IPC_CH_0_BUFF_SIZE

#define CDD_IPC_CH_0_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)

Size of buffer allocated to the channel

◆ CDD_IPC_CH_1_BUFF_SIZE

#define CDD_IPC_CH_1_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)

Size of buffer allocated to the channel

◆ CDD_IPC_MAX_CHANNEL_CFG

#define CDD_IPC_MAX_CHANNEL_CFG   (2U)

Maximum number of communication channels configured

◆ IPC_VRING_BUFFER_SIZE

#define IPC_VRING_BUFFER_SIZE   (0x1C00000U)

VRing Buffer Size required for all core combinations.

◆ IPC_MPU1_0

#define IPC_MPU1_0   (0U)

Core definitions.

ARM A72 - VM0

◆ IPC_MCU1_0

#define IPC_MCU1_0   (1U)

ARM MCU R5F - core0

◆ IPC_MCU1_1

#define IPC_MCU1_1   (2U)

ARM MCU R5F - core1

◆ IPC_MCU2_0

#define IPC_MCU2_0   (3U)

ARM Main R5F - core0

◆ IPC_MCU2_1

#define IPC_MCU2_1   (4U)

ARM Main R5F - core1

◆ IPC_MCU3_0

#define IPC_MCU3_0   (5U)

ARM Main R5F - core2

◆ IPC_MCU3_1

#define IPC_MCU3_1   (6U)

ARM Main R5F - core3

◆ IPC_C66X_1

#define IPC_C66X_1   (7U)

DSP C66x - core0

◆ IPC_C66X_2

#define IPC_C66X_2   (8U)

DSP C66x - core1

◆ IPC_C7X_1

#define IPC_C7X_1   (9U)

DSP C7x - core0

◆ IPC_MPU1_1

#define IPC_MPU1_1   (10U)

ARM A72 - VM1

◆ IPC_MAX_PROCS

#define IPC_MAX_PROCS   (11U)

Maximum Processors

◆ CDD_IPC_CORE_ID_MAX

#define CDD_IPC_CORE_ID_MAX   (11U)

IPC maximum possible core ID.

◆ IPC_MAILBOX_CLUSTER_CNT

#define IPC_MAILBOX_CLUSTER_CNT   (12U)

◆ CDD_IPC_NEW_MSG_NTFY_FXN

#define CDD_IPC_NEW_MSG_NTFY_FXN   Cdd_IpcNewMessageNotify

◆ CDD_IPC_NEW_CTRL_MSG_NTFY_FXN

#define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN   Cdd_IpcNewCtrlMessageNotify

Function Documentation

◆ Cdd_IpcNewMessageNotify()

void Cdd_IpcNewMessageNotify ( uint32  comId)

New Message notification function.

◆ Cdd_IpcNewCtrlMessageNotify()

void Cdd_IpcNewCtrlMessageNotify ( uint32  remoteProcId)

New Control Message notification function.

◆ ISR() [1/2]

ISR ( Cdd_IpcIrqMbxFromMcu_20  )

A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is used determine presence of data from the remote core in the vring.

Typically, we would have 1 interrupt for each remote core. Due to system resource needs, multiple remote cores could use a single interrupt.

Depending on the SoC variant, the isr to registered with interrupt will change. Please refer CDD IPC example application to associate right ISR with interrupt.ISR for New Message, from MCU 2 0

◆ ISR() [2/2]

ISR ( Cdd_IpcIrqMbxFromMcu_21  )

ISR for New Message, from MCU 2 1.

Variable Documentation

◆ IPC_Mailbox_BasePhyAddr

const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT]

◆ g_Ipc_mp_procInfo

Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS]

Processor IDs to name mapping for all processor in Jacinto7.

◆ g_IPC_MailboxInfo

Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS]

◆ CddIpcConfiguraions_PC

const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC

◆ Cdd_IpcDrvVertIoObj

uint8 Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE]

Communication Channels configured.