MCUSW
Cdd_IpcCfg.h
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62 
71 /******************************************************************************
72  Project : CDD_IPC_CONFIG_J721E
73  Date : 2022-08-21 17:35:15
74  SW Ver : 1.3.3
75  Module Rele Ver : AUTOSAR 4.3.1 0
76 
77  This file is generated by EB Tresos
78  Do not modify this file,otherwise the software may behave in unexpected way.
79 ******************************************************************************/
80 
88 #ifndef CDD_IPC_CFG_H_
89 #define CDD_IPC_CFG_H_
90 /* Generic requirements covered mapping */
91 /*
92  * Design : DES_CDD_IPC_020
93  */
94 /*
95  * Requirements : MCAL-3698
96  */
97 
98 /* ========================================================================== */
99 /* Include Files */
100 /* ========================================================================== */
101 
102 #include "Dem.h"
103 #include "Os.h"
104 #include <CddIpc/ipc_baremetal_hw/include/ipc_config.h>
105 
106 
107 #ifdef __cplusplus
108 extern "C" {
109 #endif
110 
111 /* ========================================================================== */
112 /* Macros & Typedefs */
113 /* ========================================================================== */
114 /*
115  * Design : DES_CDD_IPC_004, DES_CDD_IPC_002, DES_CDD_IPC_017
116  */
117 /*
118  * Requirements : MCAL-921, MCAL-3703
119  */
124 #define CDD_IPC_PRE_COMPILE_VARIANT (STD_ON)
125 /*
126  * Design : DES_CDD_IPC_012
127  */
128 /*
129  * Requirements : MCAL-3693
130  */
132 #define CDD_IPC_DEV_ERROR_DETECT (STD_ON)
133 /*
134  * Design : DES_CDD_IPC_012
135  */
136 /*
137  * Requirements : MCAL-3692
138  */
140 #define CDD_IPC_ISR_TYPE (CDD_IPC_ISR_CAT2)
141 
146 /*
147  * Design : DES_CDD_IPC_012
148  */
149 /*
150  * Requirements : MCAL-3741
151  */
153 #define CDD_IPC_VERSION_INFO_API (STD_ON)
154 /*
155  * Design : DES_CDD_IPC_012
156  */
157 /*
158  * Requirements : MCAL-3688
159  */
161 #define CDD_IPC_DEINIT_API (STD_ON)
162 /*
163  * Design : DES_CDD_IPC_012
164  */
165 /*
166  * Requirements : MCAL-3689
167  */
169 #define CDD_IPC_ANNOUNCE_API (STD_ON)
170 /*
171  * Design : DES_CDD_IPC_005, DES_CDD_IPC_012
172  */
173 /*
174  * Requirements : MCAL-3687
175  */
177 #define CDD_IPC_REGISTER_READBACK_API (STD_ON)
178 /*
179  * Design :
180  */
181 /*
182  * Requirements : MCAL-8266
183  */
185 #define CDD_IPC_SAFETY_DIAGNOSTIC_API (STD_ON)
186 /*
187  * Design : DES_CDD_IPC_040
188  */
189 /*
190  * Requirements : MCAL-4452
191  */
192 
194 #define CDD_IPC_IS_INIT_DONE_API (STD_ON)
195 
196 /*
197  * Design : DES_CDD_IPC_041
198  */
199 /*
200  * Requirements : MCAL-4453
201  */
202 
204 #define CDD_IPC_GET_MAX_MSG_SIZE_API (STD_ON)
205 
206 
207 /* @} */
208 
213 /*
214  * Design : DES_CDD_IPC_012
215  */
216 /*
217  * Requirements : MCAL-3694, MCAL-3694
218  */
220 #define CDD_IPC_OS_COUNTER_ID ((CounterType)OsCounter_0)
221 
228 /*
229  * Design : DES_CDD_IPC_020
230  */
231 /*
232  * Requirements : MCAL-3693
233  */
234 #define DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT (0xFFFFU)
235 #define CDD_IPC_DEM_NO_EVENT DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT
236 
237 #ifndef CDD_IPC_E_HARDWARE_ERROR
238 
239 #define CDD_IPC_E_HARDWARE_ERROR (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)
240 #endif
241 /* @} */
242 
247 /*
248  * Design : DES_CDD_IPC_018
249  */
250 /*
251  * Requirements : MCAL-3699, MCAL-3700
252  */
253 #define CDD_IPC_CORE_MCU1_0 (1U)
254 
255 #define CDD_IPC_CORE_MCU1_1 (2U)
256 
257 #define CDD_IPC_CORE_MCU2_0 (3U)
258 
259 #define CDD_IPC_CORE_MCU2_1 (4U)
260 
261 #define CDD_IPC_CORE_MCU3_0 (5U)
262 
263 #define CDD_IPC_CORE_MCU3_1 (6U)
264 
265 #define CDD_IPC_CORE_C66X_1 (7U)
266 
267 #define CDD_IPC_CORE_C66X_2 (8U)
268 
269 #define CDD_IPC_CORE_C7X_1 (9U)
270 
271 #define CDD_IPC_CORE_MAX_PROCS (11U)
272 
275 #define CDD_IPC_OWN_CORE_ID (CDD_IPC_CORE_MCU1_0)
276 
277 #define CDD_IPC_REMOTE_CORE_MCU2_0_USED
278 
279 #define CDD_IPC_REMOTE_CORE_MCU2_1_USED
280 
282 /* @} */
283 
284 
289 /*
290  * Design : DES_CDD_IPC_005, DES_CDD_IPC_016
291  */
292 /*
293  * Requirements : MCAL-3686,
294  */
295 #define CDD_IPC_VERTIO_OBJECT_SIZE (0x1000U)
296  /* @} */
297 
302 /*
303  * Design : DES_CDD_IPC_016
304  */
305 /*
306  * Requirements : MCAL-3686,
307  */
308 #define CddIpcConf_IpcComChanId_Cdd_IpcMcu20 (0U)
309 
310 #define CddIpcConf_IpcComChanId_Cdd_IpcMcu21 (1U)
311 
313 /*
314  * Design : DES_CDD_IPC_016
315  */
316 /*
317  * Requirements : MCAL-3755, MCAL-3682
318  */
319 #define CDD_IPC_RPMSG_OBJ_SIZE (256U)
320 
321 #define CDD_IPC_CH_0_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
322 
323 #define CDD_IPC_CH_1_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
324 
325 #define CDD_IPC_MAX_CHANNEL_CFG (2U)
326 
332 #define IPC_VRING_BUFFER_SIZE (0x1C00000U)
333 
335 #define IPC_MPU1_0 (0U)
336 #define IPC_MCU1_0 (1U)
337 #define IPC_MCU1_1 (2U)
338 #define IPC_MCU2_0 (3U)
339 #define IPC_MCU2_1 (4U)
340 #define IPC_MCU3_0 (5U)
341 #define IPC_MCU3_1 (6U)
342 #define IPC_C66X_1 (7U)
343 #define IPC_C66X_2 (8U)
344 #define IPC_C7X_1 (9U)
345 #define IPC_MPU1_1 (10U)
346 #define IPC_MAX_PROCS (11U)
350 #define CDD_IPC_CORE_ID_MAX (11U)
351 
352 #define IPC_MAILBOX_CLUSTER_CNT (12U)
353 
354 /* @} */
355 /* ========================================================================== */
356 /* Globals Variables */
357 /* ========================================================================== */
358 /* Mailbox Cluster Base Address */
360 
364 extern Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS];
365 
366 extern Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS];
367 
368 /* ========================================================================== */
369 /* Function Declarations */
370 /* ========================================================================== */
371 /*
372  * Design : DES_CDD_IPC_002, DES_CDD_IPC_017
373  */
374 /*
375  * Requirements : MCAL-3703
376  */
377 extern const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC;
378 
383 /*
384  * Design : DES_CDD_IPC_012, DES_CDD_IPC_026
385  */
386 /*
387  * Requirements : MCAL-3701, MCAL-3691
388  */
389 extern void Cdd_IpcNewMessageNotify(uint32 comId);
390 
391 #define CDD_IPC_NEW_MSG_NTFY_FXN Cdd_IpcNewMessageNotify
392 
393 #if (STD_ON == CDD_IPC_ANNOUNCE_API)
394 
399 /*
400  * Design : DES_CDD_IPC_039
401  */
402 /*
403  * Requirements : MCAL-4067, MCAL-4066
404  */
405 extern void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId);
406 
407 #define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN Cdd_IpcNewCtrlMessageNotify
408 
409 #endif /* STD_ON == CDD_IPC_ANNOUNCE_API */
410 
411 /*
412  * Design : DES_CDD_IPC_013
413  */
414 /*
415  * Requirements : MCAL-3674
416  */
422 
437 ISR( Cdd_IpcIrqMbxFromMcu_20 );
439 ISR( Cdd_IpcIrqMbxFromMcu_21 );
440 
441 #ifdef __cplusplus
442 }
443 #endif
444 
445 #endif /* #ifndef CDD_IPC_CFG_H_ */
446 
447 /* @} */
#define CDD_IPC_VERTIO_OBJECT_SIZE
Definition: Cdd_IpcCfg.h:295
const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT]
ISR(Cdd_IpcIrqMbxFromMcu_20)
A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is...
#define IPC_MAX_PROCS
Definition: Cdd_IpcCfg.h:346
void Cdd_IpcNewMessageNotify(uint32 comId)
New Message notification function.
Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS]
const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC
Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS]
Processor IDs to name mapping for all processor in Jacinto7.
#define IPC_MAILBOX_CLUSTER_CNT
Definition: Cdd_IpcCfg.h:352
void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId)
New Control Message notification function.
uint8 Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE]
Communication Channels configured.