SDL API Guide for J7200
sdlr_edc_ctl.h
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1 /********************************************************************
2  * Copyright (C) 2021 Texas Instruments Incorporated.
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30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * Name : sdlr_edc_ctl.h
33 */
34 #ifndef SDLR_EDC_CTL_H_
35 #define SDLR_EDC_CTL_H_
36 
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 #include <sdlr.h>
42 #include <stdint.h>
43 
44 /**************************************************************************
45 * Hardware Region : EDC controller serial VBUS MMRs
46 **************************************************************************/
47 
48 
49 /**************************************************************************
50 * Register Overlay Structure
51 **************************************************************************/
52 
53 typedef struct {
54  volatile uint8_t Resv_16[16];
55  volatile uint32_t REVISION; /* Revision register */
56  volatile uint32_t CONTROL; /* Control register */
57  volatile uint32_t ERR_INJECT1; /* Error inject 1 register */
58  volatile uint32_t ERR_INJECT2; /* Error inject 2 register */
59  volatile uint32_t ERR_STATUS1; /* Error status 1 register */
60  volatile uint32_t ERR_STATUS2; /* Error status 2 register */
61 } SDL_edc_ctlRegs;
62 
63 
64 /**************************************************************************
65 * Register Macros
66 **************************************************************************/
67 
68 #define SDL_EDC_CTL_REVISION (0x00000010U)
69 #define SDL_EDC_CTL_CONTROL (0x00000014U)
70 #define SDL_EDC_CTL_ERR_INJECT1 (0x00000018U)
71 #define SDL_EDC_CTL_ERR_INJECT2 (0x0000001CU)
72 #define SDL_EDC_CTL_ERR_STATUS1 (0x00000020U)
73 #define SDL_EDC_CTL_ERR_STATUS2 (0x00000024U)
74 
75 /**************************************************************************
76 * Field Definition Macros
77 **************************************************************************/
78 
79 
80 /* REVISION */
81 
82 #define SDL_EDC_CTL_REVISION_SCHEME_MASK (0xC0000000U)
83 #define SDL_EDC_CTL_REVISION_SCHEME_SHIFT (0x0000001EU)
84 #define SDL_EDC_CTL_REVISION_SCHEME_RESETVAL (0x00000001U)
85 #define SDL_EDC_CTL_REVISION_SCHEME_MAX (0x00000003U)
86 
87 #define SDL_EDC_CTL_REVISION_FUNC_MASK (0x0FFF0000U)
88 #define SDL_EDC_CTL_REVISION_FUNC_SHIFT (0x00000010U)
89 #define SDL_EDC_CTL_REVISION_FUNC_RESETVAL (0x00000F40U)
90 #define SDL_EDC_CTL_REVISION_FUNC_MAX (0x00000FFFU)
91 
92 #define SDL_EDC_CTL_REVISION_RTL_MASK (0x0000F800U)
93 #define SDL_EDC_CTL_REVISION_RTL_SHIFT (0x0000000BU)
94 #define SDL_EDC_CTL_REVISION_RTL_RESETVAL (0x00000000U)
95 #define SDL_EDC_CTL_REVISION_RTL_MAX (0x0000001FU)
96 
97 #define SDL_EDC_CTL_REVISION_MAJOR_MASK (0x00000700U)
98 #define SDL_EDC_CTL_REVISION_MAJOR_SHIFT (0x00000008U)
99 #define SDL_EDC_CTL_REVISION_MAJOR_RESETVAL (0x00000001U)
100 #define SDL_EDC_CTL_REVISION_MAJOR_MAX (0x00000007U)
101 
102 #define SDL_EDC_CTL_REVISION_CUSTOM_MASK (0x000000C0U)
103 #define SDL_EDC_CTL_REVISION_CUSTOM_SHIFT (0x00000006U)
104 #define SDL_EDC_CTL_REVISION_CUSTOM_RESETVAL (0x00000001U)
105 #define SDL_EDC_CTL_REVISION_CUSTOM_MAX (0x00000003U)
106 
107 #define SDL_EDC_CTL_REVISION_MINOR_MASK (0x0000003FU)
108 #define SDL_EDC_CTL_REVISION_MINOR_SHIFT (0x00000000U)
109 #define SDL_EDC_CTL_REVISION_MINOR_RESETVAL (0x00000000U)
110 #define SDL_EDC_CTL_REVISION_MINOR_MAX (0x0000003FU)
111 
112 #define SDL_EDC_CTL_REVISION_RESETVAL (0x4F400140U)
113 
114 /* CONTROL */
115 
116 #define SDL_EDC_CTL_CONTROL_ECC_PATTERN_MASK (0x00000F00U)
117 #define SDL_EDC_CTL_CONTROL_ECC_PATTERN_SHIFT (0x00000008U)
118 #define SDL_EDC_CTL_CONTROL_ECC_PATTERN_RESETVAL (0x00000000U)
119 #define SDL_EDC_CTL_CONTROL_ECC_PATTERN_MAX (0x0000000FU)
120 
121 #define SDL_EDC_CTL_CONTROL_ECC_PATTERN_VAL_ZEROS (0x0U)
122 #define SDL_EDC_CTL_CONTROL_ECC_PATTERN_VAL_F (0x1U)
123 #define SDL_EDC_CTL_CONTROL_ECC_PATTERN_VAL_A (0x2U)
124 #define SDL_EDC_CTL_CONTROL_ECC_PATTERN_VAL_FIVE (0x3U)
125 
126 #define SDL_EDC_CTL_CONTROL_FORCE_N_BIT_MASK (0x00000020U)
127 #define SDL_EDC_CTL_CONTROL_FORCE_N_BIT_SHIFT (0x00000005U)
128 #define SDL_EDC_CTL_CONTROL_FORCE_N_BIT_RESETVAL (0x00000000U)
129 #define SDL_EDC_CTL_CONTROL_FORCE_N_BIT_MAX (0x00000001U)
130 
131 #define SDL_EDC_CTL_CONTROL_FORCE_N_BIT_VAL_KEEP_CURR_SETTINGS (0x0U)
132 #define SDL_EDC_CTL_CONTROL_FORCE_N_BIT_VAL_INC_TO_NEXT (0x1U)
133 
134 #define SDL_EDC_CTL_CONTROL_FORCE_DE_MASK (0x00000010U)
135 #define SDL_EDC_CTL_CONTROL_FORCE_DE_SHIFT (0x00000004U)
136 #define SDL_EDC_CTL_CONTROL_FORCE_DE_RESETVAL (0x00000000U)
137 #define SDL_EDC_CTL_CONTROL_FORCE_DE_MAX (0x00000001U)
138 
139 #define SDL_EDC_CTL_CONTROL_FORCE_SE_MASK (0x00000008U)
140 #define SDL_EDC_CTL_CONTROL_FORCE_SE_SHIFT (0x00000003U)
141 #define SDL_EDC_CTL_CONTROL_FORCE_SE_RESETVAL (0x00000000U)
142 #define SDL_EDC_CTL_CONTROL_FORCE_SE_MAX (0x00000001U)
143 
144 #define SDL_EDC_CTL_CONTROL_ECC_CHECK_MASK (0x00000002U)
145 #define SDL_EDC_CTL_CONTROL_ECC_CHECK_SHIFT (0x00000001U)
146 #define SDL_EDC_CTL_CONTROL_ECC_CHECK_RESETVAL (0x00000001U)
147 #define SDL_EDC_CTL_CONTROL_ECC_CHECK_MAX (0x00000001U)
148 
149 #define SDL_EDC_CTL_CONTROL_ECC_CHECK_VAL_DISABLE (0x0U)
150 #define SDL_EDC_CTL_CONTROL_ECC_CHECK_VAL_ENABLE (0x1U)
151 
152 #define SDL_EDC_CTL_CONTROL_RESETVAL (0x00000002U)
153 
154 /* ERR_INJECT1 */
155 
156 #define SDL_EDC_CTL_ERR_INJECT1_ECC_BIT1_MASK (0x01FF0000U)
157 #define SDL_EDC_CTL_ERR_INJECT1_ECC_BIT1_SHIFT (0x00000010U)
158 #define SDL_EDC_CTL_ERR_INJECT1_ECC_BIT1_RESETVAL (0x00000000U)
159 #define SDL_EDC_CTL_ERR_INJECT1_ECC_BIT1_MAX (0x000001FFU)
160 
161 #define SDL_EDC_CTL_ERR_INJECT1_ECC_GRP_MASK (0x0000FFFFU)
162 #define SDL_EDC_CTL_ERR_INJECT1_ECC_GRP_SHIFT (0x00000000U)
163 #define SDL_EDC_CTL_ERR_INJECT1_ECC_GRP_RESETVAL (0x00000000U)
164 #define SDL_EDC_CTL_ERR_INJECT1_ECC_GRP_MAX (0x0000FFFFU)
165 
166 #define SDL_EDC_CTL_ERR_INJECT1_RESETVAL (0x00000000U)
167 
168 /* ERR_INJECT2 */
169 
170 #define SDL_EDC_CTL_ERR_INJECT2_ECC_BIT2_MASK (0x000001FFU)
171 #define SDL_EDC_CTL_ERR_INJECT2_ECC_BIT2_SHIFT (0x00000000U)
172 #define SDL_EDC_CTL_ERR_INJECT2_ECC_BIT2_RESETVAL (0x00000000U)
173 #define SDL_EDC_CTL_ERR_INJECT2_ECC_BIT2_MAX (0x000001FFU)
174 
175 #define SDL_EDC_CTL_ERR_INJECT2_RESETVAL (0x00000000U)
176 
177 /* ERR_STATUS1 */
178 
179 #define SDL_EDC_CTL_ERR_STATUS1_ERR_GRP_MASK (0xFFFF0000U)
180 #define SDL_EDC_CTL_ERR_STATUS1_ERR_GRP_SHIFT (0x00000010U)
181 #define SDL_EDC_CTL_ERR_STATUS1_ERR_GRP_RESETVAL (0x00000000U)
182 #define SDL_EDC_CTL_ERR_STATUS1_ERR_GRP_MAX (0x0000FFFFU)
183 
184 #define SDL_EDC_CTL_ERR_STATUS1_INJ_UNC_PEND_CLR_MASK (0x0000C000U)
185 #define SDL_EDC_CTL_ERR_STATUS1_INJ_UNC_PEND_CLR_SHIFT (0x0000000EU)
186 #define SDL_EDC_CTL_ERR_STATUS1_INJ_UNC_PEND_CLR_RESETVAL (0x00000000U)
187 #define SDL_EDC_CTL_ERR_STATUS1_INJ_UNC_PEND_CLR_MAX (0x00000003U)
188 
189 #define SDL_EDC_CTL_ERR_STATUS1_INJ_COR_PEND_CLR_MASK (0x00003000U)
190 #define SDL_EDC_CTL_ERR_STATUS1_INJ_COR_PEND_CLR_SHIFT (0x0000000CU)
191 #define SDL_EDC_CTL_ERR_STATUS1_INJ_COR_PEND_CLR_RESETVAL (0x00000000U)
192 #define SDL_EDC_CTL_ERR_STATUS1_INJ_COR_PEND_CLR_MAX (0x00000003U)
193 
194 #define SDL_EDC_CTL_ERR_STATUS1_UNC_PEND_CLR_MASK (0x00000C00U)
195 #define SDL_EDC_CTL_ERR_STATUS1_UNC_PEND_CLR_SHIFT (0x0000000AU)
196 #define SDL_EDC_CTL_ERR_STATUS1_UNC_PEND_CLR_RESETVAL (0x00000000U)
197 #define SDL_EDC_CTL_ERR_STATUS1_UNC_PEND_CLR_MAX (0x00000003U)
198 
199 #define SDL_EDC_CTL_ERR_STATUS1_COR_PEND_CLR_MASK (0x00000300U)
200 #define SDL_EDC_CTL_ERR_STATUS1_COR_PEND_CLR_SHIFT (0x00000008U)
201 #define SDL_EDC_CTL_ERR_STATUS1_COR_PEND_CLR_RESETVAL (0x00000000U)
202 #define SDL_EDC_CTL_ERR_STATUS1_COR_PEND_CLR_MAX (0x00000003U)
203 
204 #define SDL_EDC_CTL_ERR_STATUS1_INJ_UNC_PEND_MASK (0x000000C0U)
205 #define SDL_EDC_CTL_ERR_STATUS1_INJ_UNC_PEND_SHIFT (0x00000006U)
206 #define SDL_EDC_CTL_ERR_STATUS1_INJ_UNC_PEND_RESETVAL (0x00000000U)
207 #define SDL_EDC_CTL_ERR_STATUS1_INJ_UNC_PEND_MAX (0x00000003U)
208 
209 #define SDL_EDC_CTL_ERR_STATUS1_INJ_COR_PEND_MASK (0x00000030U)
210 #define SDL_EDC_CTL_ERR_STATUS1_INJ_COR_PEND_SHIFT (0x00000004U)
211 #define SDL_EDC_CTL_ERR_STATUS1_INJ_COR_PEND_RESETVAL (0x00000000U)
212 #define SDL_EDC_CTL_ERR_STATUS1_INJ_COR_PEND_MAX (0x00000003U)
213 
214 #define SDL_EDC_CTL_ERR_STATUS1_UNC_PEND_MASK (0x0000000CU)
215 #define SDL_EDC_CTL_ERR_STATUS1_UNC_PEND_SHIFT (0x00000002U)
216 #define SDL_EDC_CTL_ERR_STATUS1_UNC_PEND_RESETVAL (0x00000000U)
217 #define SDL_EDC_CTL_ERR_STATUS1_UNC_PEND_MAX (0x00000003U)
218 
219 #define SDL_EDC_CTL_ERR_STATUS1_COR_PEND_MASK (0x00000003U)
220 #define SDL_EDC_CTL_ERR_STATUS1_COR_PEND_SHIFT (0x00000000U)
221 #define SDL_EDC_CTL_ERR_STATUS1_COR_PEND_RESETVAL (0x00000000U)
222 #define SDL_EDC_CTL_ERR_STATUS1_COR_PEND_MAX (0x00000003U)
223 
224 #define SDL_EDC_CTL_ERR_STATUS1_RESETVAL (0x00000000U)
225 
226 /* ERR_STATUS2 */
227 
228 #define SDL_EDC_CTL_ERR_STATUS2_ERR_TYPE_MASK (0xFFFF0000U)
229 #define SDL_EDC_CTL_ERR_STATUS2_ERR_TYPE_SHIFT (0x00000010U)
230 #define SDL_EDC_CTL_ERR_STATUS2_ERR_TYPE_RESETVAL (0x00000000U)
231 #define SDL_EDC_CTL_ERR_STATUS2_ERR_TYPE_MAX (0x0000FFFFU)
232 
233 #define SDL_EDC_CTL_ERR_STATUS2_ERR_BIT_MASK (0x0000FFFFU)
234 #define SDL_EDC_CTL_ERR_STATUS2_ERR_BIT_SHIFT (0x00000000U)
235 #define SDL_EDC_CTL_ERR_STATUS2_ERR_BIT_RESETVAL (0x00000000U)
236 #define SDL_EDC_CTL_ERR_STATUS2_ERR_BIT_MAX (0x0000FFFFU)
237 
238 #define SDL_EDC_CTL_ERR_STATUS2_RESETVAL (0x00000000U)
239 
240 #ifdef __cplusplus
241 }
242 #endif
243 #endif
SDL_edc_ctlRegs::CONTROL
volatile uint32_t CONTROL
Definition: sdlr_edc_ctl.h:56
SDL_edc_ctlRegs::ERR_STATUS2
volatile uint32_t ERR_STATUS2
Definition: sdlr_edc_ctl.h:60
SDL_edc_ctlRegs::REVISION
volatile uint32_t REVISION
Definition: sdlr_edc_ctl.h:55
SDL_edc_ctlRegs::ERR_INJECT1
volatile uint32_t ERR_INJECT1
Definition: sdlr_edc_ctl.h:57
SDL_edc_ctlRegs
Definition: sdlr_edc_ctl.h:53
SDL_edc_ctlRegs::ERR_INJECT2
volatile uint32_t ERR_INJECT2
Definition: sdlr_edc_ctl.h:58
SDL_edc_ctlRegs::ERR_STATUS1
volatile uint32_t ERR_STATUS1
Definition: sdlr_edc_ctl.h:59