sdl_ecc_soc.h File Reference

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Macros
#define	SDL_ECC_WIDTH_UNDEFINED   0x1
#define	SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES   (3U)
#define	SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES   (3U)
#define	SDL_MCU_ADC0_0_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_MCU_ADC1_0_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_MCU_I3C1_0_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_MCU_I3C1_1_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_COMPUTE_CLUSTER0_0_RAM_IDS_TOTAL_ENTRIES   (24U)
#define	SDL_COMPUTE_CLUSTER0_1_RAM_IDS_TOTAL_ENTRIES   (24U)
#define	SDL_COMPUTE_CLUSTER0_2_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_COMPUTE_CLUSTER0_3_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_COMPUTE_CLUSTER0_4_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_COMPUTE_CLUSTER0_5_RAM_IDS_TOTAL_ENTRIES   (32U)
#define	SDL_COMPUTE_CLUSTER0_6_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_VC_MAIN_HC_ECC_AGGR5_0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MSRAM_512K0_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PDMA9_0_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_USB0_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_IDOM0_ECC_AGGR16_0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_WKUP_VTM0_0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCU_MSRAM_1MB0_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PCIE1_0_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_PCIE1_1_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_PSRAM2KECC0_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCAN14_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD1_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD1_1_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PDMA10_0_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_MCAN10_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PSRAMECC0_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_MCAN0_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_SA2_UL0_0_RAM_IDS_TOTAL_ENTRIES   (12U)
#define	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES   (26U)
#define	SDL_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES   (64U)
#define	SDL_NAVSS0_2_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_NAVSS0_3_RAM_IDS_TOTAL_ENTRIES   (6U)
#define	SDL_MCU_MCAN1_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_VC_MCU_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES   (10U)
#define	SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES   (15U)
#define	SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_I3C0_0_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_MCU_I3C0_1_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES   (33U)
#define	SDL_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES   (33U)
#define	SDL_IDOM1_ECC_AGGR17_0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_DDR0_0_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_DDR0_1_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_DDR0_2_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCAN8_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN1_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN0_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN3_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN2_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN4_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN7_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN6_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES   (33U)
#define	SDL_MCU_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES   (33U)
#define	SDL_MCU_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES   (14U)
#define	SDL_MCU_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES   (59U)
#define	SDL_MMCSD0_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD0_1_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PDMA5_0_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_MCAN11_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN13_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN12_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN15_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN17_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN16_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_I3C0_0_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_I3C0_1_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCAN9_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_VC_MAIN_RC_ECC_AGGR4_0_RAM_IDS_TOTAL_ENTRIES   (6U)
#define	SDL_MCAN5_0_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION   (2U)
#define	SDL_ECC_AGGREGATOR_MAX_ENTRIES

Variables
static const SDL_MemConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_MemEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SCR_J7VC_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SCR_J7VC_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SCR_J7VC_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SCR_J7VC_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SCR_J7VC_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SCR_J7VC_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_EDC_CTRL_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_M2P_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_M2P_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_groupEntries [SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_CPSW0_0_MemEntries [SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_ADC0_0_MemEntries [SDL_MCU_ADC0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_ADC1_0_MemEntries [SDL_MCU_ADC1_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_I3C1_0_MemEntries [SDL_MCU_I3C1_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_I3C1_I3C_EDC_CTRL_0_groupEntries [SDL_MCU_I3C1_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_0_MemEntries [SDL_COMPUTE_CLUSTER0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_1_MemEntries [SDL_COMPUTE_CLUSTER0_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_2_MemEntries [SDL_COMPUTE_CLUSTER0_2_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_DDRSS0_M2M_SRC_VBUSS_groupEntries [SDL_COMPUTE_CLUSTER0_DDRSS0_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_MMR_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_POSTARB_PIPE_CFG_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_POSTARB_PIPE_CFG_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EMIF0_SLV_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_EMIF0_SLV_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_CPU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_CPU8_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_CPU9_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_DATA_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_DATA_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_0_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW0_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_RMW0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_RMW0_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_0_groupEntries [SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_1_groupEntries [SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_2_groupEntries [SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_RMW0_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_RMW0_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_SRAM0_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_SRAM0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_DATARAM_BANK0_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_DATARAM_BANK0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW1_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_RMW1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_RMW1_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_0_groupEntries [SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_1_groupEntries [SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_2_groupEntries [SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_RMW1_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_RMW1_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_SRAM1_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_SRAM1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_DATARAM_BANK1_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_DATARAM_BANK1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EMIF_0_VSAFE_SI_groupEntries [SDL_COMPUTE_CLUSTER0_EMIF_0_VSAFE_SI_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_MMR_FW_EDC_CTL_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_MMR_FW_EDC_CTL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_DATA_BUF_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_DATA_BUF_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_RESP_BUF_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_RESP_BUF_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WRITE_RESP_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WRITE_RESP_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_1_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_groupEntries [SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_groupEntries [SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_5_MemEntries [SDL_COMPUTE_CLUSTER0_5_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_SCR1_SCR_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_SCR1_SCR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_groupEntries [SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_groupEntries [SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries [SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries [SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_6_MemEntries [SDL_COMPUTE_CLUSTER0_6_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_groupEntries [SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_HC2_SCR_J7VC_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_HC2_SCR_J7VC_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SCR_J7VC_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SCR_J7VC_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_IJ7VC_MAIN_HC2_FW_CBASS_0_J7VC_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_IJ7VC_MAIN_HC2_FW_CBASS_0_J7VC_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_RD_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_RD_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_WR_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_WR_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTR0_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTR0_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTW0_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTW0_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries [SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MSRAM_512K0_0_MemEntries [SDL_MSRAM_512K0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries [SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PDMA9_0_MemEntries [SDL_PDMA9_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_USB0_0_MemEntries [SDL_USB0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VC_MVO_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VC_MVO_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SCR_J7VC_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SCR_J7VC_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_MSRAM_1MB0_0_MemEntries [SDL_MCU_MSRAM_1MB0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries [SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PCIE1_0_MemEntries [SDL_PCIE1_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries [SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PCIE1_1_MemEntries [SDL_PCIE1_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PSRAM2KECC0_0_MemEntries [SDL_PSRAM2KECC0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries [SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries [SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN14_0_MemEntries [SDL_MCAN14_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN14_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN14_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MMCSD1_0_MemEntries [SDL_MMCSD1_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MMCSD1_1_MemEntries [SDL_MMCSD1_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PDMA10_0_MemEntries [SDL_PDMA10_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN10_0_MemEntries [SDL_MCAN10_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN10_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN10_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PSRAMECC0_0_MemEntries [SDL_PSRAMECC0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries [SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_groupEntries [SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_MCAN0_0_MemEntries [SDL_MCU_MCAN0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_MCAN0_CTRL_EDC_VBUSS_groupEntries [SDL_MCU_MCAN0_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_SA2_UL0_0_MemEntries [SDL_MCU_SA2_UL0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_MemEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_BR_FROM_PULSAR0_M2P_BRIDGE_BR_FROM_PULSAR0_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_BR_FROM_PULSAR0_M2P_BRIDGE_BR_FROM_PULSAR0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_EDC_CTRL_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_M2P_BUSECC_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_M2P_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_groupEntries [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_NAVSS0_0_MemEntries [SDL_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_NAVSS0_1_MemEntries [SDL_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_E_GCLK_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_E_GCLK_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_SCR_E_GCLK_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_SCR_E_GCLK_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_DEBUG_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_DEBUG_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MCASP_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MCASP_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MISC_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MISC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_USART_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_USART_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CPSW9_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CPSW9_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_NAVSS_MCU_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_NAVSS_MCU_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_DEBUG_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_DEBUG_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MCASP_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MCASP_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MISC_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MISC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_USART_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_USART_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_CPSW9_PSIL_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_CPSW9_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_NAVSS0_3_MemEntries [SDL_NAVSS0_3_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_DST_TOG_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_DST_TOG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries [SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_MCAN1_0_MemEntries [SDL_MCU_MCAN1_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_MCAN1_CTRL_EDC_VBUSS_groupEntries [SDL_MCU_MCAN1_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_0_MemEntries [SDL_MCU_VC_MCU_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SCR_J7VC_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SCR_J7VC_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SCR_J7VC_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SCR_J7VC_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CTRL_MMR_MCU_0_J7VC_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CTRL_MMR_MCU_0_J7VC_MCU_CTRL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_FSS0_0_MemEntries [SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_FSS0_1_MemEntries [SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_FSS0_2_MemEntries [SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_CPSW0_0_MemEntries [SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_I3C0_0_MemEntries [SDL_MCU_I3C0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_I3C0_I3C_EDC_CTRL_0_groupEntries [SDL_MCU_I3C0_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_R5FSS0_0_MemEntries [SDL_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries [SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_R5FSS0_1_MemEntries [SDL_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries [SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_groupEntries [SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_groupEntries [SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_groupEntries [SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_groupEntries [SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries [SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0_groupEntries [SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN8_0_MemEntries [SDL_MCAN8_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN8_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN8_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN1_0_MemEntries [SDL_MCAN1_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN1_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN1_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN0_0_MemEntries [SDL_MCAN0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN0_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN0_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN3_0_MemEntries [SDL_MCAN3_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN3_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN3_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN2_0_MemEntries [SDL_MCAN2_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN2_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN2_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN4_0_MemEntries [SDL_MCAN4_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN4_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN4_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN7_0_MemEntries [SDL_MCAN7_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN7_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN7_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN6_0_MemEntries [SDL_MCAN6_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN6_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN6_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_R5FSS0_0_MemEntries [SDL_MCU_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries [SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_R5FSS0_1_MemEntries [SDL_MCU_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries [SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_NAVSS0_0_MemEntries [SDL_MCU_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCU_NAVSS0_1_MemEntries [SDL_MCU_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_2_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MMCSD0_0_MemEntries [SDL_MMCSD0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MMCSD0_1_MemEntries [SDL_MMCSD0_1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PDMA5_0_MemEntries [SDL_PDMA5_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN11_0_MemEntries [SDL_MCAN11_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN11_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN11_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN13_0_MemEntries [SDL_MCAN13_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN13_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN13_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN12_0_MemEntries [SDL_MCAN12_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN12_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN12_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN15_0_MemEntries [SDL_MCAN15_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN15_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN15_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN17_0_MemEntries [SDL_MCAN17_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN17_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN17_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN16_0_MemEntries [SDL_MCAN16_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN16_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN16_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_I3C0_0_MemEntries [SDL_I3C0_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_I3C0_I3C_EDC_CTRL_0_groupEntries [SDL_I3C0_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN9_0_MemEntries [SDL_MCAN9_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN9_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN9_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_0_MemEntries [SDL_VC_MAIN_RC_ECC_AGGR4_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SCR_J7VC_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SCR_J7VC_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_32P_SCR_J7VC_RC_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_32P_SCR_J7VC_RC_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_J7VC_RC_TO_RC_CFG_M2P_BRIDGE_J7VC_RC_TO_RC_CFG_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_J7VC_RC_TO_RC_CFG_M2P_BRIDGE_J7VC_RC_TO_RC_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_0_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries [SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN5_0_MemEntries [SDL_MCAN5_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN5_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN5_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_RAMIdEntry_t	SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_RamIdTable [SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CPSW0_0_RamIdTable [SDL_CPSW0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_ADC0_0_RamIdTable [SDL_MCU_ADC0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_ADC1_0_RamIdTable [SDL_MCU_ADC1_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_I3C1_0_RamIdTable [SDL_MCU_I3C1_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_I3C1_1_RamIdTable [SDL_MCU_I3C1_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_0_RamIdTable [SDL_COMPUTE_CLUSTER0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_1_RamIdTable [SDL_COMPUTE_CLUSTER0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_2_RamIdTable [SDL_COMPUTE_CLUSTER0_2_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_3_RamIdTable [SDL_COMPUTE_CLUSTER0_3_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_4_RamIdTable [SDL_COMPUTE_CLUSTER0_4_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_5_RamIdTable [SDL_COMPUTE_CLUSTER0_5_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_6_RamIdTable [SDL_COMPUTE_CLUSTER0_6_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VC_MAIN_HC_ECC_AGGR5_0_RamIdTable [SDL_VC_MAIN_HC_ECC_AGGR5_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_512K0_0_RamIdTable [SDL_MSRAM_512K0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA9_0_RamIdTable [SDL_PDMA9_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_USB0_0_RamIdTable [SDL_USB0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0_RamIdTable [SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM0_ECC_AGGR16_0_RamIdTable [SDL_IDOM0_ECC_AGGR16_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_VTM0_0_RamIdTable [SDL_WKUP_VTM0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_MSRAM_1MB0_0_RamIdTable [SDL_MCU_MSRAM_1MB0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE1_0_RamIdTable [SDL_PCIE1_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE1_1_RamIdTable [SDL_PCIE1_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PSRAM2KECC0_0_RamIdTable [SDL_PSRAM2KECC0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0_RamIdTable [SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN14_0_RamIdTable [SDL_MCAN14_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD1_0_RamIdTable [SDL_MMCSD1_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD1_1_RamIdTable [SDL_MMCSD1_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA10_0_RamIdTable [SDL_PDMA10_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN10_0_RamIdTable [SDL_MCAN10_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PSRAMECC0_0_RamIdTable [SDL_PSRAMECC0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_MCAN0_0_RamIdTable [SDL_MCU_MCAN0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_SA2_UL0_0_RamIdTable [SDL_MCU_SA2_UL0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_RamIdTable [SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS0_0_RamIdTable [SDL_NAVSS0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS0_1_RamIdTable [SDL_NAVSS0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS0_2_RamIdTable [SDL_NAVSS0_2_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_NAVSS0_3_RamIdTable [SDL_NAVSS0_3_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_MCAN1_0_RamIdTable [SDL_MCU_MCAN1_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_VC_MCU_ECC_AGGR0_0_RamIdTable [SDL_MCU_VC_MCU_ECC_AGGR0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_FSS0_0_RamIdTable [SDL_MCU_FSS0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_FSS0_1_RamIdTable [SDL_MCU_FSS0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_FSS0_2_RamIdTable [SDL_MCU_FSS0_2_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_CPSW0_0_RamIdTable [SDL_MCU_CPSW0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_I3C0_0_RamIdTable [SDL_MCU_I3C0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_I3C0_1_RamIdTable [SDL_MCU_I3C0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_0_RamIdTable [SDL_R5FSS0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_1_RamIdTable [SDL_R5FSS0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM1_ECC_AGGR17_0_RamIdTable [SDL_IDOM1_ECC_AGGR17_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DDR0_0_RamIdTable [SDL_DDR0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DDR0_1_RamIdTable [SDL_DDR0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DDR0_2_RamIdTable [SDL_DDR0_2_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN8_0_RamIdTable [SDL_MCAN8_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN1_0_RamIdTable [SDL_MCAN1_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN0_0_RamIdTable [SDL_MCAN0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN3_0_RamIdTable [SDL_MCAN3_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN2_0_RamIdTable [SDL_MCAN2_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN4_0_RamIdTable [SDL_MCAN4_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN7_0_RamIdTable [SDL_MCAN7_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN6_0_RamIdTable [SDL_MCAN6_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_R5FSS0_0_RamIdTable [SDL_MCU_R5FSS0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_R5FSS0_1_RamIdTable [SDL_MCU_R5FSS0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_NAVSS0_0_RamIdTable [SDL_MCU_NAVSS0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_NAVSS0_1_RamIdTable [SDL_MCU_NAVSS0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD0_0_RamIdTable [SDL_MMCSD0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD0_1_RamIdTable [SDL_MMCSD0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA5_0_RamIdTable [SDL_PDMA5_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN11_0_RamIdTable [SDL_MCAN11_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN13_0_RamIdTable [SDL_MCAN13_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN12_0_RamIdTable [SDL_MCAN12_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN15_0_RamIdTable [SDL_MCAN15_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN17_0_RamIdTable [SDL_MCAN17_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN16_0_RamIdTable [SDL_MCAN16_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_I3C0_0_RamIdTable [SDL_I3C0_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_I3C0_1_RamIdTable [SDL_I3C0_1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN9_0_RamIdTable [SDL_MCAN9_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VC_MAIN_RC_ECC_AGGR4_0_RamIdTable [SDL_VC_MAIN_RC_ECC_AGGR4_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN5_0_RamIdTable [SDL_MCAN5_0_NUM_RAMS]
static SDL_ecc_aggrRegs *const	SDL_ECC_aggrBaseAddressTable [SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES]
	This structure holds the base addresses for each memory subtype in MCU domain More...
static uint64_t const	SDL_ECC_aggrHighBaseAddressTable [SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
SDL_ecc_aggrRegs *	SDL_ECC_aggrHighBaseAddressTableTrans [SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
static const SDL_EccAggrEntry_t	SDL_ECC_aggrTable [SDL_ECC_MEMTYPE_MAX]

Macro Definition Documentation

SDL_ECC_WIDTH_UNDEFINED

#define SDL_ECC_WIDTH_UNDEFINED   0x1

SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES   (3U)

SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES   (3U)

SDL_MCU_ADC0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_ADC0_0_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_MCU_ADC1_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_ADC1_0_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_MCU_I3C1_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_I3C1_0_RAM_IDS_TOTAL_ENTRIES   (9U)

SDL_MCU_I3C1_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_I3C1_1_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_COMPUTE_CLUSTER0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_0_RAM_IDS_TOTAL_ENTRIES   (24U)

SDL_COMPUTE_CLUSTER0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_1_RAM_IDS_TOTAL_ENTRIES   (24U)

SDL_COMPUTE_CLUSTER0_2_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_2_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_COMPUTE_CLUSTER0_3_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_3_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_COMPUTE_CLUSTER0_4_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_4_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_COMPUTE_CLUSTER0_5_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_5_RAM_IDS_TOTAL_ENTRIES   (32U)

SDL_COMPUTE_CLUSTER0_6_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_6_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_VC_MAIN_HC_ECC_AGGR5_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_VC_MAIN_HC_ECC_AGGR5_0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MSRAM_512K0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_512K0_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PDMA9_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA9_0_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_USB0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_USB0_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_IDOM0_ECC_AGGR16_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM0_ECC_AGGR16_0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_WKUP_VTM0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_VTM0_0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCU_MSRAM_1MB0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_MSRAM_1MB0_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PCIE1_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE1_0_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_PCIE1_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE1_1_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_PSRAM2KECC0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PSRAM2KECC0_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCAN14_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN14_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD1_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD1_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD1_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD1_1_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PDMA10_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA10_0_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_MCAN10_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN10_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PSRAMECC0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PSRAMECC0_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_MCAN0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_MCAN0_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_SA2_UL0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_SA2_UL0_0_RAM_IDS_TOTAL_ENTRIES   (12U)

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES   (26U)

SDL_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES   (64U)

SDL_NAVSS0_2_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS0_2_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_NAVSS0_3_RAM_IDS_TOTAL_ENTRIES

#define SDL_NAVSS0_3_RAM_IDS_TOTAL_ENTRIES   (6U)

SDL_MCU_MCAN1_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_MCAN1_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_VC_MCU_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_VC_MCU_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES   (10U)

SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES   (15U)

SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_I3C0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_I3C0_0_RAM_IDS_TOTAL_ENTRIES   (9U)

SDL_MCU_I3C0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_I3C0_1_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES   (33U)

SDL_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES   (33U)

SDL_IDOM1_ECC_AGGR17_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM1_ECC_AGGR17_0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_DDR0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_DDR0_0_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_DDR0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_DDR0_1_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_DDR0_2_RAM_IDS_TOTAL_ENTRIES

#define SDL_DDR0_2_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCAN8_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN8_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN1_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN1_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN0_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN3_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN3_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN2_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN2_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN4_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN4_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN7_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN7_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN6_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN6_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES   (33U)

SDL_MCU_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES   (33U)

SDL_MCU_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES   (14U)

SDL_MCU_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES   (59U)

SDL_MMCSD0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_1_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PDMA5_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA5_0_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_MCAN11_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN11_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN13_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN13_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN12_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN12_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN15_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN15_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN17_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN17_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN16_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN16_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_I3C0_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_I3C0_0_RAM_IDS_TOTAL_ENTRIES   (9U)

SDL_I3C0_1_RAM_IDS_TOTAL_ENTRIES

#define SDL_I3C0_1_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCAN9_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN9_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_VC_MAIN_RC_ECC_AGGR4_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_VC_MAIN_RC_ECC_AGGR4_0_RAM_IDS_TOTAL_ENTRIES   (6U)

SDL_MCAN5_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN5_0_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION

#define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION   (2U)

---

This structure holds the memory config for each memory subtype SDL_MCU_R5FSS0_0

SDL_ECC_AGGREGATOR_MAX_ENTRIES

#define SDL_ECC_AGGREGATOR_MAX_ENTRIES

Value:

(SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES + \
                                        SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES)

Variable Documentation

SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_MemEntries

const SDL_MemConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_MemEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_RD_RAMECC_RAM_ID, 0u,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_RD_RAMECC_RAM_SIZE, 4u,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_WR_RAMECC_RAM_ID, 0u,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_WR_RAMECC_RAM_SIZE, 4u,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_VCL_MAIN_INFRA_ECC_AGGR0_0

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SCR_J7VC_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SCR_J7VC_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SCR_J7VC_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SCR_J7VC_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_INAVSS256VCL_MAIN_0_OC_MSRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SCR_J7VC_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SCR_J7VC_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SCR_J7VC_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SCR_J7VC_PULSAR0_SLV_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_MEM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_MEM_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_J7VC_PULSAR0_SLV_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_MEM_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_INFRA_0_CFG_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IMSRAM16KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR_P_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_PULSAR0_SLV_CBASS_DMSC_SLV_P2P_BRIDGE_PULSAR0_SLV_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7VC_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SCR_J7VC_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SCR_J7VC_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SCR_J7VC_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SCR_J7VC_PULSAR0_MEM_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7VC_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7VC_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7VC_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_REASSEMBLY_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_J7VC_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SAFE_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_J7VC_PULSAR0_SLV_CBASS_PULSAR64_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_SLV_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_J7VC_PULSAR0_MEM_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_PULSAR0_SLV_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_J7VC_PULSAR0_MEM_CBASS_PULSAR128_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IMSRAM16KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM16KX256E_MAIN_0_CFG_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VC_PULSAR0_SLV_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_SLV_CBASS__J7VC_PULSAR0_SLV_CBASS_BR_FROM_64M_PULSAR_M2P_BRIDGE_BR_FROM_64M_PULSAR_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_EDC_CTRL_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_EDC_CTRL RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU0_WMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_J7VC_PULSAR0_MEM_CBASS_IPULSAR_SL_MAIN_0_CPU1_RMST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IJ7VC_PULSAR0_MEM_CBASS__J7VC_PULSAR0_MEM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_M2P_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_M2P_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_M2P_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_M2P_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_IEXPORT_VBUSP_32B_MST_MAIN_INFRA_0_MST_STOG_P2M_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6 RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFR_NON_SAFE_A_CBASS_MAIN_0_J7VC_MAIN_INFRA_NON_SAFE_CBASS_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7VC_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_4_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_5_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_6_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_EFUSE_PARITY_CHAIN1_BUSECC RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_groupEntries[SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_MAIN_INFRA_ECC_AGGR0_J7VCL_MAIN_INFRA_ECC_AGGR_EDC_CTRL RAM ID

SDL_CPSW0_0_MemEntries

const SDL_MemConfig_t SDL_CPSW0_0_MemEntries[SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CPSW0_CPSW_5XU_J7AMP_CORE_ECC_ECC_CTRL3_RAM_ID, 0u,
      SDL_CPSW0_CPSW_5XU_J7AMP_CORE_ECC_ECC_CTRL3_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_5XU_J7AMP_CORE_ECC_ECC_CTRL3_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_5XU_J7AMP_CORE_ECC_ECC_CTRL4_RAM_ID, 0u,
      SDL_CPSW0_CPSW_5XU_J7AMP_CORE_ECC_ECC_CTRL4_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_5XU_J7AMP_CORE_ECC_ECC_CTRL4_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_EST_RAM_RAM_ID, 0u,
      SDL_CPSW0_EST_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_EST_RAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CPSW0_0

SDL_MCU_ADC0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_ADC0_0_MemEntries[SDL_MCU_ADC0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
      SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
      SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_ADC0_0

SDL_MCU_ADC1_0_MemEntries

const SDL_MemConfig_t SDL_MCU_ADC1_0_MemEntries[SDL_MCU_ADC1_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
      SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
      SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_ADC1_0

SDL_MCU_I3C1_0_MemEntries

const SDL_MemConfig_t SDL_MCU_I3C1_0_MemEntries[SDL_MCU_I3C1_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_I3C1_I3C_IBIR_QUEUE_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_SLV_DDR_RX_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_CMDR_QUEUE_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_SLV_DDR_TX_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_IBI_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_IBI_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_IBI_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_CMD_WRD1_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_CMD_WRD1_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_TX_DATA_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_TX_DATA_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_CMD_WRD0_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_CMD_WRD0_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C1_I3C_RX_DATA_RAM_ID, 0u,
      SDL_MCU_I3C1_I3C_RX_DATA_RAM_SIZE, 4u,
      SDL_MCU_I3C1_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_I3C1_0

SDL_MCU_I3C1_I3C_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_I3C1_I3C_EDC_CTRL_0_groupEntries[SDL_MCU_I3C1_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_I3C1_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_I3C1_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_I3C1_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_I3C1_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_I3C1_I3C_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_0_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_0_MemEntries[SDL_COMPUTE_CLUSTER0_0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_0

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU1_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_1_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_1_MemEntries[SDL_COMPUTE_CLUSTER0_1_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_1

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_CPU0_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_2_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_2_MemEntries[SDL_COMPUTE_CLUSTER0_2_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_WR_RAMECC_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_WR_RAMECC_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_RD_RAMECC_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_RD_RAMECC_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_RD_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_2

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_DDRSS0_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_DDRSS0_M2M_SRC_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_DDRSS0_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_DDRSS0_M2M_SRC_VBUSS RAM ID

SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_GICSS_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_GICSS_VBUSM_GASKET_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_GICSS_VBUSM_GASKET_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR1_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_MMR_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_MMR_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_MMR_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_POSTARB_PIPE_CFG_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_POSTARB_PIPE_CFG_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_POSTARB_PIPE_CFG_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_POSTARB_PIPE_CFG_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_POSTARB_PIPE_CFG_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_POSTARB_PIPE_CFG_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_EMIF0_SLV_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EMIF0_SLV_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_EMIF0_SLV_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EMIF0_SLV_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_8_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_9_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC_GROUP_10_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EMIF0_MST_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_CPU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_CPU0_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_CPU0_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_CPU8_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_CPU8_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_CPU8_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_CPU9_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_CPU9_SLV_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
    { SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_CPU9_MST_LOCAL_ARB_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_DATA_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_DATA_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_DATA_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_DATA_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_DATA_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_DATA RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_0 RAM ID

SDL_COMPUTE_CLUSTER0_RMW0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_RMW0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW0_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_RMW0_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW0_CACHE_TAG_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_0 RAM ID

SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_1 RAM ID

SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_2_groupEntries[SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW0_QUEUE_BUSECC_2 RAM ID

SDL_COMPUTE_CLUSTER0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_RMW0_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW0_RMW_TAG_UPDATE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_RMW0_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW0_SRAM_SF_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_SRAM0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_SRAM0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_SRAM0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_SRAM0_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_DATARAM_BANK0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_DATARAM_BANK0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_DATARAM_BANK0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_DATARAM_BANK0_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_RMW1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_RMW1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW1_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_RMW1_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW1_CACHE_TAG_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_0 RAM ID

SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_1 RAM ID

SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_2_groupEntries[SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW1_QUEUE_BUSECC_2 RAM ID

SDL_COMPUTE_CLUSTER0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_RMW1_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW1_RMW_TAG_UPDATE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_RMW1_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_RMW1_SRAM_SF_PIPE_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_SRAM1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_SRAM1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_SRAM1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_SRAM1_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_DATARAM_BANK1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_DATARAM_BANK1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_DATARAM_BANK1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_DATARAM_BANK1_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_DST_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_EMIF_0_VSAFE_SI_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EMIF_0_VSAFE_SI_groupEntries[SDL_COMPUTE_CLUSTER0_EMIF_0_VSAFE_SI_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EMIF_0_VSAFE_SI RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_MMR_FW_EDC_CTL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_MMR_FW_EDC_CTL_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_MMR_FW_EDC_CTL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_MMR_FW_EDC_CTL RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_DMSC_WRAP_CBASS_CBASS_VBUSP_CPAC0_FW_P2P_BRIDGE_DST_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RACK_CID_QUEUE RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_RD_BARRIER_QUEUE RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNOOP_CMD_ID_QUEUE RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_DATA_BUF_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_DATA_BUF_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_DATA_BUF_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_DATA_BUF_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_DATA_BUF_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_DATA_BUF RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_RESP_BUF_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_RESP_BUF_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_RESP_BUF_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_RESP_BUF_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_RESP_BUF_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_SNP_RESP_BUF RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WACK_CID_QUEUE RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WR_BARRIER_QUEUE RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WRITE_RESP_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WRITE_RESP_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WRITE_RESP_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_WRITE_RESP RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_1 RAM ID

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_groupEntries[SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_EN_MSMC_P0_BUSECC_MSMC_CMD_BUFFER RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR0_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_groupEntries[SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI RAM ID

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_5_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_5_MemEntries[SDL_COMPUTE_CLUSTER0_5_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_5

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_ECC_AGGR_COREPAC_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_CORE_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_CORE_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_CORE_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_SCR1_SCR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_SCR1_SCR_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_SCR1_SCR_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_SCR1_SCR_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_5_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_6_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_6_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_7_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_7_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_8_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_8_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_9_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_9_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_10_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_10_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_11_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_11_WIDTH },
    { SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_12_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_A72_J7_1MB_WRAP_A72_DUAL_MID_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL RAM ID

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_SRC_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_GROUP_0_WIDTH },
    { SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_GROUP_1_WIDTH },
    { SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_GROUP_2_WIDTH },
    { SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_DST_VBUSS RAM ID

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_M2M_M2M_VBUSS RAM ID

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_VBUSP_CFG_DST_M2P_DST_BUSECC RAM ID

SDL_COMPUTE_CLUSTER0_6_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_6_MemEntries[SDL_COMPUTE_CLUSTER0_6_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_ICB_RAMECC_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_ICB_RAMECC_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_ICB_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_ITE_RAMECC_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_ITE_RAMECC_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_ITE_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_LPI_RAMECC_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_LPI_RAMECC_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_LPI_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_6

SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0 RAM ID

SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0 RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_HC2_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_HC2_SCR_J7VC_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_HC2_SCR_J7VC_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_HC2_SCR_J7VC_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_HC2_SCR_J7VC_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_J7VC_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_J7VC_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_J7VC_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SCR_J7VC_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SCR_J7VC_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SCR_J7VC_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_ERR_SCR_J7VC_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_IJ7VC_MAIN_HC2_FW_CBASS_0_J7VC_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_IJ7VC_MAIN_HC2_FW_CBASS_0_J7VC_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_IJ7VC_MAIN_HC2_FW_CBASS_0_J7VC_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_IJ7VC_MAIN_HC2_FW_CBASS_0_J7VC_MAIN_HC2_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC2_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_RD_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_RD_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_RD_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_RD_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_RD_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_RD_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_WR_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_WR_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_WR_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_WR_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_WR_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_IPCIE_G3X4_128_MAIN_1_PCIE_MST_WR_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTR0_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTR0_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTR0_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTR0_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTR0_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTR0_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTW0_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTW0_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTW0_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTW0_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTW0_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_IUSB3P0SS_16FFC_MAIN_0_MSTW0_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_HC_ECC_AGGR5_J7VC_MAIN_HC_ECC_AGGR_EDC_CTRL RAM ID

SDL_MSRAM_512K0_0_MemEntries

const SDL_MemConfig_t SDL_MSRAM_512K0_0_MemEntries[SDL_MSRAM_512K0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MSRAM_512K0_0

SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0 RAM ID

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL RAM ID

SDL_PDMA9_0_MemEntries

const SDL_MemConfig_t SDL_PDMA9_0_MemEntries[SDL_PDMA9_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA9_0

SDL_USB0_0_MemEntries

const SDL_MemConfig_t SDL_USB0_0_MemEntries[SDL_USB0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_USB0_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB0_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB0_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_USB0_0

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VC_MVO_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VC_MVO_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VC_MVO_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VC_MVO_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_J7VC_MVO_CC_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SCR_J7VC_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SCR_J7VC_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SCR_J7VC_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SCR_J7VC_MVO_CC_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_J7VC_MVO_CC_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_IRC_FW_CBASS_J7VC_MVO_CC_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_J7VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL RAM ID

SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IJ7VC_DOM0_ECC_AGGR_EDC_CTRL RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_RMST0_MTOG_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_ECC_AGGR16_IDOM0_M2M_MEMBDG_WMST0_MTOG_DST_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_MSRAM_1MB0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_MSRAM_1MB0_0_MemEntries[SDL_MCU_MSRAM_1MB0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_ECC0_RAM_ID, 0x0041C00000u,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_MSRAM_1MB0_0

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0 RAM ID

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL RAM ID

SDL_PCIE1_0_MemEntries

const SDL_MemConfig_t SDL_PCIE1_0_MemEntries[SDL_PCIE1_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_AXI2VBUSM_MST_RAM_ID, 0u,
      SDL_PCIE1_AXI2VBUSM_MST_RAM_SIZE, 4u,
      SDL_PCIE1_AXI2VBUSM_MST_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE1_0

SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0 RAM ID

SDL_PCIE1_1_MemEntries

const SDL_MemConfig_t SDL_PCIE1_1_MemEntries[SDL_PCIE1_1_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PCIE1_1

SDL_PSRAM2KECC0_0_MemEntries

const SDL_MemConfig_t SDL_PSRAM2KECC0_0_MemEntries[SDL_PSRAM2KECC0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_ECC_RAM_ID, 0u,
      SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PSRAM2KECC0_0

SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries[SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0 RAM ID

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS RAM ID

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_J7VC_NAVSS256_NBSS_PHYS_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCAN14_0_MemEntries

const SDL_MemConfig_t SDL_MCAN14_0_MemEntries[SDL_MCAN14_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN14_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02688000u,
      SDL_MCAN14_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN14_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN14_0

SDL_MCAN14_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN14_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN14_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN14_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN14_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN14_CTRL_EDC_VBUSS RAM ID

SDL_MMCSD1_0_MemEntries

const SDL_MemConfig_t SDL_MMCSD1_0_MemEntries[SDL_MMCSD1_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD1_0

SDL_MMCSD1_1_MemEntries

const SDL_MemConfig_t SDL_MMCSD1_1_MemEntries[SDL_MMCSD1_1_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD1_1

SDL_PDMA10_0_MemEntries

const SDL_MemConfig_t SDL_PDMA10_0_MemEntries[SDL_PDMA10_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA10_0

SDL_MCAN10_0_MemEntries

const SDL_MemConfig_t SDL_MCAN10_0_MemEntries[SDL_MCAN10_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN10_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x027A8000u,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN10_0

SDL_MCAN10_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN10_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN10_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN10_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN10_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN10_CTRL_EDC_VBUSS RAM ID

SDL_PSRAMECC0_0_MemEntries

const SDL_MemConfig_t SDL_PSRAMECC0_0_MemEntries[SDL_PSRAMECC0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_ID, 0x0000200000U,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PSRAMECC0_0

SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries[SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0 RAM ID

SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCU_MCAN0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_MCAN0_0_MemEntries[SDL_MCU_MCAN0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x40500000u,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_MCAN0_0

SDL_MCU_MCAN0_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MCAN0_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_MCAN0_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCU_MCAN0_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MCAN0_CTRL_EDC_VBUSS RAM ID

SDL_MCU_SA2_UL0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_SA2_UL0_0_MemEntries[SDL_MCU_SA2_UL0_0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_SA2_UL0_0

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_MemEntries

const SDL_MemConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_MemEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_RD_RAMECC_RAM_ID, 0u,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_RD_RAMECC_RAM_SIZE, 4u,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_WR_RAMECC_RAM_ID, 0u,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_WR_RAMECC_RAM_SIZE, 4u,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_IPPHY_6_CFG_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_IPPHY_SAFE_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_0_J7VC_IPPHY_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_FW_TO_FW_P2P_BRIDGE_J7VC_FW_TO_FW_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_CBASS_MAIN_FW_CBASS_J7VC_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7VC_IPPHY_SAFE_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_IPPHY_0_CFG_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_BR_FROM_PULSAR0_M2P_BRIDGE_BR_FROM_PULSAR0_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_BR_FROM_PULSAR0_M2P_BRIDGE_BR_FROM_PULSAR0_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_BR_FROM_PULSAR0_M2P_BRIDGE_BR_FROM_PULSAR0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_BR_FROM_PULSAR0_M2P_BRIDGE_BR_FROM_PULSAR0_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_J7VC_IPPHY_SAFE_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_J7VC_IPPHY_SAFE_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_J7VC_IPPHY_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_IPPHY_P2P_BRIDGE_J7VC_IPPHY_TO_IPPHY_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_5 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_SAFE_CBASS_0_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_J7VC_IPPHY_SAFE_CBASS_SCR_PULSAR_MST_32M_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_EDC_CTRL_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_EDC_CTRL RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_REASSEMBLY_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_P2M_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_M2P_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_M2P_BUSECC_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_M2P_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_IJ7VC_IPPHY_CBASS_WRAP_0_IJ7VC_IPPHY_TO_IPPHY_STOG_M2P_BUSECC RAM ID

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_groupEntries[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_J7VC_MAIN_SPI_G0_MAIN_0_ECCAGGR_EDC_CTRL RAM ID

SDL_NAVSS0_0_MemEntries

const SDL_MemConfig_t SDL_NAVSS0_0_MemEntries[SDL_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_NAVSS0_0

SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_ECCAGGR0_EDC_CTRL RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_SPINLOCK0_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_MAILBOX0_EDC_CTRL_2 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_TIMERMGR1_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_MODSS_INTA1_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_PROXY0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_SEC_PROXY0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_MODSS_CBASS_VD2GCLK_EDC_CTRL_1 RAM ID

SDL_NAVSS0_1_MemEntries

const SDL_MemConfig_t SDL_NAVSS0_1_MemEntries[SDL_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_NAVSS0_1

SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMAP0_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_RINGACC0_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_UDMASS_INTA0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_MSRAM0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_E_GCLK_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_E_GCLK_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_E_GCLK_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_E_GCLK_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_SCR_E_GCLK_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_SCR_E_GCLK_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_SCR_E_GCLK_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_MCU_PSIL_SCR_E_GCLK_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_DEBUG_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_DEBUG_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_DEBUG_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_DEBUG_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MCASP_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MCASP_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MCASP_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MCASP_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MISC_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MISC_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MISC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_MISC_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_USART_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_USART_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_USART_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PDMA_MAIN_USART_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CPSW9_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CPSW9_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CPSW9_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CPSW9_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_NAVSS_MCU_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_NAVSS_MCU_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_NAVSS_MCU_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_NAVSS_MCU_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_DEBUG_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_DEBUG_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_DEBUG_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_DEBUG_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MCASP_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MCASP_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MCASP_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MCASP_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MISC_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MISC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MISC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_MISC_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_USART_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_USART_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_USART_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PDMA_MAIN_USART_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_CPSW9_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_CPSW9_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_CPSW9_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_CPSW9_PSIL_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA0_EVT_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_MODSS_INTA1_EVT_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CFG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_ECCAGGR0_EDC_CTRL RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_BR_MS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB0_MS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_BR_MS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_DST_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_NB1_MS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_NBSS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_NAVSS0_3_MemEntries

const SDL_MemConfig_t SDL_NAVSS0_3_MemEntries[SDL_NAVSS0_3_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_RAM_ID, 0u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_RAM_SIZE, 4u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_ROW_WIDTH, ((bool)false) },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_WR_SB_RAM_ID, 0u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_WR_SB_RAM_SIZE, 4u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_WR_SB_ROW_WIDTH, ((bool)false) },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_RD_SB_RAM_ID, 0u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_RD_SB_RAM_SIZE, 4u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_RD_SB_ROW_WIDTH, ((bool)false) },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_WR_SB_RAM_ID, 0u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_WR_SB_RAM_SIZE, 4u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_WR_SB_ROW_WIDTH, ((bool)false) },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_RD_SB_RAM_ID, 0u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_RD_SB_RAM_SIZE, 4u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_RD_SB_ROW_WIDTH, ((bool)false) },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_TLBIF_TLB_BANK_RAM_ID, 0u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_TLBIF_TLB_BANK_RAM_SIZE, 4u,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_TLBIF_TLB_BANK_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_NAVSS0_3

SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_ECCAGGR_EDC_CTRL RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_IO_PVU0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_SRC_TOG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_CFG_TOG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_DST_TOG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_DST_TOG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_DST_TOG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_DST_TOG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_DST_TOG_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_PVU0_DST_TOG_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DMA_PVU0_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_FFI_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMA_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_SRC_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_PVU0_CFG_TOG_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_6_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_7_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0 RAM ID

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_NAVSS0_NAVSS256VCL_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0 RAM ID

SDL_MCU_MCAN1_0_MemEntries

const SDL_MemConfig_t SDL_MCU_MCAN1_0_MemEntries[SDL_MCU_MCAN1_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x40540000u,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_MCAN1_0

SDL_MCU_MCAN1_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_MCAN1_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_MCAN1_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCU_MCAN1_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_MCAN1_CTRL_EDC_VBUSS RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_0_MemEntries[SDL_MCU_VC_MCU_ECC_AGGR0_0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_VC_MCU_ECC_AGGR0_0

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU0_PMST_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_PMST_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_P2M_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRM_64B_PCLK3_R5_L0_BRIDGE_REASSEMBLY_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_0_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_FSSMCU_1_CFG_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7VC_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7VC_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7VC_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_J7VC_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_J7VC_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SCR_J7VC_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SCR_J7VC_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SCR_J7VC_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_ERR_SCR_J7VC_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CBASS_MCU_0_J7VC_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3 RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7VC_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7VC_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SCR_J7VC_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SCR_J7VC_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SCR_J7VC_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_ERR_SCR_J7VC_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_FW_CBASS_MCU_0_J7VC_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS0_SAFETY_GASKET_EDC_CTRL RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_I7_MCU_VBUSM_FSS1_SAFETY_GASKET_EDC_CTRL RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_PLL_MMR_MCU_0_J7VC_MCU_PLL_MMR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_SEC_MMR_MCU_0_J7VC_MCU_SEC_MMR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CTRL_MMR_MCU_0_J7VC_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CTRL_MMR_MCU_0_J7VC_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CTRL_MMR_MCU_0_J7VC_MCU_CTRL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_CTRL_MMR_MCU_0_J7VC_MCU_CTRL_MMR_EDC_CTRL_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IJ7VCL_IEXPORT_VBUSM_64B_MST_MCU_0_MST_MTOG_EDC_CTRL RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_BUSECC RAM ID

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_VC_MCU_ECC_AGGR0_J7VC_MCU_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCU_FSS0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_FSS0_0_MemEntries[SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_FSS0_0

SDL_MCU_FSS0_1_MemEntries

const SDL_MemConfig_t SDL_MCU_FSS0_1_MemEntries[SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
      SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
      SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_FSS0_1

SDL_MCU_FSS0_2_MemEntries

const SDL_MemConfig_t SDL_MCU_FSS0_2_MemEntries[SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
      SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
      SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_FSS0_2

SDL_MCU_CPSW0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_CPSW0_0_MemEntries[SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_CPSW0_P1_RX_FIFO_RAM_ID, 0u,
      SDL_MCU_CPSW0_P1_RX_FIFO_RAM_SIZE, 4u,
      SDL_MCU_CPSW0_P1_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_CPSW0_P1_TX_FIFO_RAM_ID, 0u,
      SDL_MCU_CPSW0_P1_TX_FIFO_RAM_SIZE, 4u,
      SDL_MCU_CPSW0_P1_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_CPSW0_EST_RAM_RAM_ID, 0u,
      SDL_MCU_CPSW0_EST_RAM_RAM_SIZE, 4u,
      SDL_MCU_CPSW0_EST_RAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_CPSW0_0

SDL_MCU_I3C0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_I3C0_0_MemEntries[SDL_MCU_I3C0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_I3C0_I3C_IBIR_QUEUE_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_SLV_DDR_RX_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_CMDR_QUEUE_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_SLV_DDR_TX_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_IBI_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_IBI_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_IBI_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_CMD_WRD1_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_CMD_WRD1_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_TX_DATA_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_TX_DATA_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_CMD_WRD0_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_CMD_WRD0_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
    { SDL_MCU_I3C0_I3C_RX_DATA_RAM_ID, 0u,
      SDL_MCU_I3C0_I3C_RX_DATA_RAM_SIZE, 4u,
      SDL_MCU_I3C0_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MCU_I3C0_0

SDL_MCU_I3C0_I3C_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_I3C0_I3C_EDC_CTRL_0_groupEntries[SDL_MCU_I3C0_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_I3C0_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_I3C0_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_I3C0_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_I3C0_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_I3C0_I3C_EDC_CTRL_0 RAM ID

SDL_R5FSS0_0_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_0_MemEntries[SDL_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_0

SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries[SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0 RAM ID

SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL RAM ID

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL RAM ID

SDL_R5FSS0_1_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_1_MemEntries[SDL_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_1

SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries[SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0 RAM ID

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_RMST1_MTOG_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IDOM1_M2M_MEMBDG_WMST1_MTOG_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_ECC_AGGR17_IJ7VC_DOM1_ECC_AGGR_EDC_CTRL RAM ID

SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_groupEntries[SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0 RAM ID

SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_groupEntries[SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0 RAM ID

SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_groupEntries[SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1 RAM ID

SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_groupEntries[SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2 RAM ID

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0 RAM ID

SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries[SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0 RAM ID

SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0_groupEntries[SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCAN8_0_MemEntries

const SDL_MemConfig_t SDL_MCAN8_0_MemEntries[SDL_MCAN8_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN8_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02788000u,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN8_0

SDL_MCAN8_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN8_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN8_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN8_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN8_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN8_CTRL_EDC_VBUSS RAM ID

SDL_MCAN1_0_MemEntries

const SDL_MemConfig_t SDL_MCAN1_0_MemEntries[SDL_MCAN1_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02718000u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN1_0

SDL_MCAN1_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN1_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN1_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN1_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN1_CTRL_EDC_VBUSS RAM ID

SDL_MCAN0_0_MemEntries

const SDL_MemConfig_t SDL_MCAN0_0_MemEntries[SDL_MCAN0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02708000u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN0_0

SDL_MCAN0_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN0_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN0_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN0_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN0_CTRL_EDC_VBUSS RAM ID

SDL_MCAN3_0_MemEntries

const SDL_MemConfig_t SDL_MCAN3_0_MemEntries[SDL_MCAN3_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02738000u,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN3_0

SDL_MCAN3_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN3_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN3_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN3_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN3_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN3_CTRL_EDC_VBUSS RAM ID

SDL_MCAN2_0_MemEntries

const SDL_MemConfig_t SDL_MCAN2_0_MemEntries[SDL_MCAN2_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02728000u,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN2_0

SDL_MCAN2_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN2_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN2_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN2_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN2_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN2_CTRL_EDC_VBUSS RAM ID

SDL_MCAN4_0_MemEntries

const SDL_MemConfig_t SDL_MCAN4_0_MemEntries[SDL_MCAN4_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02748000u,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN4_0

SDL_MCAN4_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN4_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN4_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN4_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN4_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN4_CTRL_EDC_VBUSS RAM ID

SDL_MCAN7_0_MemEntries

const SDL_MemConfig_t SDL_MCAN7_0_MemEntries[SDL_MCAN7_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN7_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02778000u,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN7_0

SDL_MCAN7_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN7_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN7_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN7_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN7_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN7_CTRL_EDC_VBUSS RAM ID

SDL_MCAN6_0_MemEntries

const SDL_MemConfig_t SDL_MCAN6_0_MemEntries[SDL_MCAN6_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN6_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02768000u,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN6_0

SDL_MCAN6_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN6_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN6_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN6_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN6_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN6_CTRL_EDC_VBUSS RAM ID

SDL_MCU_R5FSS0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_R5FSS0_0_MemEntries[SDL_MCU_R5FSS0_0_RAM_IDS_TOTAL_ENTRIES]

static

SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0 RAM ID

SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCU_R5FSS0_1_MemEntries

const SDL_MemConfig_t SDL_MCU_R5FSS0_1_MemEntries[SDL_MCU_R5FSS0_1_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_R5FSS0_1

SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries[SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0 RAM ID

SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCU_NAVSS0_0_MemEntries

const SDL_MemConfig_t SDL_MCU_NAVSS0_0_MemEntries[SDL_MCU_NAVSS0_0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_NAVSS0_0

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_1_MemEntries

const SDL_MemConfig_t SDL_MCU_NAVSS0_1_MemEntries[SDL_MCU_NAVSS0_1_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_MCU_NAVSS0_1

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_E_GCLK_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_NAVSS_PSIL_SCR_E_GCLK_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_2_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_2_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_2 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1 RAM ID

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_NAVSS0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_MMCSD0_0_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_0_MemEntries[SDL_MMCSD0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD0_0

SDL_MMCSD0_1_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_1_MemEntries[SDL_MMCSD0_1_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD0_1

SDL_PDMA5_0_MemEntries

const SDL_MemConfig_t SDL_PDMA5_0_MemEntries[SDL_PDMA5_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_216X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_216X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_216X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_216X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_216X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_216X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_216X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_216X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_216X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_216X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_216X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_216X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA5_0

SDL_MCAN11_0_MemEntries

const SDL_MemConfig_t SDL_MCAN11_0_MemEntries[SDL_MCAN11_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN11_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x027B8000u,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN11_0

SDL_MCAN11_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN11_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN11_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN11_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN11_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN11_CTRL_EDC_VBUSS RAM ID

SDL_MCAN13_0_MemEntries

const SDL_MemConfig_t SDL_MCAN13_0_MemEntries[SDL_MCAN13_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN13_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x027D8000u,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN13_0

SDL_MCAN13_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN13_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN13_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN13_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN13_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN13_CTRL_EDC_VBUSS RAM ID

SDL_MCAN12_0_MemEntries

const SDL_MemConfig_t SDL_MCAN12_0_MemEntries[SDL_MCAN12_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN12_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x027C8000u,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN12_0

SDL_MCAN12_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN12_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN12_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN12_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN12_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN12_CTRL_EDC_VBUSS RAM ID

SDL_MCAN15_0_MemEntries

const SDL_MemConfig_t SDL_MCAN15_0_MemEntries[SDL_MCAN15_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN15_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02698000u,
      SDL_MCAN15_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN15_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN15_0

SDL_MCAN15_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN15_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN15_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN15_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN15_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN15_CTRL_EDC_VBUSS RAM ID

SDL_MCAN17_0_MemEntries

const SDL_MemConfig_t SDL_MCAN17_0_MemEntries[SDL_MCAN17_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN17_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x026B8000u,
      SDL_MCAN17_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN17_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN17_0

SDL_MCAN17_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN17_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN17_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN17_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN17_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN17_CTRL_EDC_VBUSS RAM ID

SDL_MCAN16_0_MemEntries

const SDL_MemConfig_t SDL_MCAN16_0_MemEntries[SDL_MCAN16_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN16_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x026A8000u,
      SDL_MCAN16_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN16_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN16_0

SDL_MCAN16_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN16_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN16_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN16_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN16_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN16_CTRL_EDC_VBUSS RAM ID

SDL_I3C0_0_MemEntries

const SDL_MemConfig_t SDL_I3C0_0_MemEntries[SDL_I3C0_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_I3C0_I3C_IBIR_QUEUE_RAM_ID, 0u,
      SDL_I3C0_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
      SDL_I3C0_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_SLV_DDR_RX_RAM_ID, 0u,
      SDL_I3C0_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
      SDL_I3C0_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_CMDR_QUEUE_RAM_ID, 0u,
      SDL_I3C0_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
      SDL_I3C0_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_SLV_DDR_TX_RAM_ID, 0u,
      SDL_I3C0_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
      SDL_I3C0_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_IBI_RAM_ID, 0u,
      SDL_I3C0_I3C_IBI_RAM_SIZE, 4u,
      SDL_I3C0_I3C_IBI_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_CMD_WRD1_RAM_ID, 0u,
      SDL_I3C0_I3C_CMD_WRD1_RAM_SIZE, 4u,
      SDL_I3C0_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_TX_DATA_RAM_ID, 0u,
      SDL_I3C0_I3C_TX_DATA_RAM_SIZE, 4u,
      SDL_I3C0_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_CMD_WRD0_RAM_ID, 0u,
      SDL_I3C0_I3C_CMD_WRD0_RAM_SIZE, 4u,
      SDL_I3C0_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
    { SDL_I3C0_I3C_RX_DATA_RAM_ID, 0u,
      SDL_I3C0_I3C_RX_DATA_RAM_SIZE, 4u,
      SDL_I3C0_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_I3C0_0

SDL_I3C0_I3C_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_I3C0_I3C_EDC_CTRL_0_groupEntries[SDL_I3C0_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_I3C0_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_I3C0_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_I3C0_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_I3C0_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_I3C0_I3C_EDC_CTRL_0 RAM ID

SDL_MCAN9_0_MemEntries

const SDL_MemConfig_t SDL_MCAN9_0_MemEntries[SDL_MCAN9_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN9_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02798000u,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN9_0

SDL_MCAN9_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN9_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN9_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN9_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN9_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN9_CTRL_EDC_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_0_MemEntries

const SDL_MemConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_0_MemEntries[SDL_VC_MAIN_RC_ECC_AGGR4_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_RD_RAMECC_RAM_ID, 0u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_RD_RAMECC_RAM_SIZE, 4u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_WR_RAMECC_RAM_ID, 0u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_WR_RAMECC_RAM_SIZE, 4u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_WR_RAMECC_RAM_ID, 0u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_WR_RAMECC_RAM_SIZE, 4u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_RD_RAMECC_RAM_ID, 0u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_RD_RAMECC_RAM_SIZE, 4u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_WR_RAMECC_RAM_ID, 0u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_WR_RAMECC_RAM_SIZE, 4u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_RD_RAMECC_RAM_ID, 0u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_RD_RAMECC_RAM_SIZE, 4u,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_VC_MAIN_RC_ECC_AGGR4_0

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_REASSEMBLY_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_GPMC_STOG_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2GPMC_0_CFG_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_J7VC_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7VC_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2CFG_0_CFG_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_HC2_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_IPPHY_P2P_BRIDGE_J7VC_RC_TO_IPPHY_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_PULSAR0_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_64M_SCR_J7VC_RC_CBASS_SCR_MST_64M_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_P2P_BRIDGE_ISLAVE_SAFETY_GASKET_MAIN_RC2PCIE_1_CFG_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_HC2_STOG_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_MCU_TO_IPPHY_P2P_BRIDGE_J7VC_RC_MCU_TO_IPPHY_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_MCU_DIRECT_M2P_BRIDGE_BR_TO_32P_MCU_DIRECT_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SCR_J7VC_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SCR_J7VC_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SCR_J7VC_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ERR_SCR_J7VC_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_32P_SCR_J7VC_RC_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_32P_SCR_J7VC_RC_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_32P_SCR_J7VC_RC_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_32P_SCR_J7VC_RC_CBASS_SCR_MST_32P_SCR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_IPPHY_TO_RC_P2P_BRIDGE_J7VC_IPPHY_TO_RC_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_RC_TO_RC_CFG_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_J7VC_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_J7VC_HC2_TO_RC_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7VC_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_32P_P2M_BRIDGE_BR_FROM_32P_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_SCR_MST_128M_SCR_J7VC_RC_CBASS_SCR_MST_128M_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MTOG_0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MTOG_0_EDC_CTRL_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7VC_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7VC_RC_CBASS_INAVSS256VCL_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_J7VC_RC_TO_RC_CFG_M2P_BRIDGE_J7VC_RC_TO_RC_CFG_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_J7VC_RC_TO_RC_CFG_M2P_BRIDGE_J7VC_RC_TO_RC_CFG_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_J7VC_RC_TO_RC_CFG_M2P_BRIDGE_J7VC_RC_TO_RC_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_J7VC_RC_TO_RC_CFG_M2P_BRIDGE_J7VC_RC_TO_RC_CFG_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_TO_RC_CFG_STOG_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_0_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_0_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_0_EDC_CTRL_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_MTOG_0_EDC_CTRL RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7VC_RC_CBASS_ICOMPUTE_CLUSTER_J7VCL_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_BR_TO_32P_M2P_BRIDGE_BR_TO_32P_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CBASS_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_J7VC_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IJ7VC_RC_CFG_CBASS_J7VC_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IRC_FW_CBASS_J7VC_RC_CBASS_MAIN_FW_CBASS_J7VC_TO_J7VC_RC_FW_CBAS_P2P_BRIDGE_J7VC_TO_J7VC_RC_FW_CBAS_BRIDGE_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_DST_M2P_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS RAM ID

SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_VC_MAIN_RC_ECC_AGGR4_J7VC_MAIN_RC_ECC_AGGR_EDC_CTRL RAM ID

SDL_MCAN5_0_MemEntries

const SDL_MemConfig_t SDL_MCAN5_0_MemEntries[SDL_MCAN5_0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN5_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x02758000u,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN5_0

SDL_MCAN5_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN5_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN5_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN5_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN5_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN5_CTRL_EDC_VBUSS RAM ID

SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_RamIdTable[SDL_VCL_MAIN_INFRA_ECC_AGGR0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VCL_MAIN_INFRA_ECC_AGGR0_0

SDL_CPSW0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_CPSW0_0_RamIdTable[SDL_CPSW0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CPSW0_0

SDL_MCU_ADC0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_ADC0_0_RamIdTable[SDL_MCU_ADC0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
      SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
      SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
      SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
      SDL_MCU_ADC0_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_ADC0_0

SDL_MCU_ADC1_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_ADC1_0_RamIdTable[SDL_MCU_ADC1_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
      SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
      SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
      SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
      SDL_MCU_ADC1_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_ADC1_0

SDL_MCU_I3C1_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_I3C1_0_RamIdTable[SDL_MCU_I3C1_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_I3C1_0

SDL_MCU_I3C1_1_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_I3C1_1_RamIdTable[SDL_MCU_I3C1_1_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_I3C1_I3C_EDC_CTRL_0_RAM_ID,
      SDL_MCU_I3C1_I3C_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_I3C1_I3C_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_I3C1_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_I3C1_I3C_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_I3C1_1

SDL_COMPUTE_CLUSTER0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_0_RamIdTable[SDL_COMPUTE_CLUSTER0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_0

SDL_COMPUTE_CLUSTER0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_1_RamIdTable[SDL_COMPUTE_CLUSTER0_1_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_1

SDL_COMPUTE_CLUSTER0_2_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_2_RamIdTable[SDL_COMPUTE_CLUSTER0_2_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_2

SDL_COMPUTE_CLUSTER0_3_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_3_RamIdTable[SDL_COMPUTE_CLUSTER0_3_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_3

SDL_COMPUTE_CLUSTER0_4_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_4_RamIdTable[SDL_COMPUTE_CLUSTER0_4_NUM_RAMS]

static

Initial value:

=
{
    { SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_RAM_ID,
      SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_ECC_TYPE,
      SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS,
      SDL_COMPUTE_CLUSTER0_DDRSS0_ASAFE_SI_groupEntries },
    { SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_RAM_ID,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_ECC_TYPE,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_COMPUTE_CLUSTER0_VBUSP_CFG_ECC_AGGR2_P2P_DST_BUSECC_groupEntries },
    { SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_RAM_ID,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_INJECT_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_ECC_TYPE,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_COMPUTE_CLUSTER0_MSMC_J7VCL_ECC_AGGR2_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_4

SDL_COMPUTE_CLUSTER0_5_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_5_RamIdTable[SDL_COMPUTE_CLUSTER0_5_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_5

SDL_COMPUTE_CLUSTER0_6_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_6_RamIdTable[SDL_COMPUTE_CLUSTER0_6_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_6

SDL_VC_MAIN_HC_ECC_AGGR5_0_RamIdTable

const SDL_RAMIdEntry_t SDL_VC_MAIN_HC_ECC_AGGR5_0_RamIdTable[SDL_VC_MAIN_HC_ECC_AGGR5_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VC_MAIN_HC_ECC_AGGR5_0

SDL_MSRAM_512K0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_512K0_0_RamIdTable[SDL_MSRAM_512K0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
    { SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MSRAM_512K0_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_512K0_0

SDL_PDMA9_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA9_0_RamIdTable[SDL_PDMA9_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_RAM_ID,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_RAM_ID,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_RAM_ID,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_RAM_ID,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA9_PDMA_J7VC_MAIN_SPI_G0_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA9_0

SDL_USB0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_USB0_0_RamIdTable[SDL_USB0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_USB0_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB0_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB0_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_USB0_0

SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0_RamIdTable

const SDL_RAMIdEntry_t SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0_RamIdTable[SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_0

SDL_IDOM0_ECC_AGGR16_0_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM0_ECC_AGGR16_0_RamIdTable[SDL_IDOM0_ECC_AGGR16_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM0_ECC_AGGR16_0

SDL_WKUP_VTM0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_VTM0_0_RamIdTable[SDL_WKUP_VTM0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_VTM0_0

SDL_MCU_MSRAM_1MB0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_MSRAM_1MB0_0_RamIdTable[SDL_MCU_MSRAM_1MB0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_MSRAM_1MB0_0

SDL_PCIE1_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE1_0_RamIdTable[SDL_PCIE1_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_RAM_ID,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_INJECT_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_ECC_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXIMFIFO_INJECT_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXIMFIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISFIFO_INJECT_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISFIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_DIBRAM_INJECT_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_DIBRAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE1_AXI2VBUSM_MST_RAM_ID,
      SDL_PCIE1_AXI2VBUSM_MST_INJECT_TYPE,
      SDL_PCIE1_AXI2VBUSM_MST_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE1_0

SDL_PCIE1_1_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE1_1_RamIdTable[SDL_PCIE1_1_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_PNPFIFO_INJECT_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_PNPFIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RXCPLFIFO_INJECT_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RPLYBUF_INJECT_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_RPLYBUF_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISRODR_INJECT_TYPE,
      SDL_PCIE1_PCIE_G3X4_128_CORE_DBN_WRAP_RAMS_AXISRODR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE1_1

SDL_PSRAM2KECC0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PSRAM2KECC0_0_RamIdTable[SDL_PSRAM2KECC0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_ECC_RAM_ID,
      SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_PSRAM2KECC0_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PSRAM2KECC0_0

SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0_RamIdTable

const SDL_RAMIdEntry_t SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0_RamIdTable[SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_0

SDL_MCAN14_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN14_0_RamIdTable[SDL_MCAN14_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN14_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN14_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN14_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN14_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN14_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN14_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN14_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN14_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN14_0

SDL_MMCSD1_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD1_0_RamIdTable[SDL_MMCSD1_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD1_0

SDL_MMCSD1_1_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD1_1_RamIdTable[SDL_MMCSD1_1_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD1_1

SDL_PDMA10_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA10_0_RamIdTable[SDL_PDMA10_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_RAM_ID,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F0_TPRAM_64X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_RAM_ID,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_TF0_F1_TPRAM_64X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_RAM_ID,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F0_TPRAM_64X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_RAM_ID,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA10_PDMA_J7VC_MAIN_SPI_G1_PDMA_CORE_RF0_F1_TPRAM_64X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA10_0

SDL_MCAN10_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN10_0_RamIdTable[SDL_MCAN10_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN10_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN10_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN10_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN10_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN10_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN10_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN10_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN10_0

SDL_PSRAMECC0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PSRAMECC0_0_RamIdTable[SDL_PSRAMECC0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_ECC_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries },
    { SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_PSRAMECC0_PSRAM256X32E_16FFC_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PSRAMECC0_0

SDL_MCU_MCAN0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_MCAN0_0_RamIdTable[SDL_MCU_MCAN0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MCAN0_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCU_MCAN0_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCU_MCAN0_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCU_MCAN0_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCU_MCAN0_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_MCAN0_0

SDL_MCU_SA2_UL0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_SA2_UL0_0_RamIdTable[SDL_MCU_SA2_UL0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_SA2_UL0_0

SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_RamIdTable

const SDL_RAMIdEntry_t SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_RamIdTable[SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6_0

SDL_NAVSS0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS0_0_RamIdTable[SDL_NAVSS0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS0_0

SDL_NAVSS0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS0_1_RamIdTable[SDL_NAVSS0_1_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS0_1

SDL_NAVSS0_2_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS0_2_RamIdTable[SDL_NAVSS0_2_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS0_2

SDL_NAVSS0_3_RamIdTable

const SDL_RAMIdEntry_t SDL_NAVSS0_3_RamIdTable[SDL_NAVSS0_3_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_NAVSS0_3

SDL_MCU_MCAN1_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_MCAN1_0_RamIdTable[SDL_MCU_MCAN1_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCU_MCAN1_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCU_MCAN1_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCU_MCAN1_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCU_MCAN1_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCU_MCAN1_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_MCAN1_0

SDL_MCU_VC_MCU_ECC_AGGR0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_VC_MCU_ECC_AGGR0_0_RamIdTable[SDL_MCU_VC_MCU_ECC_AGGR0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_VC_MCU_ECC_AGGR0_0

SDL_MCU_FSS0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_FSS0_0_RamIdTable[SDL_MCU_FSS0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_FSS0_0

SDL_MCU_FSS0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_FSS0_1_RamIdTable[SDL_MCU_FSS0_1_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID,
      SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
      SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_FSS0_1

SDL_MCU_FSS0_2_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_FSS0_2_RamIdTable[SDL_MCU_FSS0_2_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID,
      SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
      SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_FSS0_2

SDL_MCU_CPSW0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_CPSW0_0_RamIdTable[SDL_MCU_CPSW0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_CPSW0_0

SDL_MCU_I3C0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_I3C0_0_RamIdTable[SDL_MCU_I3C0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_I3C0_0

SDL_MCU_I3C0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_I3C0_1_RamIdTable[SDL_MCU_I3C0_1_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCU_I3C0_I3C_EDC_CTRL_0_RAM_ID,
      SDL_MCU_I3C0_I3C_EDC_CTRL_0_INJECT_TYPE,
      SDL_MCU_I3C0_I3C_EDC_CTRL_0_ECC_TYPE,
      SDL_MCU_I3C0_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_MCU_I3C0_I3C_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_I3C0_1

SDL_R5FSS0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_0_RamIdTable[SDL_R5FSS0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_0

SDL_R5FSS0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_1_RamIdTable[SDL_R5FSS0_1_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_1

SDL_IDOM1_ECC_AGGR17_0_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM1_ECC_AGGR17_0_RamIdTable[SDL_IDOM1_ECC_AGGR17_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM1_ECC_AGGR17_0

SDL_DDR0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_DDR0_0_RamIdTable[SDL_DDR0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_RAM_ID,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_INJECT_TYPE,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_ECC_TYPE,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_VEDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DDR0_0

SDL_DDR0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_DDR0_1_RamIdTable[SDL_DDR0_1_NUM_RAMS]

static

Initial value:

=
{
    { SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_RAM_ID,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_INJECT_TYPE,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_ECC_TYPE,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_0_groupEntries },
    { SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_RAM_ID,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_INJECT_TYPE,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_ECC_TYPE,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_MAX_NUM_CHECKERS,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_1_groupEntries },
    { SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_RAM_ID,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_INJECT_TYPE,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_ECC_TYPE,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_MAX_NUM_CHECKERS,
      SDL_DDR0_VBUSMC2AXI_V256D32E_D_HEDC_CTRL_2_groupEntries },
    { SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_RAM_ID,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_INJECT_TYPE,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_ECC_TYPE,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries },
    { SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_RAM_ID,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_INJECT_TYPE,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_ECC_TYPE,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_DDR0_DDR32V256SS_16FFC_EW_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_DST_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DDR0_1

SDL_DDR0_2_RamIdTable

const SDL_RAMIdEntry_t SDL_DDR0_2_RamIdTable[SDL_DDR0_2_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DDR0_2

SDL_MCAN8_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN8_0_RamIdTable[SDL_MCAN8_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN8_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN8_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN8_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN8_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN8_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN8_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN8_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN8_0

SDL_MCAN1_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN1_0_RamIdTable[SDL_MCAN1_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN1_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN1_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN1_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN1_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN1_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN1_0

SDL_MCAN0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN0_0_RamIdTable[SDL_MCAN0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN0_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN0_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN0_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN0_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN0_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN0_0

SDL_MCAN3_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN3_0_RamIdTable[SDL_MCAN3_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN3_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN3_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN3_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN3_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN3_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN3_0

SDL_MCAN2_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN2_0_RamIdTable[SDL_MCAN2_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN2_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN2_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN2_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN2_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN2_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN2_0

SDL_MCAN4_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN4_0_RamIdTable[SDL_MCAN4_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN4_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN4_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN4_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN4_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN4_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN4_0

SDL_MCAN7_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN7_0_RamIdTable[SDL_MCAN7_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN7_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN7_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN7_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN7_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN7_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN7_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN7_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN7_0

SDL_MCAN6_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN6_0_RamIdTable[SDL_MCAN6_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN6_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN6_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN6_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN6_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN6_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN6_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN6_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN6_0

SDL_MCU_R5FSS0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_0_RamIdTable[SDL_MCU_R5FSS0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_R5FSS0_0

SDL_MCU_R5FSS0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_1_RamIdTable[SDL_MCU_R5FSS0_1_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_R5FSS0_1

SDL_MCU_NAVSS0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_NAVSS0_0_RamIdTable[SDL_MCU_NAVSS0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_NAVSS0_0

SDL_MCU_NAVSS0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_NAVSS0_1_RamIdTable[SDL_MCU_NAVSS0_1_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_NAVSS0_1

SDL_MMCSD0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_0_RamIdTable[SDL_MMCSD0_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_0

SDL_MMCSD0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_1_RamIdTable[SDL_MMCSD0_1_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_1

SDL_PDMA5_0_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA5_0_RamIdTable[SDL_PDMA5_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_216X128_SBW_SR_RAM_ID,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_216X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_216X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_216X128_SBW_SR_RAM_ID,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_216X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_216X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_216X144_SBW_SR_RAM_ID,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_216X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_216X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_216X144_SBW_SR_RAM_ID,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_216X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA5_PDMA_J7VC_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_216X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA5_0

SDL_MCAN11_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN11_0_RamIdTable[SDL_MCAN11_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN11_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN11_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN11_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN11_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN11_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN11_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN11_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN11_0

SDL_MCAN13_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN13_0_RamIdTable[SDL_MCAN13_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN13_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN13_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN13_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN13_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN13_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN13_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN13_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN13_0

SDL_MCAN12_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN12_0_RamIdTable[SDL_MCAN12_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN12_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN12_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN12_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN12_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN12_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN12_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN12_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN12_0

SDL_MCAN15_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN15_0_RamIdTable[SDL_MCAN15_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN15_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN15_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN15_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN15_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN15_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN15_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN15_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN15_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN15_0

SDL_MCAN17_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN17_0_RamIdTable[SDL_MCAN17_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN17_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN17_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN17_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN17_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN17_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN17_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN17_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN17_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN17_0

SDL_MCAN16_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN16_0_RamIdTable[SDL_MCAN16_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN16_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN16_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN16_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN16_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN16_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN16_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN16_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN16_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN16_0

SDL_I3C0_0_RamIdTable

const SDL_RAMIdEntry_t SDL_I3C0_0_RamIdTable[SDL_I3C0_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_I3C0_0

SDL_I3C0_1_RamIdTable

const SDL_RAMIdEntry_t SDL_I3C0_1_RamIdTable[SDL_I3C0_1_NUM_RAMS]

static

Initial value:

=
{
    { SDL_I3C0_I3C_EDC_CTRL_0_RAM_ID,
      SDL_I3C0_I3C_EDC_CTRL_0_INJECT_TYPE,
      SDL_I3C0_I3C_EDC_CTRL_0_ECC_TYPE,
      SDL_I3C0_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_I3C0_I3C_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_I3C0_1

SDL_MCAN9_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN9_0_RamIdTable[SDL_MCAN9_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN9_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN9_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN9_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN9_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN9_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN9_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN9_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN9_0

SDL_VC_MAIN_RC_ECC_AGGR4_0_RamIdTable

const SDL_RAMIdEntry_t SDL_VC_MAIN_RC_ECC_AGGR4_0_RamIdTable[SDL_VC_MAIN_RC_ECC_AGGR4_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_VC_MAIN_RC_ECC_AGGR4_0

SDL_MCAN5_0_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN5_0_RamIdTable[SDL_MCAN5_0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN5_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN5_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN5_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN5_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN5_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN5_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN5_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN5_0

SDL_ECC_aggrBaseAddressTable

SDL_ecc_aggrRegs* const SDL_ECC_aggrBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES]

static

This structure holds the base addresses for each memory subtype in MCU domain

---

SDL_ECC_aggrHighBaseAddressTable

uint64_t const SDL_ECC_aggrHighBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]

static

Initial value:

=
{
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MPU0_COREPAC_ECC_AGGR_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MPU0_CORE0_ECC_AGGR_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MPU0_CORE1_ECC_AGGR_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_VBUS_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_CTL_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_CFG_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_BASE,
}

SDL_ECC_aggrHighBaseAddressTableTrans

SDL_ecc_aggrRegs* SDL_ECC_aggrHighBaseAddressTableTrans[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]

SDL_ECC_aggrTable

const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]

static