SDL API Guide for J7200
pbist/V0/sdl_ip_pbist.h
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33 
49 #ifndef SDL_IP_PBIST_H_
50 #define SDL_IP_PBIST_H_
51 
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55 
56 #include <stdint.h>
57 #include <stdbool.h>
58 #include <src/ip/sdlr_pbist.h>
59 
88 typedef struct
89 {
92  uint32_t override;
93 
99  uint32_t algorithmsBitMap;
100 
104 
107  uint64_t scrambleValue;
109 
119 typedef struct
120 {
123  uint32_t CA0;
124 
127  uint32_t CA1;
128 
131  uint32_t CA2;
132 
135  uint32_t CA3;
136 
139  uint32_t CL0;
140 
143  uint32_t CL1;
144 
147  uint32_t CL2;
148 
151  uint32_t CL3;
152 
155  uint32_t CMS;
156 
159  uint32_t CSR;
160 
163  uint32_t I0;
164 
167  uint32_t I1;
168 
171  uint32_t I2;
172 
175  uint32_t I3;
176 
179  uint32_t RAMT;
181 
203 int32_t SDL_PBIST_softReset(SDL_pbistRegs *pPBISTRegs);
204 
218 int32_t SDL_PBIST_start(SDL_pbistRegs *pPBISTRegs,
219  const SDL_PBIST_config * pConfig);
220 
234 int32_t SDL_PBIST_startNeg(SDL_pbistRegs *pPBISTRegs,
235  const SDL_PBIST_configNeg *pConfig);
236 
250 int32_t SDL_PBIST_checkResult (const SDL_pbistRegs *pPBISTRegs, bool *pResult);
251 
265 int32_t SDL_PBIST_releaseTestMode(SDL_pbistRegs *pPBISTRegs);
266 
269 #ifdef __cplusplus
270 }
271 #endif
272 
273 #endif /* SDL_IP_PBIST_H_ */
uint32_t CL1
Definition: pbist/V0/sdl_ip_pbist.h:143
uint32_t CA3
Definition: pbist/V0/sdl_ip_pbist.h:135
uint64_t memoryGroupsBitMap
Definition: pbist/V0/sdl_ip_pbist.h:103
uint32_t CL0
Definition: pbist/V0/sdl_ip_pbist.h:139
uint32_t CA0
Definition: pbist/V0/sdl_ip_pbist.h:123
This structure contains the different configuration used for PBIST for the failure insertion test to ...
Definition: pbist/V0/sdl_ip_pbist.h:119
int32_t SDL_PBIST_releaseTestMode(SDL_pbistRegs *pPBISTRegs)
PBIST Release Test mode.
This structure contains the different configuration used for PBIST.
Definition: pbist/V0/sdl_ip_pbist.h:88
uint32_t RAMT
Definition: pbist/V0/sdl_ip_pbist.h:179
uint32_t CL3
Definition: pbist/V0/sdl_ip_pbist.h:151
int32_t SDL_PBIST_softReset(SDL_pbistRegs *pPBISTRegs)
PBIST Soft reset.
uint32_t CA1
Definition: pbist/V0/sdl_ip_pbist.h:127
uint32_t I3
Definition: pbist/V0/sdl_ip_pbist.h:175
uint32_t I2
Definition: pbist/V0/sdl_ip_pbist.h:171
uint32_t CMS
Definition: pbist/V0/sdl_ip_pbist.h:155
uint64_t scrambleValue
Definition: pbist/V0/sdl_ip_pbist.h:107
uint32_t CSR
Definition: pbist/V0/sdl_ip_pbist.h:159
uint32_t I0
Definition: pbist/V0/sdl_ip_pbist.h:163
uint32_t CA2
Definition: pbist/V0/sdl_ip_pbist.h:131
int32_t SDL_PBIST_checkResult(const SDL_pbistRegs *pPBISTRegs, bool *pResult)
PBIST check result.
int32_t SDL_PBIST_startNeg(SDL_pbistRegs *pPBISTRegs, const SDL_PBIST_configNeg *pConfig)
PBIST Failure Insertion Test Start.
uint32_t CL2
Definition: pbist/V0/sdl_ip_pbist.h:147
int32_t SDL_PBIST_start(SDL_pbistRegs *pPBISTRegs, const SDL_PBIST_config *pConfig)
PBIST Start.
uint32_t I1
Definition: pbist/V0/sdl_ip_pbist.h:167
uint32_t algorithmsBitMap
Definition: pbist/V0/sdl_ip_pbist.h:99