4.16.1. IO Retetion Mode

LPM library provides a means on J7200 to move between Active mode and IO Retention mode.

4.16.1.1. Use Case Requirements & Overview

4.16.1.1.1. Hardware Modifications

  • To enable MAIN Domain
    • It is a requirement that R74 be moved to R610 on the J7200 SOM in order for this demo to be run!
    • The user may also want to solder a wire to one of the ends of R92 at a TP.
  • To enable MCU Domain

    • Go to the SOM schematic and search for the phrase “Retention mode” to see all necessary resistor changes.

    • As of 02/25/2022, the changes are:
      • R250 -> R249
      • R304 -> R153
      • R139 -> R298
      • Populate R61
      • Replace R73 with a 10K pull-up resistor instead of a pull-down resistor on pin 2 of U13.
  • To enable both MCU and MAIN Domain simultaneously
    • This requires more significant changes overall
    • Please see the PDF schematic attached to the EVM user guide with specific instructions on each change

4.16.1.1.2. Scope of Work

Scope would be to implement a Low Power Manager (LPM) running on MCU R5 core, with APIs to switch to and from IO Retention mode to ACTIVE mode on J7200 device with dual Leo + Hera PDN. When we come back from IO Retention to ACTIVE mode, programs can be executed on all other active cores. Following Table summarizes the scope of work:

Is Is Not
Boot in ACTIVE mode and then switch to GPIO retention mode Boot in MCU only mode and switch to GPIO retention mode
Trigger interrupt to switch from GPIO retention mode into Active mode Trigger interrupt to switch into MCU Only mode
CAN or GPIO event to wakeup the PMIC from GPIO retention into active mode  
Support for A72 running Linux and other cores running FreeRTOS Support for QNX on A72
Assumes strict isolation of access - MCU SW only access MCU domain resources and Main domain SW accesses Main domain resources Cross domain access - MCU SW accessing Main domain resources or Main Domain SW accessing MCU domain resources
FreeRTOS based app showcasing use of LPM running on MCU1_0 AutoSAR on MCU1_0
Capable of enabling MAIN and MCU Domain IOs in retention low power mode  

4.16.1.1.3. Verification & Results

There are three test points on the J7200 EVM’s SoM board which can be used to validate the PMIC state. * TP29 → H_MCU_PORz * TP46 → H_SOC_PORz * TP53 → VDD_WAKE0

Mode Test Point Expected Voltage
ACTIVE TP29 1.8 V
ACTIVE TP46 1.8 V
ACTIVE TP53 0.8 V
IO Retention TP29 0 V
IO Retention TP46 0 V
IO Retention TP53 0.8 V

4.16.1.1.4. Benchmarking

The amount of time from an external wakeup trigger to the beginning of appimage execution on MCU1_0 can be acquired by means of probing test points.

# Step Mode
1 Power on the board with IO Retention appimage loaded POWER OFF
2 Press “1, 2, or 3” to send the board to IO Retention mode ACTIVE
3 Probe R92 and manually trigger CAN0 or SW1 IO RETENTION
4 Probe TP84 for GPIO Response at beginning of appimage on MCU1_0 ACTIVE
  • Measure the amount of time between the falling edge on R92 in step 3 and the rising edge of TP84 in step 4.
  • GPIO triggers can be placed in the SBL to get the earliest possible response from MCU1_0 (instead of the earliest appimage execution response). Similarly, GPIO responses can be placed at the beginnning of appimages for any core other than MCU1_0.

4.16.1.1.5. Details on call sequence

  • MAIN Domain Interrupts:
    • CAN0 & CAN1
  • MCU Domain Interrupts:
    • MCU_CAN0 & MCU_CAN1
# Description Executed from Affects Comments
1 Boot in ACTIVE mode     Cold boot in ACTIVE mode SBL boot sequence
2 Configure DMSC to Allow Falling Edge HW Interrupt in IO Retention Mode MCU1_0 M3  
3 Trigger PMIC sequence for ACTIVE to MCU/MAIN IO Retention transition MCU1_0 PMIC Enter IO retention state
4 Measure relevant power rails to assure that we are in IO retention N/A   https://www.ti.com/lit/ug/slvuby7/slvuby7.pdf#page=4 https://www.ti.com/lit/ug/slvuby7/slvuby7.pdf#page=5
5 Trigger appropriate MAIN/MCU HW Interrupt wakeup PMIC into Active Mode External User - Hardware All Cores SBL boot sequence  
6 Detect boot from IO Retention Mode and trigger TP84 GPIO rising edge for timing MCU1_0 M3 M3 regs are non-volatile in IO retention mode, so they can be read to see if they are not at reset values. If they are not, respond with UART + GPIO trigger for timing
7 Run appimage on MCU2_0 to display full reboot MCU1_0 MCU2_0 MCU2_0 IPC triggers mcu2_0 appimage Upon completion, mcu2_0 appimage sends IPC → MCU1_0 to move device back into IO retention mode

4.16.1.2. Steps to build and run the demo

4.16.1.2.1. Build commands

make lpm_io_retention_freertos SOC=j7200 BOARD=j7200_evm -sj
  • Then generate a multicore image with any other appimages that you would like for any core other than mcu1_0.
  • OR just use the lpm_io_retention_freertos appimage to just test moving between io retention and active mode.

4.16.1.2.2. How to run the demo

4.16.1.2.3. Flashing boot binaries to OSPI

sudo ~/ti/uniflash_6.2.0/dslite.sh --mode processors -c /dev/ttyUSB1 -f <path-to-uart_j7200_evm_flash_programmer_release.tiimage> -i 0
sudo ~/ti/uniflash_6.2.0/dslite.sh --mode processors -c /dev/ttyUSB1 -f <path-to-sbl_cust_img_mcu1_0_release.tiimage> -d 3 -o 0
sudo ~/ti/uniflash_6.2.0/dslite.sh --mode processors -c /dev/ttyUSB1 -f <path-to-tifs.bin> -d 3 -o 80000
sudo ~/ti/uniflash_6.2.0/dslite.sh --mode processors -c /dev/ttyUSB1 -f <path-to-appimage> -d 3 -o 100000
sudo ~/ti/uniflash_6.2.0/dslite.sh --mode processors -c /dev/ttyUSB1 -f <path-to-nor_spi_patterns.bin> -d 3 -o 3FC0000
  • SD boot not supported