4.9.7.2. J7200 Peripheral Interrupt Destination Descriptions

4.9.7.2.1. Introduction

This chapter provides information on processor interrupt destination IDs that are permitted in the j7200 SoC. The interrupt destination IDs represent inputs to SoC processor interrupt controllers or the processors themselves. The System Firmware interrupt management TISCI message APIs take interrupt destination IDs as input to set and release interrupt routes between source peripherals and destination processors.

Warning

Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.

4.9.7.2.2. Interrupt Destination IDs

Destination Device Name Destination Device ID Interrupt Destination Description Interrupt Destination Input Index
J7200_DEV_COMPUTE_CLUSTER0_GIC500SS (Reserved by System Firmware) 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0 64 to 73
J7200_DEV_COMPUTE_CLUSTER0_GIC500SS 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0 74 to 127
J7200_DEV_COMPUTE_CLUSTER0_GIC500SS 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from GPIOMUX_INTRTR0 392 to 447
J7200_DEV_COMPUTE_CLUSTER0_GIC500SS 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0 448 to 511
J7200_DEV_COMPUTE_CLUSTER0_GIC500SS 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from CMPEVENT_INTRTR0 544 to 547
J7200_DEV_COMPUTE_CLUSTER0_GIC500SS 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0 672 to 731
J7200_DEV_COMPUTE_CLUSTER0_GIC500SS (Reserved by System Firmware) 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from NAVSS0_INTR_ROUTER_0 732 to 735
J7200_DEV_COMPUTE_CLUSTER0_GIC500SS 14 J7200_DEV_COMPUTE_CLUSTER0_GIC500SS inputs from WKUP_GPIOMUX_INTRTR0 960 to 975
J7200_DEV_MCU_CPSW0 18 J7200_DEV_MCU_CPSW0 inputs from TIMESYNC_INTRTR0 0
J7200_DEV_CPSW0 19 J7200_DEV_CPSW0 inputs from TIMESYNC_INTRTR0 0
J7200_DEV_CPSW0 19 J7200_DEV_CPSW0 inputs from TIMESYNC_INTRTR0 1
J7200_DEV_CPSW0 19 J7200_DEV_CPSW0 inputs from TIMESYNC_INTRTR0 2
J7200_DEV_CPSW0 19 J7200_DEV_CPSW0 inputs from TIMESYNC_INTRTR0 3
J7200_DEV_CPSW0 19 J7200_DEV_CPSW0 inputs from TIMESYNC_INTRTR0 4
J7200_DEV_CPSW0 19 J7200_DEV_CPSW0 inputs from TIMESYNC_INTRTR0 5
J7200_DEV_CPSW0 19 J7200_DEV_CPSW0 inputs from TIMESYNC_INTRTR0 6
J7200_DEV_ESM0 97 J7200_DEV_ESM0 inputs from GPIOMUX_INTRTR0 632 to 639
J7200_DEV_ESM0 97 J7200_DEV_ESM0 inputs from GPIOMUX_INTRTR0 640 to 647
J7200_DEV_ESM0 97 J7200_DEV_ESM0 inputs from GPIOMUX_INTRTR0 648 to 655
J7200_DEV_WKUP_ESM0 99 J7200_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0 120 to 127
J7200_DEV_WKUP_ESM0 99 J7200_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0 128 to 135
J7200_DEV_WKUP_ESM0 99 J7200_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0 136 to 143
J7200_DEV_NAVSS0 199 J7200_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 0
J7200_DEV_NAVSS0 199 J7200_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 1
J7200_DEV_NAVSS0 199 J7200_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 2
J7200_DEV_NAVSS0 199 J7200_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 3
J7200_DEV_NAVSS0 199 J7200_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 4
J7200_DEV_NAVSS0 199 J7200_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 5
J7200_DEV_NAVSS0 199 J7200_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 6
J7200_DEV_NAVSS0_UDMASS_INTA_0 209 J7200_DEV_NAVSS0_UDMASS_INTA_0 inputs from TIMESYNC_INTRTR0 52 to 59
J7200_DEV_NAVSS0_UDMASS_INTA_0 209 J7200_DEV_NAVSS0_UDMASS_INTA_0 inputs from CMPEVENT_INTRTR0 60 to 63
J7200_DEV_NAVSS0_UDMASS_INTA_0 209 J7200_DEV_NAVSS0_UDMASS_INTA_0 inputs from GPIOMUX_INTRTR0 68 to 83
J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 233 J7200_DEV_MCU_NAVSS0_UDMASS_INTA_0 inputs from WKUP_GPIOMUX_INTRTR0 4 to 11
J7200_DEV_R5FSS0_CORE0 245 J7200_DEV_R5FSS0_CORE0 inputs from GPIOMUX_INTRTR0 176 to 191
J7200_DEV_R5FSS0_CORE0 (Reserved by System Firmware) 245 J7200_DEV_R5FSS0_CORE0 inputs from NAVSS0_INTR_ROUTER_0 224 to 227
J7200_DEV_R5FSS0_CORE0 245 J7200_DEV_R5FSS0_CORE0 inputs from NAVSS0_INTR_ROUTER_0 228 to 255
J7200_DEV_R5FSS0_CORE0 245 J7200_DEV_R5FSS0_CORE0 inputs from CMPEVENT_INTRTR0 326 to 329
J7200_DEV_R5FSS0_CORE0 245 J7200_DEV_R5FSS0_CORE0 inputs from GPIOMUX_INTRTR0 396 to 411
J7200_DEV_R5FSS0_CORE0 245 J7200_DEV_R5FSS0_CORE0 inputs from WKUP_GPIOMUX_INTRTR0 488 to 503
J7200_DEV_R5FSS0_CORE1 246 J7200_DEV_R5FSS0_CORE1 inputs from GPIOMUX_INTRTR0 176 to 191
J7200_DEV_R5FSS0_CORE1 (Reserved by System Firmware) 246 J7200_DEV_R5FSS0_CORE1 inputs from NAVSS0_INTR_ROUTER_0 224 to 227
J7200_DEV_R5FSS0_CORE1 246 J7200_DEV_R5FSS0_CORE1 inputs from NAVSS0_INTR_ROUTER_0 228 to 255
J7200_DEV_R5FSS0_CORE1 246 J7200_DEV_R5FSS0_CORE1 inputs from CMPEVENT_INTRTR0 326 to 329
J7200_DEV_R5FSS0_CORE1 246 J7200_DEV_R5FSS0_CORE1 inputs from GPIOMUX_INTRTR0 396 to 411
J7200_DEV_R5FSS0_CORE1 246 J7200_DEV_R5FSS0_CORE1 inputs from WKUP_GPIOMUX_INTRTR0 488 to 503
J7200_DEV_MCU_R5FSS0_CORE0 (Reserved by System Firmware) 250 J7200_DEV_MCU_R5FSS0_CORE0 inputs from MCU_NAVSS0_INTR_0 64 to 74
J7200_DEV_MCU_R5FSS0_CORE0 250 J7200_DEV_MCU_R5FSS0_CORE0 inputs from MCU_NAVSS0_INTR_0 75 to 95
J7200_DEV_MCU_R5FSS0_CORE0 250 J7200_DEV_MCU_R5FSS0_CORE0 inputs from WKUP_GPIOMUX_INTRTR0 124 to 139
J7200_DEV_MCU_R5FSS0_CORE0 250 J7200_DEV_MCU_R5FSS0_CORE0 inputs from MAIN2MCU_LVL_INTRTR0 160 to 223
J7200_DEV_MCU_R5FSS0_CORE0 250 J7200_DEV_MCU_R5FSS0_CORE0 inputs from MAIN2MCU_PLS_INTRTR0 224 to 271
J7200_DEV_MCU_R5FSS0_CORE0 250 J7200_DEV_MCU_R5FSS0_CORE0 inputs from NAVSS0_INTR_ROUTER_0 376 to 383
J7200_DEV_MCU_R5FSS0_CORE1 (Reserved by System Firmware) 251 J7200_DEV_MCU_R5FSS0_CORE1 inputs from MCU_NAVSS0_INTR_0 64 to 67
J7200_DEV_MCU_R5FSS0_CORE1 251 J7200_DEV_MCU_R5FSS0_CORE1 inputs from MCU_NAVSS0_INTR_0 68 to 95
J7200_DEV_MCU_R5FSS0_CORE1 251 J7200_DEV_MCU_R5FSS0_CORE1 inputs from WKUP_GPIOMUX_INTRTR0 124 to 139
J7200_DEV_MCU_R5FSS0_CORE1 251 J7200_DEV_MCU_R5FSS0_CORE1 inputs from MAIN2MCU_LVL_INTRTR0 160 to 223
J7200_DEV_MCU_R5FSS0_CORE1 251 J7200_DEV_MCU_R5FSS0_CORE1 inputs from MAIN2MCU_PLS_INTRTR0 224 to 271
J7200_DEV_MCU_R5FSS0_CORE1 251 J7200_DEV_MCU_R5FSS0_CORE1 inputs from NAVSS0_INTR_ROUTER_0 376 to 383