50 #ifndef ti_osal_CacheP__include
51 #define ti_osal_CacheP__include
71 #define OSAL_CACHEP_COHERENT ((uint32_t) 0U)
73 #define OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U)
87 #define CacheP_Mar_DISABLE ((uint32_t) 0U)
89 #define CacheP_Mar_ENABLE ((uint32_t) 1U)
100 extern void CacheP_wb(
const void * addr, uint32_t size);
void CacheP_wb(const void *addr, uint32_t size)
Function to write back cache lines.
uint32_t CacheP_Mar
This enumerator defines the MAR register setting types.
Definition: CacheP.h:85
void CacheP_wbInv(const void *addr, uint32_t size)
Function to write back and invalidate cache lines.
void CacheP_setMar(void *baseAddr, uint32_t size, uint32_t value)
Set MAR attribute for a memory range.
uint32_t CacheP_getMar(uintptr_t baseAddr)
Get MAR attribute for a region of 16MB.
uint32_t Osal_CacheP_isCoherent
This enumerator defines the cache coherent types.
Definition: CacheP.h:69
void CacheP_Inv(const void *addr, uint32_t size)
Function to invalidate cache lines.