Cache Handling routines for the RTOS Porting Interface. More...
#include <stdint.h>#include <stdbool.h>#include <stddef.h>Go to the source code of this file.
Cache coherent type definitions | |
| #define | OSAL_CACHEP_COHERENT ((uint32_t) 0U) |
| #define | OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U) |
| typedef uint32_t | Osal_CacheP_isCoherent |
| This enumerator defines the cache coherent types. More... | |
Set Cache MAR register | |
| #define | CacheP_Mar_DISABLE ((uint32_t) 0U) |
| #define | CacheP_Mar_ENABLE ((uint32_t) 1U) |
| typedef uint32_t | CacheP_Mar |
| This enumerator defines the MAR register setting types. More... | |
| void | CacheP_wb (const void *addr, uint32_t size) |
| Function to write back cache lines. More... | |
| void | CacheP_Inv (const void *addr, uint32_t size) |
| Function to invalidate cache lines. More... | |
| void | CacheP_wbInv (const void *addr, uint32_t size) |
| Function to write back and invalidate cache lines. More... | |
| void | CacheP_setMar (void *baseAddr, uint32_t size, uint32_t value) |
| Set MAR attribute for a memory range. More... | |
| uint32_t | CacheP_getMar (uintptr_t baseAddr) |
| Get MAR attribute for a region of 16MB. More... | |
Cache Handling routines for the RTOS Porting Interface.
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