CacheP

Files
file	CacheP.h
	Cache Handling routines for the RTOS Porting Interface.

Cache coherent type definitions
typedef uint32_t	Osal_CacheP_isCoherent
	This enumerator defines the cache coherent types. More...
#define	OSAL_CACHEP_COHERENT   ((uint32_t) 0U)
#define	OSAL_CACHEP_NOT_COHERENT   ((uint32_t) 1U)

Set Cache MAR register
typedef uint32_t	CacheP_Mar
	This enumerator defines the MAR register setting types. More...
void	CacheP_wb (const void *addr, uint32_t size)
	Function to write back cache lines. More...
void	CacheP_Inv (const void *addr, uint32_t size)
	Function to invalidate cache lines. More...
void	CacheP_wbInv (const void *addr, uint32_t size)
	Function to write back and invalidate cache lines. More...
void	CacheP_setMar (void *baseAddr, uint32_t size, uint32_t value)
	Set MAR attribute for a memory range. More...
uint32_t	CacheP_getMar (uintptr_t baseAddr)
	Get MAR attribute for a region of 16MB. More...
#define	CacheP_Mar_DISABLE   ((uint32_t) 0U)
#define	CacheP_Mar_ENABLE   ((uint32_t) 1U)

Detailed Description

CacheP interface

Macro Definition Documentation

OSAL_CACHEP_COHERENT

#define OSAL_CACHEP_COHERENT   ((uint32_t) 0U)

Cache is coherent on this CPU

OSAL_CACHEP_NOT_COHERENT

#define OSAL_CACHEP_NOT_COHERENT   ((uint32_t) 1U)

Cache is not coherent on this CPU

CacheP_Mar_DISABLE

#define CacheP_Mar_DISABLE   ((uint32_t) 0U)

Cache MAR register disabled

CacheP_Mar_ENABLE

#define CacheP_Mar_ENABLE   ((uint32_t) 1U)

Cache MAR register is enabled

Typedef Documentation

Osal_CacheP_isCoherent

typedef uint32_t Osal_CacheP_isCoherent

This enumerator defines the cache coherent types.

CacheP_Mar

typedef uint32_t CacheP_Mar

This enumerator defines the MAR register setting types.

Function Documentation

CacheP_wb()

void CacheP_wb	(	const void *	addr,
		uint32_t	size
	)

Function to write back cache lines.

Parameters

addr	Start address of the cache line/s
size	size (in bytes) of the memory to be written back

CacheP_Inv()

void CacheP_Inv	(	const void *	addr,
		uint32_t	size
	)

Function to invalidate cache lines.

Parameters

addr	Start address of the cache line/s
size	size (in bytes) of the memory to invalidate

CacheP_wbInv()

void CacheP_wbInv	(	const void *	addr,
		uint32_t	size
	)

Function to write back and invalidate cache lines.

Parameters

addr	Start address of the cache line/s
size	size (in bytes) of the memory to be written back and invalidate

CacheP_setMar()

void CacheP_setMar	(	void *	baseAddr,
		uint32_t	size,
		uint32_t	value
	)

Set MAR attribute for a memory range.

[C66x Only] The API will set the MAR attribute for the range, start_addr = floor(baseAddr, 16MB) .. end_addr = ceil(baseAddr+size, 16MB)

Parameters

baseAddr	Region start address. Recommended to be 16MB aligned
size	Region size in bytes. Recommended to be multiple of 16MB aligned
value	value for setting MAR register CacheP_Mar

CacheP_getMar()

uint32_t CacheP_getMar

(

uintptr_t

baseAddr

)

Get MAR attribute for a region of 16MB.

[C66x Only] The API will return the MAR attribute of the region with start addr as start_addr = floor(baseAddr, 16MB)

Parameters

baseAddr

region start address, recommended to be 16MB aligned

Returns

MAR attribute for this 16MB region