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| file | ipc_soc.h |
| | IPC Low Level Driver J784S4/J742S2 SOC specific file.
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| int32_t | Ipc_sciclientIrqRelease (uint16_t remoteId, uint32_t clusterId, uint32_t userId, uint32_t intNumber) |
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| int32_t | Ipc_sciclientIrqSet (uint16_t remoteId, uint32_t clusterId, uint32_t userId, uint32_t intNumber) |
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| int32_t | Ipc_getIntNumRange (uint32_t coreIndex, uint16_t *rangeStartP, uint16_t *rangeNumP) |
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This is IPC documentation specific to J784S4/J742S2 SoC
◆ IPC_VRING_BUFFER_SIZE
| #define IPC_VRING_BUFFER_SIZE (0x3000000U) |
VRing Buffer Size required for all core combinations.
◆ IPC_MPU1_0
Core definitions.
ARM A72 - VM0
◆ IPC_MCU1_0
◆ IPC_MCU1_1
◆ IPC_MCU2_0
◆ IPC_MCU2_1
◆ IPC_MCU3_0
◆ IPC_MCU3_1
◆ IPC_MCU4_0
◆ IPC_MCU4_1
◆ IPC_C7X_1
◆ IPC_C7X_2
◆ IPC_C7X_3
◆ IPC_MAILBOX_CLUSTER_CNT
| #define IPC_MAILBOX_CLUSTER_CNT (18U) |
◆ IPC_MAILBOX_USER_CNT
| #define IPC_MAILBOX_USER_CNT (4U) |
◆ MAIN_NAVSS_MAILBOX_INPUTINTR_MAX
| #define MAIN_NAVSS_MAILBOX_INPUTINTR_MAX (440U) |
◆ MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX
| #define MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX (512U) |
◆ IPC_MCU_NAVSS0_INTR0_CFG_BASE
| #define IPC_MCU_NAVSS0_INTR0_CFG_BASE (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE) |
◆ C7X_CLEC_BASE_ADDR
| #define C7X_CLEC_BASE_ADDR (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE) |
◆ C7X_CLEC_OFFSET
| #define C7X_CLEC_OFFSET (1024U - 32U) |
◆ IPC_C7X_MBINTR_OFFSET
| #define IPC_C7X_MBINTR_OFFSET (59U) |
◆ Ipc_sciclientIrqRelease()
| int32_t Ipc_sciclientIrqRelease |
( |
uint16_t |
remoteId, |
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uint32_t |
clusterId, |
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uint32_t |
userId, |
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uint32_t |
intNumber |
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) |
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◆ Ipc_sciclientIrqSet()
| int32_t Ipc_sciclientIrqSet |
( |
uint16_t |
remoteId, |
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uint32_t |
clusterId, |
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uint32_t |
userId, |
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uint32_t |
intNumber |
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) |
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◆ Ipc_getIntNumRange()
| int32_t Ipc_getIntNumRange |
( |
uint32_t |
coreIndex, |
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uint16_t * |
rangeStartP, |
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uint16_t * |
rangeNumP |
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) |
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