3.2.2.13. SERDES

3.2.2.13.1. Introduction

SERDES converts device (SoC) parallel data into serialized data that can be output over a high-speed electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel data that can be processed by the device.

SERDES is used for transmitting/receiving data for PCIe, USB3, CPSW (QSGMII, SGMII, USXGMII, XFI), eDP in K3 SoC.

Note

The following documentation describes the different PHY types (data rates) supported by the SERDES. While the SERDES might support a given protocol, it does not imply that the peripheral is capable of utilizing it. Please refer to the Technical Reference Manual for verifying hardware support for the peripheral. Refer to the peripheral driver documentation for verifying software support for the peripheral.

3.2.2.13.3. SERDES Configurations

This section lists the set of PHY types (data rates) that the SERDES can be configured in, from the perspective of the SERDES driver and SERDES hardware support. To enable the desired configuration, the SoC device-tree has to be modified based on the instructions mentioned in the SERDES Muxing section.

3.2.2.13.5. SERDES Muxing

SERDES Muxing refers to the process of selecting the mapping between the Peripheral Lanes and the SERDES Lanes. A valid mapping refers to the process of selecting a valid combination of Peripheral Lane and SERDES Lane based on the physical connections available to choose from. Listed below is the valid set of combinations for the SERDES instances.

The Muxing configuration for each of the SERDES lanes can be described using device tree. The device tree node labelled serdes_ln_ctrl corresponds to the mux used to configure each of the SERDES lanes. The property “idle-states” inside the serdes_ln_ctrl mux is used to specify the mapping between the SERDES lane and the IP lane.

A valid mapping can be determined by referring to the SERDES muxing section above. To select a mapping, the following format has to be used:

<SoC_SERDESw_LANEx_IPa_LANEb>

where:

  • SoC is the name of the SoC,

  • ‘w’ specifies the SERDES instance: SERDES0 for example,

  • ‘x’ specifies the SERDES Lane: LANE0 for example,

  • IP specifies the peripheral IP: PCIE for example,

  • ‘a’ specifies the instance of that peripheral IP: PCIE0 for example,

  • ‘b’ specifies the peripheral IP’s Lane: LANE0 for example.

The mapping is interpret as follows:

For the SoC named: SoC, SERDESw LANEx should be mapped to IPa LANEb.

For unused Serdes lanes, indicate them using:

<SoC_SERDESw_LANEx_IPa_UNUSED>

Serdes Muxing Example

Consider an SoC named SoCX with one 1L SERDES, one 2L SERDES and one 4L SERDES, with the instances being SERDES0, SERDES1 and SERDES2. Additionally, let the SoC have PCIe instance PCIE1, EDP instance EDP0 and a CPSW instance using QSGMII.

Then, to configure:

  • SERDES0 Lane0 for PCIE1 Lane0

  • SERDES1 Lane0 for EDP0 Lane2

  • SERDES1 Lane1 for EDP0 Lane3

  • SERDES2 Lane0 for QSGMII Lane3

  • SERDES2 Lane1 for QSGMII Lane4

  • SERDES2 Lane2 for QSGMII Lane1

  • SERDES2 Lane3 for QSGMII Lane2

the device tree serdes_ln_ctrl node has to be defined as follows:

&serdes_ln_ctrl {
        idle-states = <SoCX_SERDES0_LANE0_PCIE1_LANE0>, <SoCX_SERDES1_LANE0_EDP0_LANE2>,
                      <SoCX_SERDES1_LANE1_EDP0_LANE3>, <SoCX_SERDES2_LANE0_QSGMII_LANE3>,
                      <SoCX_SERDES2_LANE1_QSGMII_LANE4>, <SoCX_SERDES2_LANE2_QSGMII_LANE1>
                      <SoCX_SERDES2_LANE3_QSGMII_LANE2>;
};

Default Device Tree Muxing

The exact mux values to be programmed can be obtained from the dt-bindings include directory of the kernel repository:

include/dt-bindings/mux/ti-serdes.h

The serdes_ln_ctrl based configuration uses the mux framework of Linux. More information can be found in the Documentation of the kernel repository:

Documentation/devicetree/bindings/mux/mux-controller.yaml

3.2.2.13.6. SERDES Clocking Options

Each SERDES has PLLs inside it which have to be programmed to operate at different frequencies, based on the data rate required by the Peripheral IP connected to the SERDES.

For example, based on the specification, the data rates for some of the Peripheral IPs are:

  1. 8Gbps for PCIe GEN3

  2. 5Gbps for PCIe GEN2

  3. 2.5Gbps for PCIe GEN1

  4. 5Gbps for USB3 SS

  5. 5Gbps for QSGMII [CPSW Ethernet]

The input reference clocks connected to each SERDES are used to program the PLLs inside the SERDES. The details regarding the PLL frequencies and programming is abstracted from the user. The user only has to provide the reference clocks to be used by the SERDES for programming the PLLs, based on the data rates required by the Peripheral IPs being used.

3.2.2.13.6.3. Selecting Between Internal and External Reference Clock

The WIZ wrapper allows selecting between the internal and external clock to be used as the input to PLL0 and PLL1 of the SERDES. Additionally, the reference clock to be used as input for the digital logic of the SERDES PHY and PMA can also be selected.