a: TI Targets

Detailed Description

TI Targets (for vxSetNodeTarget)

The following list of defines are the list of targets supported for the call to vxSetNodeTarget

Defines
#define	TIVX_TARGET_MPU_0   "MPU-0"
	Target name for MPU_0.
#define	TIVX_TARGET_MPU_1   "MPU-1"
	Target name for MPU_1.
#define	TIVX_TARGET_MPU_2   "MPU-2"
	Target name for MPU_2.
#define	TIVX_TARGET_MPU_3   "MPU-3"
	Target name for MPU_3.
#define	TIVX_TARGET_DSP_C7_1   "DSP_C7-1"
	Target name for DSP_C7_1 This target task is first in priority. Each of the C7X targets are assigned a different task priority. Subsequent C7X targets are assigned lower priority than the preceding target (i.e., TIVX_TARGET_DSP_C7_1_PRI_2 is lower priority than TIVX_TARGET_DSP_C7_1_PRI_1). Therefore, the TIVX_TARGET_DSP_C7_1_PRI_2 target will be preempted by TIVX_TARGET_DSP_C7_1_PRI_1 once the higher priority target is unblocked to execute.
#define	TIVX_TARGET_DSP_C7_1_PRI_1   TIVX_TARGET_DSP_C7_1
	Target name for DSP_C7_1 This target task is first in priority. This aliases to the same task as TIVX_TARGET_DSP_C7_1.
#define	TIVX_TARGET_DSP_C7_1_PRI_2   "DSP_C7-1_PRI_2"
	Target name for DSP_C7-1_PRI_2 This target task is second in priority.
#define	TIVX_TARGET_DSP_C7_1_PRI_3   "DSP_C7-1_PRI_3"
	Target name for DSP_C7-1_PRI_3 This target task is third in priority.
#define	TIVX_TARGET_DSP_C7_1_PRI_4   "DSP_C7-1_PRI_4"
	Target name for DSP_C7-1_PRI_4 This target task is fourth in priority.
#define	TIVX_TARGET_DSP_C7_1_PRI_5   "DSP_C7-1_PRI_5"
	Target name for DSP_C7-1_PRI_5 This target task is fifth in priority.
#define	TIVX_TARGET_DSP_C7_1_PRI_6   "DSP_C7-1_PRI_6"
	Target name for DSP_C7-1_PRI_6 This target task is sixth in priority.
#define	TIVX_TARGET_DSP_C7_1_PRI_7   "DSP_C7-1_PRI_7"
	Target name for DSP_C7-1_PRI_7 This target task is seventh in priority.
#define	TIVX_TARGET_DSP_C7_1_PRI_8   "DSP_C7-1_PRI_8"
	Target name for DSP_C7-1_PRI_8 This target task is eighth in priority.
#define	TIVX_TARGET_DSP_C7_2   "DSP_C7-2"
	Target name for DSP_C7_2 This target task is first in priority. Each of the C7X targets are assigned a different task priority. Subsequent C7X targets are assigned lower priority than the preceding target (i.e., TIVX_TARGET_DSP_C7_2_PRI_2 is lower priority than TIVX_TARGET_DSP_C7_2_PRI_1). Therefore, the TIVX_TARGET_DSP_C7_2_PRI_2 target will be preempted by TIVX_TARGET_DSP_C7_2_PRI_1 once the higher priority target is unblocked to execute.
#define	TIVX_TARGET_DSP_C7_2_PRI_1   TIVX_TARGET_DSP_C7_2
	Target name for DSP_C7_2 This target task is first in priority. This aliases to the same task as TIVX_TARGET_DSP_C7_2.
#define	TIVX_TARGET_DSP_C7_2_PRI_2   "DSP_C7-2_PRI_2"
	Target name for DSP_C7-2_PRI_2 This target task is second in priority.
#define	TIVX_TARGET_DSP_C7_2_PRI_3   "DSP_C7-2_PRI_3"
	Target name for DSP_C7-2_PRI_3 This target task is third in priority.
#define	TIVX_TARGET_DSP_C7_2_PRI_4   "DSP_C7-2_PRI_4"
	Target name for DSP_C7-2_PRI_4 This target task is fourth in priority.
#define	TIVX_TARGET_DSP_C7_2_PRI_5   "DSP_C7-2_PRI_5"
	Target name for DSP_C7-2_PRI_5 This target task is fifth in priority.
#define	TIVX_TARGET_DSP_C7_2_PRI_6   "DSP_C7-2_PRI_6"
	Target name for DSP_C7-2_PRI_6 This target task is sixth in priority.
#define	TIVX_TARGET_DSP_C7_2_PRI_7   "DSP_C7-2_PRI_7"
	Target name for DSP_C7-2_PRI_7 This target task is seventh in priority.
#define	TIVX_TARGET_DSP_C7_2_PRI_8   "DSP_C7-2_PRI_8"
	Target name for DSP_C7-2_PRI_8 This target task is eighth in priority.
#define	TIVX_TARGET_DSP_C7_3   "DSP_C7-3"
	Target name for DSP_C7_3 This target task is first in priority. Each of the C7X targets are assigned a different task priority. Subsequent C7X targets are assigned lower priority than the preceding target (i.e., TIVX_TARGET_DSP_C7_3_PRI_2 is lower priority than TIVX_TARGET_DSP_C7_3_PRI_1). Therefore, the TIVX_TARGET_DSP_C7_3_PRI_2 target will be preempted by TIVX_TARGET_DSP_C7_3_PRI_1 once the higher priority target is unblocked to execute.
#define	TIVX_TARGET_DSP_C7_3_PRI_1   TIVX_TARGET_DSP_C7_3
	Target name for DSP_C7_3 This target task is first in priority. This aliases to the same task as TIVX_TARGET_DSP_C7_3.
#define	TIVX_TARGET_DSP_C7_3_PRI_2   "DSP_C7-3_PRI_2"
	Target name for DSP_C7-3_PRI_2 This target task is second in priority.
#define	TIVX_TARGET_DSP_C7_3_PRI_3   "DSP_C7-3_PRI_3"
	Target name for DSP_C7-3_PRI_3 This target task is third in priority.
#define	TIVX_TARGET_DSP_C7_3_PRI_4   "DSP_C7-3_PRI_4"
	Target name for DSP_C7-3_PRI_4 This target task is fourth in priority.
#define	TIVX_TARGET_DSP_C7_3_PRI_5   "DSP_C7-3_PRI_5"
	Target name for DSP_C7-3_PRI_5 This target task is fifth in priority.
#define	TIVX_TARGET_DSP_C7_3_PRI_6   "DSP_C7-3_PRI_6"
	Target name for DSP_C7-3_PRI_6 This target task is sixth in priority.
#define	TIVX_TARGET_DSP_C7_3_PRI_7   "DSP_C7-3_PRI_7"
	Target name for DSP_C7-3_PRI_7 This target task is seventh in priority.
#define	TIVX_TARGET_DSP_C7_3_PRI_8   "DSP_C7-3_PRI_8"
	Target name for DSP_C7-3_PRI_8 This target task is eighth in priority.
#define	TIVX_TARGET_DSP1   TIVX_TARGET_DSP_C7_2
	Name for DSP target class, instance 1. More...
#define	TIVX_TARGET_MCU2_0   "MCU2-0"
	Name for MCU2 target class, core 0. More...
#define	TIVX_TARGET_MCU2_1   "MCU2-1"
	Name for MCU2 target class, core 1. More...
#define	TIVX_TARGET_MCU3_0   "MCU3-0"
	Name for MCU3_0 target class, core 0. More...
#define	TIVX_TARGET_MCU3_1   "MCU3-1"
	Name for MCU3_1 target class, core 1. More...
#define	TIVX_TARGET_MCU4_0   "MCU4-0"
	Name for MCU4_0 target class, core 0. More...
#define	TIVX_TARGET_MCU4_1   "MCU4-1"
	Name for MCU4_1 target class, core 1. More...
#define	TIVX_TARGET_CAPTURE1   "CAPTURE1"
	Target name for Capture.
#define	TIVX_TARGET_CAPTURE2   "CAPTURE2"
	Target name for Capture.
#define	TIVX_TARGET_CAPTURE3   "CAPTURE3"
	Target name for Capture Node Instance 3.
#define	TIVX_TARGET_CAPTURE4   "CAPTURE4"
	Target name for Capture Node Instance 4.
#define	TIVX_TARGET_CAPTURE5   "CAPTURE5"
	Target name for Capture Node Instance 5.
#define	TIVX_TARGET_CAPTURE6   "CAPTURE6"
	Target name for Capture Node Instance 6.
#define	TIVX_TARGET_CAPTURE7   "CAPTURE7"
	Target name for Capture Node Instance 7.
#define	TIVX_TARGET_CAPTURE8   "CAPTURE8"
	Target name for Capture Node Instance 8.
#define	TIVX_TARGET_CAPTURE9   "CAPTURE9"
	Target name for Capture Node Instance 9.
#define	TIVX_TARGET_CAPTURE10   "CAPTURE10"
	Target name for Capture Node Instance 10.
#define	TIVX_TARGET_CAPTURE11   "CAPTURE11"
	Target name for Capture Node Instance 11.
#define	TIVX_TARGET_CAPTURE12   "CAPTURE12"
	Target name for Capture Node Instance 12.
#define	TIVX_TARGET_CSITX   "CSITX"
	Target name for CSITX.
#define	TIVX_TARGET_CSITX2   "CSITX2"
	Target name for CSITX2.
#define	TIVX_TARGET_DISPLAY_M2M1   "DSS_M2M1"
	Target name for Display M2M Node Instance 1.
#define	TIVX_TARGET_DISPLAY_M2M2   "DSS_M2M2"
	Target name for Display M2M Node Instance 2.
#define	TIVX_TARGET_DISPLAY_M2M3   "DSS_M2M3"
	Target name for Display M2M Node Instance 3.
#define	TIVX_TARGET_DISPLAY_M2M4   "DSS_M2M4"
	Target name for Display M2M Node Instance 4.
#define	TIVX_TARGET_DISPLAY1   "DISPLAY1"
	Target name for Display.
#define	TIVX_TARGET_DISPLAY2   "DISPLAY2"
	Target name for Display.
#define	TIVX_TARGET_DMPAC_DOF   "DMPAC_DOF"
	Target name for DMPAC DOF.
#define	TIVX_TARGET_DMPAC_SDE   "DMPAC_SDE"
	Target name for DMPAC SDE.
#define	TIVX_TARGET_VPAC1_LDC1   "VPAC_LDC1"
	Target name for VPAC1 LDC1.
#define	TIVX_TARGET_VPAC2_LDC1   "VPAC2_LDC1"
	Target name for VPAC2 LDC1.
#define	TIVX_TARGET_VPAC1_MSC1   "VPAC_MSC1"
	Target name for VPAC1 MSC1.
#define	TIVX_TARGET_VPAC1_MSC2   "VPAC_MSC2"
	Target name for VPAC1 MSC2.
#define	TIVX_TARGET_VPAC2_MSC1   "VPAC2_MSC1"
	Target name for VPAC2 MSC1.
#define	TIVX_TARGET_VPAC2_MSC2   "VPAC2_MSC2"
	Target name for VPAC2 MSC2.
#define	TIVX_TARGET_VPAC1_NF   "VPAC_NF"
	Target name for VPAC1 NF.
#define	TIVX_TARGET_VPAC2_NF   "VPAC2_NF"
	Target name for VPAC2 NF.
#define	TIVX_TARGET_VPAC1_VISS1   "VPAC_VISS1"
	Target name for VPAC1 VISS1.
#define	TIVX_TARGET_VPAC2_VISS1   "VPAC2_VISS1"
	Target name for VPAC2 VISS1.
#define	TIVX_TARGET_VPAC1_FC   "VPAC1_FC"
	Target name for VPAC1 FC.
#define	TIVX_TARGET_VPAC2_FC   "VPAC2_FC"
	Target name for VPAC2 FC.

Macro Definition Documentation

TIVX_TARGET_DSP1

#define TIVX_TARGET_DSP1   TIVX_TARGET_DSP_C7_2

Name for DSP target class, instance 1.

Assigned to DSP_C7_2 core

Definition at line 298 of file tivx_soc_j742s2.h.

TIVX_TARGET_MCU2_0

#define TIVX_TARGET_MCU2_0   "MCU2-0"

Name for MCU2 target class, core 0.

Assigned to MCU2_0 core

Definition at line 306 of file tivx_soc_j742s2.h.

TIVX_TARGET_MCU2_1

#define TIVX_TARGET_MCU2_1   "MCU2-1"

Name for MCU2 target class, core 1.

Assigned to MCU2_1 core

Definition at line 314 of file tivx_soc_j742s2.h.

TIVX_TARGET_MCU3_0

#define TIVX_TARGET_MCU3_0   "MCU3-0"

Name for MCU3_0 target class, core 0.

Assigned to MCU3_0 core

Definition at line 322 of file tivx_soc_j742s2.h.

TIVX_TARGET_MCU3_1

#define TIVX_TARGET_MCU3_1   "MCU3-1"

Name for MCU3_1 target class, core 1.

Assigned to MCU3_1 core

Definition at line 330 of file tivx_soc_j742s2.h.

TIVX_TARGET_MCU4_0

#define TIVX_TARGET_MCU4_0   "MCU4-0"

Name for MCU4_0 target class, core 0.

Assigned to MCU4_0 core

Definition at line 338 of file tivx_soc_j742s2.h.

TIVX_TARGET_MCU4_1

#define TIVX_TARGET_MCU4_1   "MCU4-1"

Name for MCU4_1 target class, core 1.

Assigned to MCU4_1 core

Definition at line 346 of file tivx_soc_j742s2.h.