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TI J721E Imaging User Guide
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TI J721E Imaging User Guide
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Enumerations for VPAC VISS error events.
| #define TIVX_VPAC_VISS_RAWFE_CFG_ERR_INTR (0x1U) |
Config read or write memory acccess occurred during functional operation and likely corrupted functional opertion. VISS merges all config error sources from RawFE and refer to RawFE spec for the entire error source list.
| #define TIVX_VPAC_VISS_RAWFE_AEW_PULSE_INTR (0x2U) |
H3A AEW interrupt
| #define TIVX_VPAC_VISS_RAWFE_AF_PULSE_INTR (0x4U) |
H3A AF interrupt
| #define TIVX_VPAC_VISS_RAWFE_H3A_PULSE_INTR (0x8U) |
H3A interrupt
| #define TIVX_VPAC_VISS_RAWFE_H3A_BUF_OVRFLOW_PULSE_INTR (0x10U) |
H3A output buffer overflow
| #define TIVX_VPAC_VISS_NSF4V_LINEMEM_CFG_ERR_INTR (0x20U) |
VBUSP diagnostic read access of, while NSF data using RAM for functional purpose
| #define TIVX_VPAC_VISS_NSF4V_HBLANK_ERR_INTR (0x40U) |
Horzontal Blanking too short between lines
| #define TIVX_VPAC_VISS_NSF4V_VBLANK_ERR_INTR (0x80U) |
Vertical Blanking too short between frames
| #define TIVX_VPAC_VISS_GLBCE_CFG_ERR_INTR (0x100U) |
Either non-shadowed registers written or statastic memories are accessed during active window
| #define TIVX_VPAC_VISS_GLBCE_FILT_START_INTR (0x200U) |
GLBCE started filtering. This interrupt is issued at the rising edge of filtering signal
| #define TIVX_VPAC_VISS_GLBCE_FILT_DONE_INTR (0x400U) |
GLBCE ended filtering. This interrupt is issued at the falling edge of filtering signal
| #define TIVX_VPAC_VISS_GLBCE_HSYNC_ERR_INTR (0x800U) |
Generated when delayed HS/HE signals does not match with derived signals from GLBCE core.
| #define TIVX_VPAC_VISS_GLBCE_VSYNC_ERR_INTR (0x1000U) |
Generated when delayed VS/VE signals does not match with derived signals from GLBCE core
| #define TIVX_VPAC_VISS_GLBCE_VP_ERR_INTR (0x2000U) |
This interrupt is issued, if there is a data input while filtering is high
| #define TIVX_VPAC_VISS_FCFA_CFG_ERR_INTR (0x4000U) |
Either non-shadowed registers written or line memories are accessed during active window
| #define TIVX_VPAC_VISS_FCC_CFG_ERR_INTR (0x8000U) |
Configuration access to registers/memories has corrupted functional operation. Configuration read or write memory acccess occurred during functional operation. Merged independent error sources at VISS. Refer to Section VISS Flexible Color Processing (FCP) for all sources.
| #define TIVX_VPAC_VISS_FCC_OUTIF_OVF_ERR_INTR (0x10000U) |
FIFO overflow on FIFO for Y12 LSE I/F. Merged all FCC output overflow error sources at VISS. Refer to Section VISS Flexible Color Processing (FCP) for all sources.
| #define TIVX_VPAC_VISS_FCC_HIST_READ_ERR_INTR (0x20000U) |
Host was not able to read the entire histogram mem between VS-VE window (triggered when the first access to histogram has been performed but the last has not been performed).
| #define TIVX_VPAC_VISS_EE_CFG_ERR (0x40000U) |
Configuration happened to EE regions causing corruption during frame processing
| #define TIVX_VPAC_VISS_EE_SYNCOVF_ERR (0x80000U) |
EE horizontal synchronization FIFO overflow interrupt
| #define TIVX_VPAC_VISS_LSE_FR_DONE_EVT_INTR (0x100000U) |
LSE frame done interrupt
| #define TIVX_VPAC_VISS_LSE_SL2_RD_ERR_INTR (0x200000U) |
Set whenever there is an error response on VBUSM read command for any input channel.
| #define TIVX_VPAC_VISS_LSE_SL2_WR_ERR_INTR (0x400000U) |
Set whenever there is an error response on VBUSM write command for any output channel.
| #define TIVX_VPAC_VISS_LSE_CAL_VP_ERR_INTR (0x800000U) |
Set whenever one of the following input frame errors is detected at VPORT_INPUT brief Output Frame Start (from VISS top level)
| #define TIVX_VPAC_VISS_LSE_OUT_FR_START_EVT_INTR (0x1000000U) |
| #define TIVX_VPAC_VISS_WDTIMER_ERR (0x40000000U) |
Watchdog Timeout Error for VISS
1.8.14