I2SCC32XX.h
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39 #ifndef ti_drivers_i2s_I2SCC32XX__include
40 #define ti_drivers_i2s_I2SCC32XX__include
41 
42 #include <ti/drivers/I2S.h>
44 #include <ti/drivers/dpl/SemaphoreP.h>
45 #include <ti/drivers/dpl/HwiP.h>
46 #include <ti/drivers/utils/List.h>
47 #include <ti/drivers/Power.h>
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
53 /*
54  * Macros defining possible I2S signal pin mux options
55  *
56  * The bits in the pin mode macros are as follows:
57  * The lower 8 bits of the macro refer to the pin, offset by 1, to match
58  * driverlib pin defines. For example, I2SCC32XX_PIN_02_WS & 0xff = 1,
59  * which equals PIN_02 in driverlib pin.h. By matching the PIN_xx defines in
60  * driverlib pin.h, we can pass the pin directly to the driverlib functions.
61  * The upper 8 bits of the macro correspond to the pin mux confg mode
62  * value for the pin to operate in the I2S mode. For example, pin 2 is
63  * configured with mode 13 to operate as WS.
64  *
65  * The macro I2SCC32XX_PIN_UNUSED allows the user to not activate one
66  * of the signal.
67  */
69 #define I2SCC32XX_PIN_02_McAFSX 0x0d01
70 #define I2SCC32XX_PIN_03_McACLK 0x0302
71 #define I2SCC32XX_PIN_15_McAFSX 0x070e
72 #define I2SCC32XX_PIN_17_McAFSX 0x0610
73 #define I2SCC32XX_PIN_21_McAFSX 0x0214
74 #define I2SCC32XX_PIN_45_McAXR0 0x062c
75 #define I2SCC32XX_PIN_45_McAFSX 0x0c2c
76 #define I2SCC32XX_PIN_50_McAXR0 0x0431
77 #define I2SCC32XX_PIN_50_McAXR1 0x0631
78 #define I2SCC32XX_PIN_52_McACLK 0x0233
79 #define I2SCC32XX_PIN_52_McAXR0 0x0433
80 #define I2SCC32XX_PIN_53_McACLK 0x0234
81 #define I2SCC32XX_PIN_53_McAFSX 0x0334
82 #define I2SCC32XX_PIN_60_McAXR1 0x063b
83 #define I2SCC32XX_PIN_62_McACLKX 0x0d3d
84 #define I2SCC32XX_PIN_63_McAFSX 0x073e
85 #define I2SCC32XX_PIN_64_McAXR0 0x073f
86 #define I2SCC32XX_PIN_UNUSED 0xffff
88 #define I2SCC32XX_PIN_50_SD1 I2SCC32XX_PIN_50_McAXR1
89 #define I2SCC32XX_PIN_60_SD1 I2SCC32XX_PIN_60_McAXR1
90 #define I2SCC32XX_PIN_52_SD0 I2SCC32XX_PIN_52_McAXR0
91 #define I2SCC32XX_PIN_64_SD0 I2SCC32XX_PIN_64_McAXR0
92 #define I2SCC32XX_PIN_45_SD0 I2SCC32XX_PIN_45_McAXR0
93 #define I2SCC32XX_PIN_50_SD0 I2SCC32XX_PIN_50_McAXR0
94 #define I2SCC32XX_PIN_03_SCK I2SCC32XX_PIN_03_McACLK
95 #define I2SCC32XX_PIN_52_SCK I2SCC32XX_PIN_52_McACLK
96 #define I2SCC32XX_PIN_53_SCK I2SCC32XX_PIN_53_McACLK
97 #define I2SCC32XX_PIN_62_SCKX I2SCC32XX_PIN_62_McACLKX
98 #define I2SCC32XX_PIN_02_WS I2SCC32XX_PIN_02_McAFSX
99 #define I2SCC32XX_PIN_15_WS I2SCC32XX_PIN_15_McAFSX
100 #define I2SCC32XX_PIN_17_WS I2SCC32XX_PIN_17_McAFSX
101 #define I2SCC32XX_PIN_21_WS I2SCC32XX_PIN_21_McAFSX
102 #define I2SCC32XX_PIN_45_WS I2SCC32XX_PIN_45_McAFSX
103 #define I2SCC32XX_PIN_63_WS I2SCC32XX_PIN_63_McAFSX
104 #define I2SCC32XX_PIN_53_WS I2SCC32XX_PIN_53_McAFSX
137 typedef struct
138 {
139  uint32_t pinSD1;
142  uint32_t pinSD0;
145  uint32_t pinSCK;
148  uint32_t pinSCKX;
150  uint32_t pinWS;
154  uint32_t rxChannelIndex;
157  uint32_t txChannelIndex;
160  uint32_t intPriority;
162 
170 typedef struct
171 {
172  I2S_DataInterfaceUse interfaceConfig;
173  I2S_ChannelConfig channelsUsed;
174  uint8_t numberOfChannelsUsed;
175  uint8_t dataLine;
176 } I2SCC32XX_DataInterface;
186 typedef struct
187 {
188  uint16_t delay;
190  I2S_Transaction *activeTransfer;
191  I2S_Callback callback;
192  uint32_t udmaConfig;
194  I2S_StopInterface stopInterface;
195 } I2SCC32XX_Interface;
205 typedef void (*I2SCC32XX_FifoUpdate)(uintptr_t arg);
206 
212 typedef struct
213 {
214 
215  bool isOpen;
216  bool invertWS;
219  bool isMSBFirst;
222  bool isDMAUnused;
225  volatile bool isLastReadTransfer;
228  volatile bool isLastWriteTransfer;
231  uint8_t dataShift;
237  uint8_t memorySlotLength;
242  uint8_t sampleRotation;
244  uint8_t noOfInputs;
245  uint8_t noOfOutputs;
246  uint8_t udmaArbLength;
249  uint8_t dataLength;
250  I2S_Role moduleRole;
253  I2S_SamplingEdge samplingEdge;
256  uint32_t samplingFrequency;
257  uint32_t sampleMask;
259  uint32_t activatedFlag;
261  I2SCC32XX_DataInterface dataInterfaceSD0;
262  I2SCC32XX_DataInterface dataInterfaceSD1;
263  I2SCC32XX_Interface read;
264  I2SCC32XX_Interface write;
265  I2S_Callback errorCallback;
266  I2SCC32XX_FifoUpdate updateDataReadFxn;
267  I2SCC32XX_FifoUpdate updateDataWriteFxn;
268  HwiP_Handle hwi;
269  UDMACC32XX_Handle dmaHandle;
270  Power_NotifyObj notifyObj;
271 } I2SCC32XX_Object;
274 #ifdef __cplusplus
275 }
276 #endif
277 
278 #endif /* ti_drivers_i2s_I2SCC32XX__include */
uint32_t pinSCKX
Definition: I2SCC32XX.h:148
void(* I2S_Callback)(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr)
The definition of a user-callback function used by the I2S driver.
Definition: I2S.h:712
Power Manager.
uint32_t rxChannelIndex
Definition: I2SCC32XX.h:154
I2S_DataInterfaceUse
I2S data interface configuration.
Definition: I2S.h:794
uDMA driver implementation for CC32XX.
uint32_t pinSD0
Definition: I2SCC32XX.h:142
uint32_t pinWS
Definition: I2SCC32XX.h:150
I2S_Role
I2S controller / target selection.
Definition: I2S.h:755
UDMACC32XX Global configuration.
Definition: UDMACC32XX.h:126
I2S Hardware attributes.
Definition: I2SCC32XX.h:137
uint32_t pinSD1
Definition: I2SCC32XX.h:139
void(* I2SCC32XX_FifoUpdate)(uintptr_t arg)
The definition of a function used by the I2S driver to refresh the FIFO.
Definition: I2SCC32XX.h:205
Inter-Integrated Circuit Sound (I2S) Bus Driver.
I2S_ChannelConfig
Channels used selection.
Definition: I2S.h:811
Power notify object structure.
Definition: Power.h:442
I2S_SamplingEdge
I2S sampling setting.
Definition: I2S.h:768
uint32_t txChannelIndex
Definition: I2SCC32XX.h:157
void(* I2S_StopInterface)(I2S_Handle handle)
The definition of a function used to stop an I2S interface.
Definition: I2S.h:730
uint32_t intPriority
Definition: I2SCC32XX.h:160
I2S transaction descriptor.
Definition: I2S.h:681
uint32_t pinSCK
Definition: I2SCC32XX.h:145
Linked List interface for use in drivers.
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