UDMACC32XX_HWAttrs Struct Reference

UDMACC32XX Hardware attributes. More...

#include <UDMACC32XX.h>

Data Fields
void *	controlBaseAddr
UDMACC32XX_ErrorFxn	dmaErrorFxn
uint8_t	intNum
uint8_t	intPriority

Detailed Description

UDMACC32XX Hardware attributes.

This structure contains the base address of the uDMA control table, and uDMA error interrupt attributes.

The control table is used by the uDMA controller to store channel control structures. The control table can be located anywhere in system memory, but must be contiguous and aligned on a 1024-byte boundary.

dmaErrorFxn is the uDMA peripheral's error interrupt handler.

intPriority is priority of the uDMA peripheral's error interrupt, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().

A sample structure is shown below:

#include <ti/devices/cc32xx/driverlib/udma.h>

static tDMAControlTable dmaControlTable[64] __attribute__ ((aligned (1024)));

#include <ti/drivers/dma/UDMACC32XX.h>

UDMACC32XX_Object udmaCC32XXObject;

const UDMACC32XX_HWAttrs udmaCC32XXHWAttrs = {
        .controlBaseAddr = (void *)dmaControlTable,
        .dmaErrorFxn = UDMACC32XX_errorFxn,
        .intNum = INT_UDMAERR,
        .intPriority = (~0)
};

Field Documentation

controlBaseAddr

void* UDMACC32XX_HWAttrs::controlBaseAddr

uDMA control registers base address

dmaErrorFxn

UDMACC32XX_ErrorFxn UDMACC32XX_HWAttrs::dmaErrorFxn

uDMA error interrupt handler

intNum

uint8_t UDMACC32XX_HWAttrs::intNum

uDMA error interrupt number

intPriority

uint8_t UDMACC32XX_HWAttrs::intPriority

uDMA error interrupt priority.

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The documentation for this struct was generated from the following file:

• UDMACC32XX.h