| #define EDMA3_DRV_DMA_CHANNEL_ANY 1002u |
Used to specify any available DMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). DMA channel from the pool of (owned && non_reserved && available_right_now) DMA channels will be chosen and returned.
Referenced by EDMA3_DRV_requestChannel().
| #define EDMA3_DRV_LINK_CHANNEL 1005u |
Used to specify any available PaRAM Set while requesting one. Used in the API EDMA3_DRV_requestChannel(), for Link channels. PaRAM Set from the pool of (owned && non_reserved && available_right_now) PaRAM Sets will be chosen and returned.
Referenced by EDMA3_DRV_requestChannel().
| #define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS) |
QDMA Channel defines They should be used while requesting a specific QDMA channel.
QDMA Channel 0
Referenced by EDMA3_DRV_setPaRAMField().
| #define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u) |
QDMA Channel 1
| #define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u) |
QDMA Channel 2
| #define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u) |
QDMA Channel 3
| #define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u) |
QDMA Channel 4
| #define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u) |
QDMA Channel 5
| #define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u) |
QDMA Channel 6
| #define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u) |
QDMA Channel 7
Referenced by EDMA3_DRV_setPaRAMField().
| #define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u |
Used to specify any available QDMA Channel while requesting one. Used in the API EDMA3_DRV_requestChannel(). QDMA channel from the pool of (owned && non_reserved && available_right_now) QDMA channels will be chosen and returned.
Referenced by EDMA3_DRV_requestChannel().
| #define EDMA3_DRV_TCC_ANY 1004u |
Used to specify any available TCC while requesting one. Used in the API EDMA3_DRV_requestChannel(), for both DMA and QDMA channels. TCC from the pool of (owned && non_reserved && available_right_now) TCCs will be chosen and returned.
Referenced by EDMA3_DRV_requestChannel().
DMA Channels assigned to different Hardware Events. They should be used while requesting a specific DMA channel. One possible usage is to maintain a SoC specific file, which will contain the mapping of these hardware events to the respective peripherals for better understanding and lesser probability of errors. Also, if any event associated with a particular peripheral gets changed, only that SoC specific file needs to be changed.
for eg, the sample SoC specific file "soc.h" can have these defines:
define EDMA3_DRV_HW_CHANNEL_MCBSP_TX EDMA3_DRV_HW_CHANNEL_EVENT_2 define EDMA3_DRV_HW_CHANNEL_MCBSP_RX EDMA3_DRV_HW_CHANNEL_EVENT_3
These defines will be used by the MCBSP driver. The same event EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also.
| EDMA3_DRV_Result EDMA3_DRV_clearErrorBits | ( | EDMA3_DRV_Handle | hEdma, | |
| unsigned int | channelId | |||
| ) |
Clears Event Register and Error Register for a specific DMA channel and brings back EDMA3 to its initial state.
This API clears the Event register, Event Miss register Event Enable register for a specific DMA channel. It also clears the CC Error register.
| hEdma | [IN] Handle to the EDMA Driver Instance. | |
| channelId | [IN] DMA Channel needs to be cleaned. |
References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::shadowRegs.
| EDMA3_DRV_Result EDMA3_DRV_freeChannel | ( | EDMA3_DRV_Handle | hEdma, | |
| unsigned int | channelId | |||
| ) |
Free the specified channel (DMA/QDMA/Link) and its associated resources (PaRAM Set, TCC etc) and removes various mappings.
This API internally uses EDMA3_RM_freeResource () to free the desired resources.
For Link channels, this API only frees the associated PaRAM Set.
For DMA/QDMA channels, it does the following operations: a) Disable any ongoing transfer on the channel, b) Unregister the TCC Callback function and disable the interrupts, c) Remove the channel to Event Queue mapping, d) For DMA channels, clear the DCHMAP register, if available e) For QDMA channels, clear the QCHMAP register, f) Frees the DMA/QDMA channel in the end.
| hEdma | [IN] Handle to the EDMA Driver Instance. | |
| channelId | [IN] Logical Channel number to be freed. |
References EDMA3_DRV_CHANNEL_TYPE_DMA, EDMA3_DRV_CHANNEL_TYPE_LINK, EDMA3_DRV_CHANNEL_TYPE_NONE, EDMA3_DRV_CHANNEL_TYPE_QDMA, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LINK_CH_MAX_VAL, EDMA3_DRV_LINK_CH_MIN_VAL, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, and EDMA3_DRV_ChBoundResources::tcc.
Referenced by EDMA3_DRV_requestChannel().
| EDMA3_DRV_Result EDMA3_DRV_linkChannel | ( | EDMA3_DRV_Handle | hEdma, | |
| unsigned int | lCh1, | |||
| unsigned int | lCh2 | |||
| ) |
Link two logical channels.
This API is used to link two previously allocated logical (DMA/QDMA/Link) channels.
It sets the Link field of the PaRAM set associated with first logical channel (lCh1) to point it to the PaRAM set associated with second logical channel (lCh2).
It also sets the TCC field of PaRAM set associated with second logical channel to the same as that of the first logical channel.
After linking the channels, user should not update any PaRAM Set of the channel.
| hEdma | [IN] Handle to the EDMA Driver Instance. | |
| lCh1 | [IN] Logical Channel to which particular channel will be linked. | |
| lCh2 | [IN] Logical Channel which needs to be linked to the first channel. After the transfer based on the PaRAM set of lCh1 is over, the PaRAM set of lCh2 will be copied to the PaRAM set of lCh1 and transfer will resume. For DMA channels, another sync event is required to initiate the transfer on the Link channel. |
References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_GET_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.
| EDMA3_DRV_Result EDMA3_DRV_requestChannel | ( | EDMA3_DRV_Handle | hEdma, | |
| unsigned int * | pLCh, | |||
| unsigned int * | pTcc, | |||
| EDMA3_RM_EventQueue | evtQueue, | |||
| EDMA3_RM_TccCallback | tccCb, | |||
| void * | cbData | |||
| ) |
Request a DMA/QDMA/Link channel.
Each channel (DMA/QDMA/Link) must be requested before initiating a DMA transfer on that channel.
This API is used to allocate a logical channel (DMA/QDMA/Link) along with the associated resources. For DMA and QDMA channels, TCC and PaRAM Set are also allocated along with the requested channel. For Link channel, ONLY a PaRAM Set is allocated.
User can request a specific logical channel by passing the channel id in 'pLCh'. Note that the channel id is the same as the actual resource id in case of DMA channels. To allocate specific QDMA channels, user SHOULD use the defines EDMA3_DRV_QDMA_CHANNEL_X mentioned above.
User can also request ANY available logical channel also by specifying the below mentioned values in '*pLCh': a) EDMA3_DRV_DMA_CHANNEL_ANY: For DMA channels b) EDMA3_DRV_QDMA_CHANNEL_ANY: For QDMA channels, and c) EDMA3_DRV_LINK_CHANNEL: For Link channels. Normally user should use this value to request link channels (PaRAM Sets used for linking purpose only), unless he wants to use some specific link channels (PaRAM Sets) which is also allowed.
This API internally uses EDMA3_RM_allocResource () to allocate the desired resources (DMA/QDMA channel, PaRAM Set and TCC).
This API also registers a specific callback function against the allocated TCC.
For DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated. The event queue needs to be specified by the user.
For DMA channel, it also sets the DCHMAP register, if required.
For QDMA channel, it sets the QCHMAP register and CCNT as trigger word and enables the QDMA channel by writing to the QEESR register.
| hEdma | [IN] Handle to the previously opened Driver Instance. | |
| pLCh | [IN/OUT] Requested logical channel id. Examples:
|
In case user passes a specific channel Id, pLCh value is left unchanged. In case user requests ANY available resource, the allocated channel id is returned in pLCh.
This function will update *pLCh with the allocated Link channel handle. This handle could be DIFFERENT from the actual PaRAM Set allocated by the Resource Manager internally. So user SHOULD NOT assume the handle as the PaRAM Set Id.
| pTcc | [IN/OUT] The channel number on which the completion/error interrupt is generated. Not used if user requested for a Link channel. Examples:
|
| evtQueue | [IN] Event Queue Number to which the channel will be mapped (valid only for the Master Channel (DMA/QDMA) request) | |
| tccCb | [IN] TCC callback - caters to channel- specific events like "Event Miss Error" or "Transfer Complete" | |
| cbData | [IN] Data which will be passed directly to the tccCb callback function |
Fill the resource id, whose associated TCC needs to be registered. For QDMA channels, pass the actual QDMA channel no instead of (*pLCh).
Map the allocated PaRAM Set to the logical DMa/QDMA channel.
First check whether the mapping feature is supported on the underlying platform. In case it is not supported, dont call this API, because this API returns error in case the feature is not there.
References EDMA3_DRV_GblConfigParams::dmaChannelPaRAMMap, EDMA3_DRV_GblConfigParams::dmaChannelTccMap, EDMA3_DRV_GblConfigParams::dmaChPaRAMMapExists, EDMA3_DRV_CH_NO_PARAM_MAP, EDMA3_DRV_CH_NO_TCC_MAP, EDMA3_DRV_CHANNEL_TYPE_DMA, EDMA3_DRV_CHANNEL_TYPE_QDMA, EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMA_CHANNEL_ANY, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_DMAQNUM_SET_MASK, EDMA3_DRV_E_CH_PARAM_BIND_FAIL, EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL, EDMA3_DRV_E_TCC_REGISTER_FAIL, EDMA3_DRV_E_TCC_UNAVAIL, EDMA3_DRV_freeChannel(), EDMA3_DRV_LINK_CH_MAX_VAL, EDMA3_DRV_LINK_CH_MIN_VAL, EDMA3_DRV_LINK_CHANNEL, EDMA3_DRV_OPT_TCC_CLR_MASK, EDMA3_DRV_OPT_TCC_SET_MASK, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMA_CHANNEL_ANY, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_QDMAQNUM_SET_MASK, EDMA3_DRV_TCC_ANY, EDMA3_DRV_TRIG_MODE_NONE, EDMA3_DRV_TRIG_MODE_QDMA, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numDmaChannels, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, EDMA3_DRV_Object::phyCtrllerInstId, EDMA3_DRV_Instance::resMgrInstance, EDMA3_DRV_Instance::shadowRegs, EDMA3_DRV_ChBoundResources::tcc, and EDMA3_DRV_ChBoundResources::trigMode.
| EDMA3_DRV_Result EDMA3_DRV_unlinkChannel | ( | EDMA3_DRV_Handle | hEdma, | |
| unsigned int | lCh | |||
| ) |
Unlink the channel from the earlier linked logical channel.
This function breaks the link between the specified channel and the earlier linked logical channel by clearing the Link Address field.
| hEdma | [IN] Handle to the EDMA Driver Instance. | |
| lCh | [IN] Channel for which linking has to be removed |
References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.
1.5.9