Instance: EVENT
Component: EVENT
Base address: 0x40083000
Event Fabric Component Definition
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x0000 0004 |
0x0000 0000 |
0x4008 3000 |
|
RO |
32 |
0x0000 0009 |
0x0000 0004 |
0x4008 3004 |
|
RO |
32 |
0x0000 001E |
0x0000 0008 |
0x4008 3008 |
|
RO |
32 |
0x0000 0038 |
0x0000 000C |
0x4008 300C |
|
RO |
32 |
0x0000 0007 |
0x0000 0010 |
0x4008 3010 |
|
RO |
32 |
0x0000 0024 |
0x0000 0014 |
0x4008 3014 |
|
RO |
32 |
0x0000 001C |
0x0000 0018 |
0x4008 3018 |
|
RO |
32 |
0x0000 0022 |
0x0000 001C |
0x4008 301C |
|
RO |
32 |
0x0000 0023 |
0x0000 0020 |
0x4008 3020 |
|
RO |
32 |
0x0000 001B |
0x0000 0024 |
0x4008 3024 |
|
RO |
32 |
0x0000 001A |
0x0000 0028 |
0x4008 3028 |
|
RO |
32 |
0x0000 0019 |
0x0000 002C |
0x4008 302C |
|
RO |
32 |
0x0000 0008 |
0x0000 0030 |
0x4008 3030 |
|
RO |
32 |
0x0000 001D |
0x0000 0034 |
0x4008 3034 |
|
RO |
32 |
0x0000 0018 |
0x0000 0038 |
0x4008 3038 |
|
RO |
32 |
0x0000 0010 |
0x0000 003C |
0x4008 303C |
|
RO |
32 |
0x0000 0011 |
0x0000 0040 |
0x4008 3040 |
|
RO |
32 |
0x0000 0012 |
0x0000 0044 |
0x4008 3044 |
|
RO |
32 |
0x0000 0013 |
0x0000 0048 |
0x4008 3048 |
|
RO |
32 |
0x0000 000C |
0x0000 004C |
0x4008 304C |
|
RO |
32 |
0x0000 000D |
0x0000 0050 |
0x4008 3050 |
|
RO |
32 |
0x0000 000E |
0x0000 0054 |
0x4008 3054 |
|
RO |
32 |
0x0000 000F |
0x0000 0058 |
0x4008 3058 |
|
RO |
32 |
0x0000 005D |
0x0000 005C |
0x4008 305C |
|
RO |
32 |
0x0000 0027 |
0x0000 0060 |
0x4008 3060 |
|
RO |
32 |
0x0000 0026 |
0x0000 0064 |
0x4008 3064 |
|
RO |
32 |
0x0000 0015 |
0x0000 0068 |
0x4008 3068 |
|
RO |
32 |
0x0000 0064 |
0x0000 006C |
0x4008 306C |
|
RO |
32 |
0x0000 000B |
0x0000 0070 |
0x4008 3070 |
|
RO |
32 |
0x0000 0001 |
0x0000 0074 |
0x4008 3074 |
|
RW |
32 |
0x0000 0000 |
0x0000 0078 |
0x4008 3078 |
|
RO |
32 |
0x0000 006A |
0x0000 007C |
0x4008 307C |
|
RO |
32 |
0x0000 0073 |
0x0000 0080 |
0x4008 3080 |
|
RO |
32 |
0x0000 0068 |
0x0000 0084 |
0x4008 3084 |
|
RO |
32 |
0x0000 003D |
0x0000 0100 |
0x4008 3100 |
|
RO |
32 |
0x0000 003E |
0x0000 0104 |
0x4008 3104 |
|
RO |
32 |
0x0000 003F |
0x0000 0108 |
0x4008 3108 |
|
RO |
32 |
0x0000 0040 |
0x0000 010C |
0x4008 310C |
|
RO |
32 |
0x0000 0041 |
0x0000 0110 |
0x4008 3110 |
|
RO |
32 |
0x0000 0042 |
0x0000 0114 |
0x4008 3114 |
|
RO |
32 |
0x0000 0043 |
0x0000 0118 |
0x4008 3118 |
|
RO |
32 |
0x0000 0044 |
0x0000 011C |
0x4008 311C |
|
RO |
32 |
0x0000 0077 |
0x0000 0120 |
0x4008 3120 |
|
RW |
32 |
0x0000 0002 |
0x0000 0124 |
0x4008 3124 |
|
RW |
32 |
0x0000 0055 |
0x0000 0200 |
0x4008 3200 |
|
RW |
32 |
0x0000 0056 |
0x0000 0204 |
0x4008 3204 |
|
RW |
32 |
0x0000 0057 |
0x0000 0300 |
0x4008 3300 |
|
RW |
32 |
0x0000 0058 |
0x0000 0304 |
0x4008 3304 |
|
RW |
32 |
0x0000 0059 |
0x0000 0400 |
0x4008 3400 |
|
RW |
32 |
0x0000 005A |
0x0000 0404 |
0x4008 3404 |
|
RO |
32 |
0x0000 0031 |
0x0000 0508 |
0x4008 3508 |
|
RO |
32 |
0x0000 0030 |
0x0000 050C |
0x4008 350C |
|
RO |
32 |
0x0000 0033 |
0x0000 0510 |
0x4008 3510 |
|
RO |
32 |
0x0000 0032 |
0x0000 0514 |
0x4008 3514 |
|
RO |
32 |
0x0000 0029 |
0x0000 0518 |
0x4008 3518 |
|
RO |
32 |
0x0000 0028 |
0x0000 051C |
0x4008 351C |
|
RO |
32 |
0x0000 002B |
0x0000 0520 |
0x4008 3520 |
|
RO |
32 |
0x0000 002A |
0x0000 0524 |
0x4008 3524 |
|
RO |
32 |
0x0000 003A |
0x0000 0528 |
0x4008 3528 |
|
RO |
32 |
0x0000 0039 |
0x0000 052C |
0x4008 352C |
|
RO |
32 |
0x0000 003C |
0x0000 0530 |
0x4008 3530 |
|
RO |
32 |
0x0000 003B |
0x0000 0534 |
0x4008 3534 |
|
RO |
32 |
0x0000 0075 |
0x0000 0538 |
0x4008 3538 |
|
RO |
32 |
0x0000 0076 |
0x0000 053C |
0x4008 353C |
|
RO |
32 |
0x0000 0074 |
0x0000 0540 |
0x4008 3540 |
|
RO |
32 |
0x0000 0074 |
0x0000 0544 |
0x4008 3544 |
|
RW |
32 |
0x0000 0045 |
0x0000 0548 |
0x4008 3548 |
|
RW |
32 |
0x0000 004D |
0x0000 054C |
0x4008 354C |
|
RW |
32 |
0x0000 0046 |
0x0000 0550 |
0x4008 3550 |
|
RW |
32 |
0x0000 004E |
0x0000 0554 |
0x4008 3554 |
|
RW |
32 |
0x0000 0047 |
0x0000 0558 |
0x4008 3558 |
|
RW |
32 |
0x0000 004F |
0x0000 055C |
0x4008 355C |
|
RW |
32 |
0x0000 0048 |
0x0000 0560 |
0x4008 3560 |
|
RW |
32 |
0x0000 0050 |
0x0000 0564 |
0x4008 3564 |
|
RO |
32 |
0x0000 0003 |
0x0000 056C |
0x4008 356C |
|
RW |
32 |
0x0000 0001 |
0x0000 0574 |
0x4008 3574 |
|
RO |
32 |
0x0000 0007 |
0x0000 057C |
0x4008 357C |
|
RO |
32 |
0x0000 002D |
0x0000 0580 |
0x4008 3580 |
|
RO |
32 |
0x0000 002C |
0x0000 0584 |
0x4008 3584 |
|
RO |
32 |
0x0000 002F |
0x0000 0588 |
0x4008 3588 |
|
RO |
32 |
0x0000 002E |
0x0000 058C |
0x4008 358C |
|
RO |
32 |
0x0000 0064 |
0x0000 05A8 |
0x4008 35A8 |
|
RO |
32 |
0x0000 0064 |
0x0000 05AC |
0x4008 35AC |
|
RO |
32 |
0x0000 0065 |
0x0000 05B0 |
0x4008 35B0 |
|
RO |
32 |
0x0000 0065 |
0x0000 05B4 |
0x4008 35B4 |
|
RO |
32 |
0x0000 0066 |
0x0000 05B8 |
0x4008 35B8 |
|
RO |
32 |
0x0000 0066 |
0x0000 05BC |
0x4008 35BC |
|
RO |
32 |
0x0000 0067 |
0x0000 05C0 |
0x4008 35C0 |
|
RO |
32 |
0x0000 0067 |
0x0000 05C4 |
0x4008 35C4 |
|
RW |
32 |
0x0000 005B |
0x0000 0600 |
0x4008 3600 |
|
RW |
32 |
0x0000 005C |
0x0000 0604 |
0x4008 3604 |
|
RW |
32 |
0x0000 0010 |
0x0000 0700 |
0x4008 3700 |
|
RO |
32 |
0x0000 0063 |
0x0000 0800 |
0x4008 3800 |
|
RW |
32 |
0x0000 005F |
0x0000 0900 |
0x4008 3900 |
|
RW |
32 |
0x0000 0078 |
0x0000 0A00 |
0x4008 3A00 |
|
RW |
32 |
0x0000 0000 |
0x0000 0F00 |
0x4008 3F00 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4008 3000 | Instance | 0x4008 3000 |
Description | Output Selection for CPU Interrupt 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 0100 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4008 3004 | Instance | 0x4008 3004 |
Description | Output Selection for CPU Interrupt 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 1001 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x4008 3008 | Instance | 0x4008 3008 |
Description | Output Selection for CPU Interrupt 2 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 1110 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x4008 300C | Instance | 0x4008 300C |
Description | Output Selection for CPU Interrupt 3 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0038 |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4008 3010 | Instance | 0x4008 3010 |
Description | Output Selection for CPU Interrupt 4 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 0111 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4008 3014 | Instance | 0x4008 3014 |
Description | Output Selection for CPU Interrupt 5 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 0100 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x4008 3018 | Instance | 0x4008 3018 |
Description | Output Selection for CPU Interrupt 6 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 1100 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4008 301C | Instance | 0x4008 301C |
Description | Output Selection for CPU Interrupt 7 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 0010 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4008 3020 | Instance | 0x4008 3020 |
Description | Output Selection for CPU Interrupt 8 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 0011 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4008 3024 | Instance | 0x4008 3024 |
Description | Output Selection for CPU Interrupt 9 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 1011 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4008 3028 | Instance | 0x4008 3028 |
Description | Output Selection for CPU Interrupt 10 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 1010 |
Address Offset | 0x0000 002C | ||
Physical Address | 0x4008 302C | Instance | 0x4008 302C |
Description | Output Selection for CPU Interrupt 11 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 1001 |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4008 3030 | Instance | 0x4008 3030 |
Description | Output Selection for CPU Interrupt 12 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 1000 |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4008 3034 | Instance | 0x4008 3034 |
Description | Output Selection for CPU Interrupt 13 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 1101 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4008 3038 | Instance | 0x4008 3038 |
Description | Output Selection for CPU Interrupt 14 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 1000 |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4008 303C | Instance | 0x4008 303C |
Description | Output Selection for CPU Interrupt 15 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 0000 |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4008 3040 | Instance | 0x4008 3040 |
Description | Output Selection for CPU Interrupt 16 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 0001 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4008 3044 | Instance | 0x4008 3044 |
Description | Output Selection for CPU Interrupt 17 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 0010 |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4008 3048 | Instance | 0x4008 3048 |
Description | Output Selection for CPU Interrupt 18 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 0011 |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4008 304C | Instance | 0x4008 304C |
Description | Output Selection for CPU Interrupt 19 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 1100 |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4008 3050 | Instance | 0x4008 3050 |
Description | Output Selection for CPU Interrupt 20 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 1101 |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4008 3054 | Instance | 0x4008 3054 |
Description | Output Selection for CPU Interrupt 21 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 1110 |
Address Offset | 0x0000 0058 | ||
Physical Address | 0x4008 3058 | Instance | 0x4008 3058 |
Description | Output Selection for CPU Interrupt 22 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 1111 |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4008 305C | Instance | 0x4008 305C |
Description | Output Selection for CPU Interrupt 23 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b101 1101 |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4008 3060 | Instance | 0x4008 3060 |
Description | Output Selection for CPU Interrupt 24 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 0111 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4008 3064 | Instance | 0x4008 3064 |
Description | Output Selection for CPU Interrupt 25 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 0110 |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4008 3068 | Instance | 0x4008 3068 |
Description | Output Selection for CPU Interrupt 26 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b001 0101 |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4008 306C | Instance | 0x4008 306C |
Description | Output Selection for CPU Interrupt 27 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0100 |
Address Offset | 0x0000 0070 | ||
Physical Address | 0x4008 3070 | Instance | 0x4008 3070 |
Description | Output Selection for CPU Interrupt 28 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 1011 |
Address Offset | 0x0000 0074 | ||
Physical Address | 0x4008 3074 | Instance | 0x4008 3074 |
Description | Output Selection for CPU Interrupt 29 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 0001 |
Address Offset | 0x0000 0078 | ||
Physical Address | 0x4008 3078 | Instance | 0x4008 3078 |
Description | Output Selection for CPU Interrupt 30 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b000 0000 |
Address Offset | 0x0000 007C | ||
Physical Address | 0x4008 307C | Instance | 0x4008 307C |
Description | Output Selection for CPU Interrupt 31 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 1010 |
Address Offset | 0x0000 0080 | ||
Physical Address | 0x4008 3080 | Instance | 0x4008 3080 |
Description | Output Selection for CPU Interrupt 32 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b111 0011 |
Address Offset | 0x0000 0084 | ||
Physical Address | 0x4008 3084 | Instance | 0x4008 3084 |
Description | Output Selection for CPU Interrupt 33 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 1000 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4008 3100 | Instance | 0x4008 3100 |
Description | Output Selection for RFC Event 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b011 1101 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4008 3104 | Instance | 0x4008 3104 |
Description | Output Selection for RFC Event 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b011 1110 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4008 3108 | Instance | 0x4008 3108 |
Description | Output Selection for RFC Event 2 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b011 1111 |
Address Offset | 0x0000 010C | ||
Physical Address | 0x4008 310C | Instance | 0x4008 310C |
Description | Output Selection for RFC Event 3 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b100 0000 |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4008 3110 | Instance | 0x4008 3110 |
Description | Output Selection for RFC Event 4 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b100 0001 |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4008 3114 | Instance | 0x4008 3114 |
Description | Output Selection for RFC Event 5 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b100 0010 |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x4008 3118 | Instance | 0x4008 3118 |
Description | Output Selection for RFC Event 6 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b100 0011 |
Address Offset | 0x0000 011C | ||
Physical Address | 0x4008 311C | Instance | 0x4008 311C |
Description | Output Selection for RFC Event 7 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b100 0100 |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x4008 3120 | Instance | 0x4008 3120 |
Description | Output Selection for RFC Event 8 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b111 0111 |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x4008 3124 | Instance | 0x4008 3124 |
Description | Output Selection for RFC Event 9 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b000 0010 |
Address Offset | 0x0000 0200 | ||
Physical Address | 0x4008 3200 | Instance | 0x4008 3200 |
Description | Output Selection for GPT0 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 0101 |
Address Offset | 0x0000 0204 | ||
Physical Address | 0x4008 3204 | Instance | 0x4008 3204 |
Description | Output Selection for GPT0 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 0110 |
Address Offset | 0x0000 0300 | ||
Physical Address | 0x4008 3300 | Instance | 0x4008 3300 |
Description | Output Selection for GPT1 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 0111 |
Address Offset | 0x0000 0304 | ||
Physical Address | 0x4008 3304 | Instance | 0x4008 3304 |
Description | Output Selection for GPT1 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 1000 |
Address Offset | 0x0000 0400 | ||
Physical Address | 0x4008 3400 | Instance | 0x4008 3400 |
Description | Output Selection for GPT2 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 1001 |
Address Offset | 0x0000 0404 | ||
Physical Address | 0x4008 3404 | Instance | 0x4008 3404 |
Description | Output Selection for GPT2 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 1010 |
Address Offset | 0x0000 0508 | ||
Physical Address | 0x4008 3508 | Instance | 0x4008 3508 |
Description | Output Selection for DMA Channel 1 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b011 0001 |
Address Offset | 0x0000 050C | ||
Physical Address | 0x4008 350C | Instance | 0x4008 350C |
Description | Output Selection for DMA Channel 1 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b011 0000 |
Address Offset | 0x0000 0510 | ||
Physical Address | 0x4008 3510 | Instance | 0x4008 3510 |
Description | Output Selection for DMA Channel 2 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b011 0011 |
Address Offset | 0x0000 0514 | ||
Physical Address | 0x4008 3514 | Instance | 0x4008 3514 |
Description | Output Selection for DMA Channel 2 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b011 0010 |
Address Offset | 0x0000 0518 | ||
Physical Address | 0x4008 3518 | Instance | 0x4008 3518 |
Description | Output Selection for DMA Channel 3 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 1001 |
Address Offset | 0x0000 051C | ||
Physical Address | 0x4008 351C | Instance | 0x4008 351C |
Description | Output Selection for DMA Channel 3 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 1000 |
Address Offset | 0x0000 0520 | ||
Physical Address | 0x4008 3520 | Instance | 0x4008 3520 |
Description | Output Selection for DMA Channel 4 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 1011 |
Address Offset | 0x0000 0524 | ||
Physical Address | 0x4008 3524 | Instance | 0x4008 3524 |
Description | Output Selection for DMA Channel 4 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 1010 |
Address Offset | 0x0000 0528 | ||
Physical Address | 0x4008 3528 | Instance | 0x4008 3528 |
Description | Output Selection for DMA Channel 5 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 003A |
Address Offset | 0x0000 052C | ||
Physical Address | 0x4008 352C | Instance | 0x4008 352C |
Description | Output Selection for DMA Channel 5 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 0039 |
Address Offset | 0x0000 0530 | ||
Physical Address | 0x4008 3530 | Instance | 0x4008 3530 |
Description | Output Selection for DMA Channel 6 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 003C |
Address Offset | 0x0000 0534 | ||
Physical Address | 0x4008 3534 | Instance | 0x4008 3534 |
Description | Output Selection for DMA Channel 6 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 003B |
Address Offset | 0x0000 0538 | ||
Physical Address | 0x4008 3538 | Instance | 0x4008 3538 |
Description | Output Selection for DMA Channel 7 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b111 0101 |
Address Offset | 0x0000 053C | ||
Physical Address | 0x4008 353C | Instance | 0x4008 353C |
Description | Output Selection for DMA Channel 7 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b111 0110 |
Address Offset | 0x0000 0540 | ||
Physical Address | 0x4008 3540 | Instance | 0x4008 3540 |
Description | Output Selection for DMA Channel 8 SREQ Single request is ignored for this channel |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b111 0100 |
Address Offset | 0x0000 0544 | ||
Physical Address | 0x4008 3544 | Instance | 0x4008 3544 |
Description | Output Selection for DMA Channel 8 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b111 0100 |
Address Offset | 0x0000 0548 | ||
Physical Address | 0x4008 3548 | Instance | 0x4008 3548 |
Description | Output Selection for DMA Channel 9 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b100 0101 |
Address Offset | 0x0000 054C | ||
Physical Address | 0x4008 354C | Instance | 0x4008 354C |
Description | Output Selection for DMA Channel 9 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b100 1101 |
Address Offset | 0x0000 0550 | ||
Physical Address | 0x4008 3550 | Instance | 0x4008 3550 |
Description | Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b100 0110 |
Address Offset | 0x0000 0554 | ||
Physical Address | 0x4008 3554 | Instance | 0x4008 3554 |
Description | Output Selection for DMA Channel 10 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b100 1110 |
Address Offset | 0x0000 0558 | ||
Physical Address | 0x4008 3558 | Instance | 0x4008 3558 |
Description | Output Selection for DMA Channel 11 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b100 0111 |
Address Offset | 0x0000 055C | ||
Physical Address | 0x4008 355C | Instance | 0x4008 355C |
Description | Output Selection for DMA Channel 11 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b100 1111 |
Address Offset | 0x0000 0560 | ||
Physical Address | 0x4008 3560 | Instance | 0x4008 3560 |
Description | Output Selection for DMA Channel 12 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b100 1000 |
Address Offset | 0x0000 0564 | ||
Physical Address | 0x4008 3564 | Instance | 0x4008 3564 |
Description | Output Selection for DMA Channel 12 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 0000 |
Address Offset | 0x0000 056C | ||
Physical Address | 0x4008 356C | Instance | 0x4008 356C |
Description | Output Selection for DMA Channel 13 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 0011 |
Address Offset | 0x0000 0574 | ||
Physical Address | 0x4008 3574 | Instance | 0x4008 3574 |
Description | Output Selection for DMA Channel 14 REQ | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b000 0001 |
Address Offset | 0x0000 057C | ||
Physical Address | 0x4008 357C | Instance | 0x4008 357C |
Description | Output Selection for DMA Channel 15 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b000 0111 |
Address Offset | 0x0000 0580 | ||
Physical Address | 0x4008 3580 | Instance | 0x4008 3580 |
Description | Output Selection for DMA Channel 16 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 1101 |
Address Offset | 0x0000 0584 | ||
Physical Address | 0x4008 3584 | Instance | 0x4008 3584 |
Description | Output Selection for DMA Channel 16 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 1100 |
Address Offset | 0x0000 0588 | ||
Physical Address | 0x4008 3588 | Instance | 0x4008 3588 |
Description | Output Selection for DMA Channel 17 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 1111 |
Address Offset | 0x0000 058C | ||
Physical Address | 0x4008 358C | Instance | 0x4008 358C |
Description | Output Selection for DMA Channel 17 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b010 1110 |
Address Offset | 0x0000 05A8 | ||
Physical Address | 0x4008 35A8 | Instance | 0x4008 35A8 |
Description | Output Selection for DMA Channel 21 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0100 |
Address Offset | 0x0000 05AC | ||
Physical Address | 0x4008 35AC | Instance | 0x4008 35AC |
Description | Output Selection for DMA Channel 21 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0100 |
Address Offset | 0x0000 05B0 | ||
Physical Address | 0x4008 35B0 | Instance | 0x4008 35B0 |
Description | Output Selection for DMA Channel 22 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0101 |
Address Offset | 0x0000 05B4 | ||
Physical Address | 0x4008 35B4 | Instance | 0x4008 35B4 |
Description | Output Selection for DMA Channel 22 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0101 |
Address Offset | 0x0000 05B8 | ||
Physical Address | 0x4008 35B8 | Instance | 0x4008 35B8 |
Description | Output Selection for DMA Channel 23 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0110 |
Address Offset | 0x0000 05BC | ||
Physical Address | 0x4008 35BC | Instance | 0x4008 35BC |
Description | Output Selection for DMA Channel 23 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0110 |
Address Offset | 0x0000 05C0 | ||
Physical Address | 0x4008 35C0 | Instance | 0x4008 35C0 |
Description | Output Selection for DMA Channel 24 SREQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0111 |
Address Offset | 0x0000 05C4 | ||
Physical Address | 0x4008 35C4 | Instance | 0x4008 35C4 |
Description | Output Selection for DMA Channel 24 REQ | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0111 |
Address Offset | 0x0000 0600 | ||
Physical Address | 0x4008 3600 | Instance | 0x4008 3600 |
Description | Output Selection for GPT3 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 1011 |
Address Offset | 0x0000 0604 | ||
Physical Address | 0x4008 3604 | Instance | 0x4008 3604 |
Description | Output Selection for GPT3 1 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 1100 |
Address Offset | 0x0000 0700 | ||
Physical Address | 0x4008 3700 | Instance | 0x4008 3700 |
Description | Output Selection for AUX Subscriber 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b001 0000 |
Address Offset | 0x0000 0800 | ||
Physical Address | 0x4008 3800 | Instance | 0x4008 3800 |
Description | Output Selection for NMI Subscriber 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||
6:0 | EV | Read only selection value
|
RO | 0b110 0011 |
Address Offset | 0x0000 0900 | ||
Physical Address | 0x4008 3900 | Instance | 0x4008 3900 |
Description | Output Selection for I2S Subscriber 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b101 1111 |
Address Offset | 0x0000 0A00 | ||
Physical Address | 0x4008 3A00 | Instance | 0x4008 3A00 |
Description | Output Selection for FRZ Subscriber 0 | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||
31:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | ||||||||||||||
6:0 | EV | Read/write selection value
|
RW | 0b111 1000 |
Address Offset | 0x0000 0F00 | ||
Physical Address | 0x4008 3F00 | Instance | 0x4008 3F00 |
Description | Set or Clear Software Events | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:25 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
24 | SWEV3 | Writing "1" to this bit when the value is "0" triggers the Software 3 event. | RW | 0 | ||
23:17 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
16 | SWEV2 | Writing "1" to this bit when the value is "0" triggers the Software 2 event. | RW | 0 | ||
15:9 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
8 | SWEV1 | Writing "1" to this bit when the value is "0" triggers the Software 1 event. | RW | 0 | ||
7:1 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
0 | SWEV0 | Writing "1" to this bit when the value is "0" triggers the Software 0 event. | RW | 0 |
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