Instance: AUX_TDC
Component: AUX_TDC
Base address: 0x400C4000
AUX Time To Digital Converter
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RW |
32 |
0x0000 0000 |
0x0000 0000 |
0x400C 4000 |
|
RO |
32 |
0x0000 0006 |
0x0000 0004 |
0x400C 4004 |
|
RO |
32 |
0x0000 0002 |
0x0000 0008 |
0x400C 4008 |
|
RW |
32 |
0x0000 000F |
0x0000 000C |
0x400C 400C |
|
RW |
32 |
0x0000 0000 |
0x0000 0010 |
0x400C 4010 |
|
RW |
32 |
0x0000 0000 |
0x0000 0014 |
0x400C 4014 |
|
RW |
32 |
0x0000 0000 |
0x0000 0018 |
0x400C 4018 |
|
RW |
32 |
0x0000 0000 |
0x0000 001C |
0x400C 401C |
|
RW |
32 |
0x0000 001F |
0x0000 0020 |
0x400C 4020 |
|
RW |
32 |
0x0000 0000 |
0x0000 0024 |
0x400C 4024 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x400C 4000 | Instance | 0x400C 4000 |
Description | Control | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||||||||
1:0 | CMD | TDC command strobes
|
WO | 0b00 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x400C 4004 | Instance | 0x400C 4004 |
Description | Status | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | ||||||||||||||||||||||||||||||||||||||
7 | SAT | Saturation flag for TDC measurement 0: Conversion has not saturated 1: Conversion stopped due to saturation This field is cleared when starting new measurement or setting CTL.CMD to CLR_RESULT |
RO | 0 | ||||||||||||||||||||||||||||||||||||||
6 | DONE | Measurement complete flag 0: Measurement not yet complete 1: Measurement complete This field is cleared when starting new measurement or setting CTL.CMD to CLR_RESULT |
RO | 0 | ||||||||||||||||||||||||||||||||||||||
5:0 | STATE | TDC internal state machine status
|
RO | 0b00 0110 |
Address Offset | 0x0000 0008 | ||
Physical Address | 0x400C 4008 | Instance | 0x400C 4008 |
Description | Result Result of last TDC conversion |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:25 | RESERVED25 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | ||
24:0 | VALUE | Result of the TDC conversion. The result is in clock edges of the clock selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and falling edges are counted. When saturating the result is slightly higher than the saturation limit, since it takes a non-zero time to stop the measurement. The highest saturation limit is 24 bits (see SATCFG.LIMIT) so maximum value of VALUE is hence slightly above 2^24. |
RO | 0b0 0000 0000 0000 0000 0000 0010 |
Address Offset | 0x0000 000C | ||
Physical Address | 0x400C 400C | Instance | 0x400C 400C |
Description | Saturation Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||||||||||||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | ||||||||||||||||||||||||||||||||||||||||||||
3:0 | LIMIT | Select when the TDC times out. Values not enumerated are not supported
|
RW | 0xF |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x400C 4010 | Instance | 0x400C 4010 |
Description | Trigger Source TDC start/stop trigger source selection |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:14 | RESERVED14 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 | STOP_POL | Polarity of stop signal. Note! Must not be changed if STAT.STATE is not IDLE
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12:8 | STOP_SRC | Selects the asynchronous stop signal Note! Must not be changed if STAT.STATE is not IDLE
|
RW | 0b0 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | START_POL | Polarity of start signal. Note! Must not be changed if STAT.STATE is not IDLE
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | START_SRC | Selects the asynchronous start signal Note! Must not be changed if STAT.STATE is not IDLE
|
RW | 0b0 0000 |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x400C 4014 | Instance | 0x400C 4014 |
Description | Trigger Counter Stop counter status/control of TDC |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | CNT | Remaining number of stop events that will be ignored. Writing to this register updates the value. The CNT will be loaded with the value of TRIGCNTLOAD.CNT at the start of every measurement. When the stop counter is enabled the first CNT-1 stop events is ignored after which the TDC will stop measurement on event number CNT Note! Must not be changed if STAT.STATE is not IDLE |
RW | 0x0000 |
Address Offset | 0x0000 0018 | ||
Physical Address | 0x400C 4018 | Instance | 0x400C 4018 |
Description | Trigger Counter Load Stop counter control of TDC |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | CNT | Selects the number of stop events that will be ignored by the TDC. This can be used to measure multiple periods of a clock signal. The value written to this field is loaded into the stop counter at the start of each measurement. Note! Both values 0 and 1 will make the TDC stop on the first event after the start event Note! Must not be changed if STAT.STATE is not IDLE |
RW | 0x0000 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x400C 401C | Instance | 0x400C 401C |
Description | Trigger Counter Configuration | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||
0 | EN | Stop counter enable 0: Stop counter is disabled 1: Stop counter is enabled |
RW | 0 |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x400C 4020 | Instance | 0x400C 4020 |
Description | Prescaler Control The prescaler can be used to count events that are faster than the AUX clock speed. It can be used standalone or as a start/stop source for the TDC by configuring TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to TDC_PRE. When counting fast signals with the TDC that are faster than 1/10th of the clock frequency of AUX it is recommended to use the prescaler. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | RESET_N | Prescaler reset control 0: Prescaler is held in reset 1: Prescaler is not held in reset |
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | RATIO | Prescaler ratio. This controls how often an event is generated on the TDC_PRE line. After the prescaler is reset the event output TDC_PRE is 0.
|
RW | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | RESERVED5 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | SRC | Selects event for prescaler to use as input Note! Only change when prescaler is in reset
|
RW | 0b1 1111 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x400C 4024 | Instance | 0x400C 4024 |
Description | Prescaler Counter Value of prescaler counter |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0000 | ||
15:0 | CNT | Writing to this register will latch the contents of the 16 bit prescaler counter (The value written is don't care). Reading will return the latched value. |
RW | 0x0000 |
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