40 #include <inc/hw_memmap.h>
41 #include <inc/hw_types.h>
42 #include <inc/hw_adi.h>
43 #include <inc/hw_adi_0_rf.h>
44 #include <inc/hw_adi_1_synth.h>
45 #include <inc/hw_adi_2_refsys.h>
46 #include <inc/hw_adi_3_refsys.h>
47 #include <inc/hw_adi_4_aux.h>
48 #include <inc/hw_aon_ioc.h>
49 #include <inc/hw_aon_sysctl.h>
50 #include <inc/hw_aon_wuc.h>
51 #include <inc/hw_aux_wuc.h>
52 #include <inc/hw_ccfg.h>
53 #include <inc/hw_chip_def.h>
54 #include <inc/hw_ddi.h>
55 #include <inc/hw_flash.h>
56 #include <inc/hw_fcfg1.h>
57 #include <inc/hw_ddi_0_osc.h>
58 #include <inc/hw_prcm.h>
59 #include <inc/hw_vims.h>
60 #include <inc/hw_aon_batmon.h>
61 #include <inc/hw_aon_rtc.h>
74 #ifdef __IAR_SYSTEMS_ICC__
75 #include <intrinsics.h>
111 #define DELAY_20_USEC 0x140
123 #define CPU_DELAY_MICRO_SECONDS( x ) \
124 CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 )
148 uint32_t vimsCtlMode0 ;
193 uint32_t ui32Fcfg1Revision;
194 uint32_t ui32AonSysResetctl;
201 if ( ui32Fcfg1Revision == 0xFFFFFFFF ) {
202 ui32Fcfg1Revision = 0;
378 uint32_t ccfg_ModeConfReg ;
379 uint32_t currentHfClock ;
380 uint32_t ccfgExtLfClk ;
381 int32_t i32VddrSleepTrim ;
382 int32_t i32VddrSleepDelta ;
383 uint32_t fcfg1OscConf ;
481 i32VddrSleepDelta = ((((int32_t)ccfg_ModeConfReg )
483 >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W ));
485 i32VddrSleepTrim = ( i32VddrSleepTrim + i32VddrSleepDelta + 1 );
486 if ( i32VddrSleepTrim > 21 ) i32VddrSleepTrim = 21;
487 if ( i32VddrSleepTrim < -10 ) i32VddrSleepTrim = -10;
554 ( 0x20 | ( ui32Trim << 1 ));
563 ( 0x10 | ( ui32Trim ));
582 ( 0x60 | ( ui32Trim << 1 ));
593 ( 0x80 | ( ui32Trim << 3 ));
605 ( 0xFC00 | ( ui32Trim << 2 ));
625 mp1rev = ( HWREG(
FCFG1_BASE + 0x00000314 ) & 0x0000FFFF );
626 if ( mp1rev < 542 ) {
627 uint32_t vtrim_bod = (( HWREG(
FCFG1_BASE + 0x000002BC ) >> 24 ) & 0xF );
628 uint32_t vtrim_udig = (( HWREG(
FCFG1_BASE + 0x000002BC ) >> 16 ) & 0xF );
629 if ( vtrim_bod > 0 ) {
632 if ( vtrim_udig != 7 ) {
633 if ( vtrim_udig == 6 ) {
636 vtrim_udig = (( vtrim_udig + 2 ) & 0xF );
782 int32_t i32SignedVddrVal = ui32VddrTrimVal;
783 if ( i32SignedVddrVal > 0x15 ) {
784 i32SignedVddrVal -= 0x20;
786 return ( i32SignedVddrVal );
812 uint32_t ui32Fcfg1Value ;
813 uint32_t ui32XoscHfRow ;
814 uint32_t ui32XoscHfCol ;
815 int32_t i32CustomerDeltaAdjust ;
816 uint32_t ui32TrimValue ;
824 ui32XoscHfRow = (( ui32Fcfg1Value &
827 ui32XoscHfCol = (( ui32Fcfg1Value &
831 i32CustomerDeltaAdjust = 0;
839 i32CustomerDeltaAdjust = ((int32_t)ccfg_ModeConfReg << 16 ) >> 24;
841 while ( i32CustomerDeltaAdjust < 0 ) {
843 if ( ui32XoscHfCol == 0 ) {
844 ui32XoscHfCol = 0xFFFF;
846 if ( ui32XoscHfRow == 0 ) {
851 i32CustomerDeltaAdjust++;
853 while ( i32CustomerDeltaAdjust > 0 ) {
854 ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1;
855 if ( ui32XoscHfCol > 0xFFFF ) {
857 ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1;
858 if ( ui32XoscHfRow > 0xF ) {
860 ui32XoscHfCol = 0xFFFF;
863 i32CustomerDeltaAdjust--;
870 return (ui32TrimValue);
882 uint32_t ui32TrimValue;
898 return(ui32TrimValue);
910 uint32_t ui32TrimValue;
919 return(ui32TrimValue);
930 uint32_t ui32TrimValue;
931 uint32_t ui32Fcfg1Value;
937 ui32TrimValue = ((ui32Fcfg1Value &
941 ui32TrimValue |= (((ui32Fcfg1Value &
945 ui32TrimValue |= (((ui32Fcfg1Value &
949 ui32TrimValue |= (((ui32Fcfg1Value &
954 return(ui32TrimValue);
965 uint32_t ui32TrimValue;
966 uint32_t ui32Fcfg1Value;
972 ui32TrimValue = (((ui32Fcfg1Value &
976 ui32TrimValue |= (((ui32Fcfg1Value &
980 ui32TrimValue |= (((ui32Fcfg1Value &
984 ui32TrimValue |= (((ui32Fcfg1Value &
989 return(ui32TrimValue);
1000 uint32_t ui32TrimValue ;
1001 uint32_t ui32Fcfg1Value ;
1002 uint32_t ibiasOffset ;
1003 uint32_t ibiasInit ;
1004 uint32_t modeConf1 ;
1005 int32_t deltaAdjust ;
1012 ibiasOffset = ( ui32Fcfg1Value &
1015 ibiasInit = ( ui32Fcfg1Value &
1025 deltaAdjust += (int32_t)ibiasOffset;
1026 if ( deltaAdjust < 0 ) {
1032 ibiasOffset = (uint32_t)deltaAdjust;
1035 deltaAdjust += (int32_t)ibiasInit;
1036 if ( deltaAdjust < 0 ) {
1042 ibiasInit = (uint32_t)deltaAdjust;
1047 ui32TrimValue |= (((ui32Fcfg1Value &
1051 ui32TrimValue |= (((ui32Fcfg1Value &
1055 ui32TrimValue |= (((ui32Fcfg1Value &
1060 if ( ui32Fcfg1Revision >= 0x00000022 ) {
1061 ui32TrimValue |= ((( ui32Fcfg1Value &
1067 return(ui32TrimValue);
1078 uint32_t dblrLoopFilterResetVoltageValue = 0;
1080 if ( ui32Fcfg1Revision >= 0x00000020 ) {
1086 return ( dblrLoopFilterResetVoltageValue );
1097 uint32_t getTrimForAdcShModeEnValue = 1;
1099 if ( ui32Fcfg1Revision >= 0x00000022 ) {
1105 return ( getTrimForAdcShModeEnValue );
1116 uint32_t getTrimForAdcShVbufEnValue = 1;
1118 if ( ui32Fcfg1Revision >= 0x00000022 ) {
1124 return ( getTrimForAdcShVbufEnValue );
1135 uint32_t getTrimForXoschfCtlValue = 0;
1138 if ( ui32Fcfg1Revision >= 0x00000020 ) {
1140 getTrimForXoschfCtlValue =
1145 getTrimForXoschfCtlValue |=
1150 getTrimForXoschfCtlValue |=
1156 return ( getTrimForXoschfCtlValue );
1167 uint32_t ui32XoscHfFastStartValue ;
1174 return ( ui32XoscHfFastStartValue );
1185 uint32_t getTrimForRadcExtCfgValue = 0x403F8000;
1188 if ( ui32Fcfg1Revision >= 0x00000020 ) {
1190 getTrimForRadcExtCfgValue =
1195 getTrimForRadcExtCfgValue |=
1200 getTrimForRadcExtCfgValue |=
1206 return ( getTrimForRadcExtCfgValue );
1217 uint32_t trimForRcOscLfIBiasTrimValue = 0;
1219 if ( ui32Fcfg1Revision >= 0x00000022 ) {
1225 return ( trimForRcOscLfIBiasTrimValue );
1237 uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0;
1239 if ( ui32Fcfg1Revision >= 0x00000022 ) {
1246 return ( trimForXoscLfRegulatorAndCmirrwrRatioValue );
1259 uint32_t newTrimRaw ;
1260 int32_t targetTrim ;
1261 int32_t currentTrim ;
1287 if ( currentTrim != targetTrim ) {
1291 while ( currentTrim != targetTrim ) {
1292 deltaTrim = targetTrim - currentTrim;
1293 if ( deltaTrim > 2 ) deltaTrim = 2;
1294 if ( deltaTrim < -2 ) deltaTrim = -2;
1295 currentTrim += deltaTrim;
static void SysCtrlAonSync(void)
Sync all accesses to the AON register interface.
#define IOC_PORT_AON_CLK32K
static void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)
Write a 32 bit value to a register in the DDI slave.
#define AUX_WUC_POWER_DOWN
static void HapiTrimDevicePowerDown(void)
Trims to be applied when coming from POWER_DOWN (also called when coming from SHUTDOWN and PIN_RESET)...
static void HapiTrimDeviceShutDown(uint32_t ui32Fcfg1Revision)
Trims to be applied when coming from SHUTDOWN (also called when coming from PIN_RESET).
static uint32_t GetTrimForRadcExtCfg(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG.
void AUXWUCPowerCtrl(uint32_t ui32PowerMode)
Control the power to the AUX domain.
static uint32_t GetTrimForRcOscLfRtuneCtuneTrim(void)
Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the RCOSCLF_CTUNE_TRIM bit fields in...
uint32_t OSCClockSourceGet(uint32_t ui32SrcClk)
Get the source clock settings.
void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)
Write a bitfield via the DDI using 16-bit maskable write.
int32_t SignExtendVddrTrimValue(uint32_t ui32VddrTrimVal)
Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)
void ThisCodeIsBuiltForCC13xxHwRev20AndLater_HaltIfViolated(void)
Verifies that curent chip is built for CC13xx HwRev 2.0 or later and never returns if violated...
static uint32_t GetTrimForRcOscLfIBiasTrim(uint32_t ui32Fcfg1Revision)
Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM.
static uint32_t GetTrimForXoscLfRegulatorAndCmirrwrRatio(uint32_t ui32Fcfg1Revision)
Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet spanning bits [5:0] in the retur...
static uint32_t GetTrimForAmpcompTh2(void)
Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG.
static uint32_t GetTrimForAnabypassValue1(uint32_t ccfg_ModeConfReg)
Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG.
static uint32_t GetTrimForDblrLoopFilterResetVoltage(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting.
static void HapiTrimDeviceColdReset(void)
Trims to be applied when coming from PIN_RESET.
static uint32_t GetTrimForXoscHfFastStart(void)
Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START.
static uint32_t GetTrimForAdcShVbufEn(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting.
void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)
Set the configuration of an IO port.
static uint32_t GetTrimForXoscHfCtl(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG.
static uint32_t GetTrimForAdcShModeEn(uint32_t ui32Fcfg1Revision)
Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting.
static void SetAonRtcSubSecInc(uint32_t subSecInc)
Doing the tricky stuff needed to enter new RTCSUBSECINC value.
static uint32_t GetTrimForXoscHfIbiastherm(void)
Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in the ANABYPASS_VALUE2 regist...
void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc)
Configure the oscillator input to the a source clock.
static void SetupCacheModeAccordingToCcfgSetting(void)
Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM)
static uint32_t GetTrimForAmpcompTh1(void)
Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG.
void SetVddrLevel(uint32_t ccfg_ModeConfReg)
static uint32_t GetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision)
Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG.
void trimDevice(void)
Performs the necessary trim of the device which is not done in boot code.
static void AONWUCJtagPowerOff(void)
Request power off of the JTAG domain.