enum CacheNull_Type |
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Lists of bitmask cache types
typedef enum CacheNull_Type {
CacheNull_Type_L1P,
// Level 1 Program cache
CacheNull_Type_L1D,
// Level 1 Data cache
CacheNull_Type_L1,
// Level 1 caches
CacheNull_Type_L2P,
// Level 2 Program cache
CacheNull_Type_L2D,
// Level 2 Data cache
CacheNull_Type_L2,
// Level 2 caches
CacheNull_Type_ALLP,
// All Program caches
CacheNull_Type_ALLD,
// All Data caches
CacheNull_Type_ALL
// All caches
} CacheNull_Type;
CacheNull_disable() // module-wide |
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Disables the 'type' cache(s)
Void CacheNull_disable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
CacheNull_enable() // module-wide |
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Enables all cache(s)
Void CacheNull_enable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
CacheNull_inv() // module-wide |
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Invalidate the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
in range are invalidated for all the 'type' caches
Void CacheNull_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
CacheNull_wait() // module-wide |
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Wait for a previous cache operation to complete
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache
operation is not truly complete until it has worked its way
through all buffering and all memory writes have landed in the
source memory.
CacheNull_wb() // module-wide |
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Writes back a range of memory from all cache(s)
Void CacheNull_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
within the range are left valid in the 'type' caches and the data
within the range will be written back to the source memory.
CacheNull_wbAll() // module-wide |
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Write back all caches
DETAILS
Perform a global write back. There is no effect on program cache.
All data cache lines are left valid.
CacheNull_wbInv() // module-wide |
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Writes back and invalidates the range of memory within the
specified starting address and byte count. The range of
addresses operated on gets quantized to whole cache lines in
each cache. All lines within the range are written back to the
source memory and then invalidated for all 'type' caches
Void CacheNull_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
CacheNull_wbInvAll() // module-wide |
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Write back invalidate all caches
Void CacheNull_wbInvAll();
DETAILS
Performs a global write back and invalidate. All cache lines
are written out to physical memory and then invalidated.
Module-Wide Built-Ins |
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// Get this module's unique id
Bool CacheNull_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool CacheNull_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 CacheNull_Module_getMask();
// Returns the diagnostics mask for this module
Void CacheNull_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module