enum Cache_L1Size |
|
Level 1 cache size type definition. Can be used for both L1D & L1P
typedef enum Cache_L1Size {
Cache_L1Size_0K,
// Amount of cache is 0K, Amount of SRAM is 32K
Cache_L1Size_4K,
// Amount of cache is 4K, Amount of SRAM is 28K
Cache_L1Size_8K,
// Amount of cache is 8K, Amount of SRAM is 24K
Cache_L1Size_16K,
// Amount of cache is 16K, Amount of SRAM is 16K
Cache_L1Size_32K
// Amount of cache is 32K, Amount of SRAM is 0K
} Cache_L1Size;
enum Cache_L2Size |
|
Level 2 cache size type definition
typedef enum Cache_L2Size {
Cache_L2Size_0K,
// L2 is all SRAM
Cache_L2Size_32K,
// Amount of cache is 32K
Cache_L2Size_64K,
// Amount of cache is 64K
Cache_L2Size_128K,
// Amount of cache is 128K
Cache_L2Size_256K,
// Amount of cache is 256K
Cache_L2Size_512K,
// Amount of cache is 512K
Cache_L2Size_1024K
// Amount of cache is 1024K
} Cache_L2Size;
enum Cache_Mar |
|
MAR register setting type definition
typedef enum Cache_Mar {
Cache_Mar_DISABLE,
// The Permit Copy bit of MAR register is disabled
Cache_Mar_ENABLE
// The Permit Copy bit of MAR register is enabled
} Cache_Mar;
enum Cache_Mode |
|
Lists of cache modes for L1/L2 caches
typedef enum Cache_Mode {
Cache_Mode_FREEZE,
// No new cache lines are allocated
Cache_Mode_BYPASS,
// All access result in long-distance access
Cache_Mode_NORMAL
// Normal operation of cache
} Cache_Mode;
enum Cache_Type |
|
Lists of bitmask cache types
typedef enum Cache_Type {
Cache_Type_L1P,
// Level 1 Program cache
Cache_Type_L1D,
// Level 1 Data cache
Cache_Type_L1,
// Level 1 caches
Cache_Type_L2P,
// Level 2 Program cache
Cache_Type_L2D,
// Level 2 Data cache
Cache_Type_L2,
// Level 2 caches
Cache_Type_ALLP,
// All Program caches
Cache_Type_ALLD,
// All Data caches
Cache_Type_ALL
// All caches
} Cache_Type;
struct Cache_Size |
|
Structure for specifying all cache sizes
typedef struct Cache_Size {
// L1 Program cache size
// L1 Data data size
// L2 cache size
} Cache_Size;
config Cache_EMIFA_BASE // module-wide |
|
EMIF A base register address
extern const UInt Cache_EMIFA_BASE;
DETAILS
By default, this is set to the emif A base register physical address.
On devices with a MMU where the physical address is mapped to a virtual
address, the virtual address must be specified here.
config Cache_EMIFA_CFG // module-wide |
|
EMIF A configuration address
extern const UInt *Cache_EMIFA_CFG;
DETAILS
By default, this is set to the physical address. On devices with
a MMU where the physical address is mapped to a virtual address,
the virtual address must be specified here.
config Cache_EMIFA_LENGTH // module-wide |
|
EMIF A address space length
extern const UInt Cache_EMIFA_LENGTH;
config Cache_EMIFB_BASE // module-wide |
|
EMIF B base register address
extern const UInt Cache_EMIFB_BASE;
DETAILS
By default, this is set to the emif B base register physical address.
On devices with a MMU where the physical address is mapped to a virtual
address, the virtual address must be specified here.
config Cache_EMIFB_CFG // module-wide |
|
EMIF B configuration address
extern const UInt *Cache_EMIFB_CFG;
DETAILS
By default, this is set to the physical address. On devices with
a MMU where the physical address is mapped to a virtual address,
the virtual address must be specified here.
config Cache_EMIFB_LENGTH // module-wide |
|
EMIF B address space length
extern const UInt Cache_EMIFB_LENGTH;
config Cache_EMIFC_BASE // module-wide |
|
EMIF C base register address
extern const UInt Cache_EMIFC_BASE;
DETAILS
By default, this is set to the emif C base register physical address.
On devices with a MMU where the physical address is mapped to a virtual
address, the virtual address must be specified here.
config Cache_EMIFC_CFG // module-wide |
|
EMIF C configuration address
extern const UInt *Cache_EMIFC_CFG;
DETAILS
By default, this is set to the physical address. On devices with
a MMU where the physical address is mapped to a virtual address,
the virtual address must be specified here.
config Cache_EMIFC_LENGTH // module-wide |
|
EMIF C address space length
extern const UInt Cache_EMIFC_LENGTH;
config Cache_MAR0_31 // module-wide |
|
MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
extern const UInt32 Cache_MAR0_31;
DETAILS
If undefined by the user, this parameter is configured to match the
memory map of the platform.
Each memory region defined in the platform will have all of its
corresponding MAR bits set.
To override the default behavior you must initialize this parameter
in your configuration script:
// disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
Cache.MAR0_31 = 0x00000000;
config Cache_MAR128_159 // module-wide |
|
MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
extern const UInt32 Cache_MAR128_159;
DETAILS
see
MAR0_31 for more info
config Cache_MAR160_191 // module-wide |
|
MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
extern const UInt32 Cache_MAR160_191;
DETAILS
see
MAR0_31 for more info
config Cache_MAR192_223 // module-wide |
|
MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
extern const UInt32 Cache_MAR192_223;
DETAILS
see
MAR0_31 for more info
config Cache_MAR224_255 // module-wide |
|
MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
extern const UInt32 Cache_MAR224_255;
DETAILS
see
MAR0_31 for more info
config Cache_MAR32_63 // module-wide |
|
MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
extern const UInt32 Cache_MAR32_63;
DETAILS
see
MAR0_31 for more info
config Cache_MAR64_95 // module-wide |
|
MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
extern const UInt32 Cache_MAR64_95;
DETAILS
see
MAR0_31 for more info
config Cache_MAR96_127 // module-wide |
|
MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
extern const UInt32 Cache_MAR96_127;
DETAILS
see
MAR0_31 for more info
config Cache_initSize // module-wide |
|
Cache sizes
DETAILS
When this parameter is set in user's cfg script, user set cache sizes
override those specified by the Cache module or the platform.
Cache_disable() // module-wide |
|
Disables the 'type' cache(s)
Void Cache_disable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
DETAILS
Disabling of L2 cache is currently not supported.
Cache_enable() // module-wide |
|
Enables all cache(s)
Void Cache_enable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
Cache_getMar() // module-wide |
|
Get the value of the MAR register defined for the specified
base address
ARGUMENTS
baseAddr
address for which MAR is requested
RETURNS
value of MAR register associated with specified address
Cache_getMode() // module-wide |
|
Get mode of a cache
ARGUMENTS
type
bit mask of cache type
RETURNS
mode of specified level of cache
Cache_getSize() // module-wide |
|
Get sizes of all caches
ARGUMENTS
size
pointer to structure of type Cache_Size
Cache_inv() // module-wide |
|
Invalidate the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
in range are invalidated for all the 'type' caches
Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_invL1pAll() // module-wide |
|
Invalidate all of L1 Program cache
DETAILS
Performs a global invalidate of L1P cache.
Polls the L1P invalidate register until done.
Cache_setMar() // module-wide |
|
Set the MAR register(s) that corresponds to the specified
address range
Void Cache_setMar(
Ptr baseAddr,
SizeT byteSize,
Cache_Mar value);
ARGUMENTS
baseAddr
start address for which to set MAR
byteSize
size (in bytes) of memory block
value
enum of type Cache_Mar
Cache_setMode() // module-wide |
|
Set mode of a cache
ARGUMENTS
type
bit mask of cache type
mode
mode of cache
RETURNS
previous mode of cache
Cache_setSize() // module-wide |
|
Set sizes of all caches
ARGUMENTS
size
pointer to structure of type Cache_Size
Cache_wait() // module-wide |
|
Wait for a previous cache operation to complete
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache
operation is not truly complete until it has worked its way
through all buffering and all memory writes have landed in the
source memory.
Cache_wb() // module-wide |
|
Writes back a range of memory from all cache(s)
Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
within the range are left valid in the 'type' caches and the data
within the range will be written back to the source memory.
Cache_wbAll() // module-wide |
|
Write back all caches
DETAILS
Perform a global write back. There is no effect on program cache.
All data cache lines are left valid.
Perform a global write back. There is no effect on L1P cache.
All cache lines are left valid in L1D cache and dirty lines in L1D cache
are written back to L2 or external. All cache lines are left valid in
L2 cache and dirty lines in L2 cache are written back to external.
This function does not wait for write back operation to perculate
through the whole memory system before returing. Call Cache_wait(),
after this function if necessary.
Cache_wbInv() // module-wide |
|
Writes back and invalidates the range of memory within the
specified starting address and byte count. The range of
addresses operated on gets quantized to whole cache lines in
each cache. All lines within the range are written back to the
source memory and then invalidated for all 'type' caches
Void Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_wbInvAll() // module-wide |
|
Write back invalidate all caches
DETAILS
Performs a global write back and invalidate. All cache lines
are written out to physical memory and then invalidated.
Performs a global write back and invalidate. All cache lines are
invalidated in L1P cache. All dirty cache lines are written back to L2
or external and then invalidated in L1D cache. All dirty cache lines
are written back to external and then invalidated in L2 cache.
This function does not wait for write back operation to perculate
through the whole memory system before returing. Call Cache_wait(),
after this function if necessary.
Cache_wbInvL1dAll() // module-wide |
|
Write back invalidate L1D cache
Void Cache_wbInvL1dAll();
DETAILS
Performs a global write back and invalidate of L1D cache.
All dirty cache lines are written back to L2 or
external and then invalidated in L1D cache.
This function does not wait for write back operation to perculate
through the whole memory system before returing. Call Cache_wait(),
after this function if necessary.
Cache_wbL1dAll() // module-wide |
|
Write back L1D cache
DETAILS
Perform a global write back of L1D cache. There is no effect on L1P
or L2 cache. All cache lines are left valid in L1D cache and the
dirty lines in L1D cache are written back to L2 or external.
This function does not wait for write back operation to perculate
through the whole memory system before returing. Call Cache_wait(),
after this function if necessary.
Module-Wide Built-Ins |
|
// Get this module's unique id
Bool Cache_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Cache_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Cache_Module_getMask();
// Returns the diagnostics mask for this module
Void Cache_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
enum Cache.L1Size |
|
Level 1 cache size type definition. Can be used for both L1D & L1P
values of type Cache.L1Size
const Cache.L1Size_0K;
// Amount of cache is 0K, Amount of SRAM is 32K
const Cache.L1Size_4K;
// Amount of cache is 4K, Amount of SRAM is 28K
const Cache.L1Size_8K;
// Amount of cache is 8K, Amount of SRAM is 24K
const Cache.L1Size_16K;
// Amount of cache is 16K, Amount of SRAM is 16K
const Cache.L1Size_32K;
// Amount of cache is 32K, Amount of SRAM is 0K
C SYNOPSIS
enum Cache.L2Size |
|
Level 2 cache size type definition
values of type Cache.L2Size
const Cache.L2Size_0K;
// L2 is all SRAM
const Cache.L2Size_32K;
// Amount of cache is 32K
const Cache.L2Size_64K;
// Amount of cache is 64K
const Cache.L2Size_128K;
// Amount of cache is 128K
const Cache.L2Size_256K;
// Amount of cache is 256K
const Cache.L2Size_512K;
// Amount of cache is 512K
const Cache.L2Size_1024K;
// Amount of cache is 1024K
C SYNOPSIS
enum Cache.Mar |
|
MAR register setting type definition
values of type Cache.Mar
const Cache.Mar_DISABLE;
// The Permit Copy bit of MAR register is disabled
const Cache.Mar_ENABLE;
// The Permit Copy bit of MAR register is enabled
C SYNOPSIS
enum Cache.Mode |
|
Lists of cache modes for L1/L2 caches
values of type Cache.Mode
const Cache.Mode_FREEZE;
// No new cache lines are allocated
const Cache.Mode_BYPASS;
// All access result in long-distance access
const Cache.Mode_NORMAL;
// Normal operation of cache
C SYNOPSIS
enum Cache.Type |
|
Lists of bitmask cache types
values of type Cache.Type
const Cache.Type_L1P;
// Level 1 Program cache
const Cache.Type_L1D;
// Level 1 Data cache
const Cache.Type_L1;
// Level 1 caches
const Cache.Type_L2P;
// Level 2 Program cache
const Cache.Type_L2D;
// Level 2 Data cache
const Cache.Type_L2;
// Level 2 caches
const Cache.Type_ALLP;
// All Program caches
const Cache.Type_ALLD;
// All Data caches
const Cache.Type_ALL;
// All caches
C SYNOPSIS
struct Cache.Size |
|
Structure for specifying all cache sizes
var obj = new Cache.Size;
// L1 Program cache size
// L1 Data data size
// L2 cache size
C SYNOPSIS
config Cache.EMIFA_BASE // module-wide |
|
EMIF A base register address
Cache.EMIFA_BASE = UInt undefined;
DETAILS
By default, this is set to the emif A base register physical address.
On devices with a MMU where the physical address is mapped to a virtual
address, the virtual address must be specified here.
C SYNOPSIS
config Cache.EMIFA_CFG // module-wide |
|
EMIF A configuration address
Cache.EMIFA_CFG = UInt* undefined;
DETAILS
By default, this is set to the physical address. On devices with
a MMU where the physical address is mapped to a virtual address,
the virtual address must be specified here.
C SYNOPSIS
config Cache.EMIFA_LENGTH // module-wide |
|
EMIF A address space length
Cache.EMIFA_LENGTH = UInt undefined;
C SYNOPSIS
config Cache.EMIFB_BASE // module-wide |
|
EMIF B base register address
Cache.EMIFB_BASE = UInt undefined;
DETAILS
By default, this is set to the emif B base register physical address.
On devices with a MMU where the physical address is mapped to a virtual
address, the virtual address must be specified here.
C SYNOPSIS
config Cache.EMIFB_CFG // module-wide |
|
EMIF B configuration address
Cache.EMIFB_CFG = UInt* undefined;
DETAILS
By default, this is set to the physical address. On devices with
a MMU where the physical address is mapped to a virtual address,
the virtual address must be specified here.
C SYNOPSIS
config Cache.EMIFB_LENGTH // module-wide |
|
EMIF B address space length
Cache.EMIFB_LENGTH = UInt undefined;
C SYNOPSIS
config Cache.EMIFC_BASE // module-wide |
|
EMIF C base register address
Cache.EMIFC_BASE = UInt undefined;
DETAILS
By default, this is set to the emif C base register physical address.
On devices with a MMU where the physical address is mapped to a virtual
address, the virtual address must be specified here.
C SYNOPSIS
config Cache.EMIFC_CFG // module-wide |
|
EMIF C configuration address
Cache.EMIFC_CFG = UInt* undefined;
DETAILS
By default, this is set to the physical address. On devices with
a MMU where the physical address is mapped to a virtual address,
the virtual address must be specified here.
C SYNOPSIS
config Cache.EMIFC_LENGTH // module-wide |
|
EMIF C address space length
Cache.EMIFC_LENGTH = UInt undefined;
C SYNOPSIS
config Cache.MAR0_31 // module-wide |
|
MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
Cache.MAR0_31 = UInt32 undefined;
DETAILS
If undefined by the user, this parameter is configured to match the
memory map of the platform.
Each memory region defined in the platform will have all of its
corresponding MAR bits set.
To override the default behavior you must initialize this parameter
in your configuration script:
// disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
Cache.MAR0_31 = 0x00000000;
C SYNOPSIS
config Cache.MAR128_159 // module-wide |
|
MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
Cache.MAR128_159 = UInt32 undefined;
DETAILS
see
MAR0_31 for more info
C SYNOPSIS
config Cache.MAR160_191 // module-wide |
|
MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
Cache.MAR160_191 = UInt32 undefined;
DETAILS
see
MAR0_31 for more info
C SYNOPSIS
config Cache.MAR192_223 // module-wide |
|
MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
Cache.MAR192_223 = UInt32 undefined;
DETAILS
see
MAR0_31 for more info
C SYNOPSIS
config Cache.MAR224_255 // module-wide |
|
MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
Cache.MAR224_255 = UInt32 undefined;
DETAILS
see
MAR0_31 for more info
C SYNOPSIS
config Cache.MAR32_63 // module-wide |
|
MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
Cache.MAR32_63 = UInt32 undefined;
DETAILS
see
MAR0_31 for more info
C SYNOPSIS
config Cache.MAR64_95 // module-wide |
|
MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
Cache.MAR64_95 = UInt32 undefined;
DETAILS
see
MAR0_31 for more info
C SYNOPSIS
config Cache.MAR96_127 // module-wide |
|
MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
Cache.MAR96_127 = UInt32 undefined;
DETAILS
see
MAR0_31 for more info
C SYNOPSIS
config Cache.initSize // module-wide |
|
Cache sizes
DETAILS
When this parameter is set in user's cfg script, user set cache sizes
override those specified by the Cache module or the platform.
C SYNOPSIS
metaonly config Cache.common$ // module-wide |
|
Common module configuration parameters
DETAILS
All modules have this configuration parameter. Its name
contains the '$' character to ensure it does not conflict with
configuration parameters declared by the module. This allows
new configuration parameters to be added in the future without
any chance of breaking existing modules.