111 #ifndef ti_drivers_UDMACC26XX__include
112 #define ti_drivers_UDMACC26XX__include
120 #include "driverlib/udma.h"
121 #include "inc/hw_types.h"
123 #include <ti/sysbios/family/arm/cc26xx/Power.h>
124 #include <ti/sysbios/family/arm/cc26xx/PowerCC2650.h>
127 #ifndef UDMACC26XX_CONFIG_BASE
128 #define UDMACC26XX_CONFIG_BASE 0x20000400
132 #if(UDMACC26XX_CONFIG_BASE & 0x3FF)
133 #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned."
137 #if defined(__IAR_SYSTEMS_ICC__)
138 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
139 __no_init static volatile tDMAControlTable ENTRY_NAME @ UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable)
140 #elif defined(__TI_COMPILER_VERSION__)
141 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
142 PRAGMA(LOCATION( ENTRY_NAME , UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) );)\
143 static volatile tDMAControlTable ENTRY_NAME
144 #define PRAGMA(x) _Pragma(#x)
145 #elif defined(__GNUC__)
146 #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
147 extern int UDMACC26XX_ ## ENTRY_NAME ## _is_placed; __attribute__ ((section("."#ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = {&UDMACC26XX_ ## ENTRY_NAME ## _is_placed}
149 #error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain"
153 #define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M)
155 #define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1)
162 ti_sysbios_family_arm_m3_Hwi_Struct
hwi;
234 object->isOpen = FALSE;
275 HWREG(hwAttrs->
baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask;
304 return (uDMAIntStatus(hwAttrs->
baseAddr) & channelBitMask) ?
true :
false;
332 uDMAIntClear(hwAttrs->
baseAddr, channelBitMask);
360 uDMAChannelDisable(hwAttrs->
baseAddr, channelBitMask);
bool isOpen
Definition: UDMACC26XX.h:161
void UDMACC26XX_close(UDMACC26XX_Handle handle)
Function to close the DMA driver.
__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:324
__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:267
uint8_t intNum
Definition: UDMACC26XX.h:171
__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
Function to initialize the CC26XX DMA driver.
Definition: UDMACC26XX.h:226
UDMACC26XX Global configuration.
Definition: UDMACC26XX.h:201
ti_sysbios_family_arm_m3_Hwi_Struct hwi
Definition: UDMACC26XX.h:162
struct UDMACC26XX_Object UDMACC26XX_Object
UDMACC26XX object.
Power_Resource powerMngrId
Definition: UDMACC26XX.h:170
UDMACC26XX_Handle UDMACC26XX_open()
Function to initialize the CC26XX DMA peripheral.
struct UDMACC26XX_Config UDMACC26XX_Config
UDMACC26XX Global configuration.
UDMACC26XX hardware attributes.
Definition: UDMACC26XX.h:168
void * object
Definition: UDMACC26XX.h:202
uint8_t intPriority
UDMACC26XX error interrupt priority. intPriority is the DMA peripheral's interrupt priority...
Definition: UDMACC26XX.h:195
__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:352
__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
Definition: UDMACC26XX.h:296
uint32_t baseAddr
Definition: UDMACC26XX.h:169
void UDMACC26XX_hwiIntFxn(UArg callbacks)
UDMACC26XX object.
Definition: UDMACC26XX.h:160
struct UDMACC26XX_Config * UDMACC26XX_Handle
A handle that is returned from a UDMACC26XX_open() call.
Definition: UDMACC26XX.h:209
void const * hwAttrs
Definition: UDMACC26XX.h:203
struct UDMACC26XX_HWAttrs UDMACC26XX_HWAttrs
UDMACC26XX hardware attributes.