Instance: FCFG1
Component: FCFG1
Base address: 0x50001000
Factory configuration area (FCFG1)
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0xFFFF FFXX |
0x0000 00A0 |
0x5000 10A0 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 00B0 |
0x5000 10B0 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 00B4 |
0x5000 10B4 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 00B8 |
0x5000 10B8 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 00BC |
0x5000 10BC |
|
RO |
32 |
0xXXXX XXXX |
0x0000 00C0 |
0x5000 10C0 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00C4 |
0x5000 10C4 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00C8 |
0x5000 10C8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00CC |
0x5000 10CC |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00D0 |
0x5000 10D0 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00D4 |
0x5000 10D4 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00D8 |
0x5000 10D8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00DC |
0x5000 10DC |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00E0 |
0x5000 10E0 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00E4 |
0x5000 10E4 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00E8 |
0x5000 10E8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00EC |
0x5000 10EC |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00F0 |
0x5000 10F0 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00F4 |
0x5000 10F4 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00F8 |
0x5000 10F8 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 00FC |
0x5000 10FC |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0100 |
0x5000 1100 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0104 |
0x5000 1104 |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0108 |
0x5000 1108 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0118 |
0x5000 1118 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 011C |
0x5000 111C |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0120 |
0x5000 1120 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0124 |
0x5000 1124 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0138 |
0x5000 1138 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 013C |
0x5000 113C |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0164 |
0x5000 1164 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 016C |
0x5000 116C |
|
RO |
32 |
0x1733 1A33 |
0x0000 0170 |
0x5000 1170 |
|
RO |
32 |
0x0A0A 2000 |
0x0000 0174 |
0x5000 1174 |
|
RO |
32 |
0x026E 0200 |
0x0000 0178 |
0x5000 1178 |
|
RO |
32 |
0x0200 F000 |
0x0000 017C |
0x5000 117C |
|
RO |
32 |
0x0000 0001 |
0x0000 0180 |
0x5000 1180 |
|
RO |
32 |
0x00XX 0014 |
0x0000 0184 |
0x5000 1184 |
|
RO |
32 |
0x0FA0 0010 |
0x0000 0188 |
0x5000 1188 |
|
RO |
32 |
0x0000 0FA0 |
0x0000 018C |
0x5000 118C |
|
RO |
32 |
0x0X0X 0X04 |
0x0000 0190 |
0x5000 1190 |
|
RO |
32 |
0x0X08 XX01 |
0x0000 0194 |
0x5000 1194 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0198 |
0x5000 1198 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0294 |
0x5000 1294 |
|
RO |
32 |
0x0011 XX03 |
0x0000 02B0 |
0x5000 12B0 |
|
RO |
32 |
0b1XXX XX10 01XX XXXX 1111 0100 0111 1111 |
0x0000 02B4 |
0x5000 12B4 |
|
RO |
32 |
0b111X XXXX 1111 1000 1110 0000 1111 1011 |
0x0000 02B8 |
0x5000 12B8 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 02E8 |
0x5000 12E8 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 02EC |
0x5000 12EC |
|
RO |
32 |
0xXXXX XXXX |
0x0000 02F0 |
0x5000 12F0 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 02F4 |
0x5000 12F4 |
|
RO |
32 |
0x9898 9F9F |
0x0000 0308 |
0x5000 1308 |
|
RO |
32 |
0xFFFF FF33 |
0x0000 030C |
0x5000 130C |
|
RO |
32 |
0x0000 0003 |
0x0000 0310 |
0x5000 1310 |
|
RO |
32 |
0x8B99 A02F |
0x0000 0318 |
0x5000 1318 |
|
RO |
32 |
0x0000 0023 |
0x0000 031C |
0x5000 131C |
|
RO |
32 |
0x0000 C6XX |
0x0000 0320 |
0x5000 1320 |
|
RO |
32 |
0b1111 1111 1111 1111 1XXX XXXX 0XXX XXXX |
0x0000 0344 |
0x5000 1344 |
|
RO |
32 |
0b0011 0100 0110 0000 1111 01XX XXXX XXXX |
0x0000 034C |
0x5000 134C |
|
RO |
32 |
0b1111 1100 0000 0000 1111 11XX XXXX XX00 |
0x0000 0350 |
0x5000 1350 |
|
RO |
32 |
0b0111 XXXX 0000 0XXX XXX1 1111 1XXX XXXX |
0x0000 0354 |
0x5000 1354 |
|
RO |
32 |
0xFFFF FXXX |
0x0000 0358 |
0x5000 1358 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 035C |
0x5000 135C |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0360 |
0x5000 1360 |
|
RO |
32 |
0xXXXX XXXX |
0x0000 0368 |
0x5000 1368 |
|
RO |
32 |
0bXXXX XXXX XX11 XXXX XXXX XXXX 10XX XXXX |
0x0000 036C |
0x5000 136C |
|
RO |
32 |
0xFF7B 828E |
0x0000 0370 |
0x5000 1370 |
|
RO |
32 |
0x6B8B 0303 |
0x0000 0374 |
0x5000 1374 |
|
RO |
32 |
0xFF18 3F47 |
0x0000 0378 |
0x5000 1378 |
|
RO |
32 |
0xFFFF C3FF |
0x0000 037C |
0x5000 137C |
|
RO |
32 |
0b1111 1111 1111 11XX XXXX XXX1 0100 1101 |
0x0000 0380 |
0x5000 1380 |
|
RO |
32 |
0b1111 1111 1111 1111 1111 1111 111X XXXX |
0x0000 0388 |
0x5000 1388 |
|
RO |
32 |
0b1111 0000 0000 1XXX XXXX XXXX XXXX XXXX |
0x0000 038C |
0x5000 138C |
|
RO |
32 |
0xFFFF FFFF |
0x0000 0394 |
0x5000 1394 |
|
RO |
32 |
0xE004 03F8 |
0x0000 0398 |
0x5000 1398 |
|
RO |
32 |
0x080B A608 |
0x0000 039C |
0x5000 139C |
|
RO |
32 |
0x0C10 A50A |
0x0000 03A0 |
0x5000 13A0 |
|
RO |
32 |
0x1218 A20D |
0x0000 03A4 |
0x5000 13A4 |
|
RO |
32 |
0x1C25 9C14 |
0x0000 03A8 |
0x5000 13A8 |
|
RO |
32 |
0x2E3B 9021 |
0x0000 03AC |
0x5000 13AC |
|
RO |
32 |
0x4C62 7A3B |
0x0000 03B0 |
0x5000 13B0 |
|
RO |
32 |
0x789E 706B |
0x0000 03B4 |
0x5000 13B4 |
|
RO |
32 |
0xADE1 809A |
0x0000 03B8 |
0x5000 13B8 |
Address Offset | 0x0000 00A0 | ||
Physical Address | 0x5000 10A0 | Instance | 0x5000 10A0 |
Description | Misc configurations | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF FFFF | ||
7:0 | DEVICE_MINOR_REV | HW minor revision number (a value of 0xFF shall be treated equally to 0x00). Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer. Value may change without warning. |
RO | 0xXX |
Address Offset | 0x0000 00B0 | ||
Physical Address | 0x5000 10B0 | Instance | 0x5000 10B0 |
Description | |||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | BAW_D5 | Insertion 5 BAW delta frequency: D = round((f/48e6-1)*2^22) Default value holds log information from production test. |
RO | 0xXXXX | ||
15:8 | BAW_T5 | Insertion 5 BAW temp sensor readout, in degrees C, relative to 27C: T = round(t-27) Default value holds log information from production test. |
RO | 0xXX | ||
7:0 | BAW_DT5 | Insertion 5 BAW delta T readout over VDDS, in 0.25 degrees C steps: DT = round ((4*(t at VDDS=3.8V))-round((4*(t at VDDS=1.8V)) Default value holds log information from production test. |
RO | 0xXX |
Address Offset | 0x0000 00B4 | ||
Physical Address | 0x5000 10B4 | Instance | 0x5000 10B4 |
Description | |||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | BAW_D4 | Insertion 4 BAW delta frequency: D = round((f/48e6-1)*2^22) Default value holds log information from production test. |
RO | 0xXXXX | ||
15:8 | BAW_T4 | Insertion 4 BAW temp sensor readout, in degrees C, relative to 27C: T = round(t-27) Default value holds log information from production test. |
RO | 0xXX | ||
7:0 | BAW_DT4 | Insertion 4 BAW delta T readout over VDDS, in 0.25 degrees C steps: DT = round ((4*(t at VDDS=3.8V))-round((4*(t at VDDS=1.8V)) Default value holds log information from production test. |
RO | 0xXX |
Address Offset | 0x0000 00B8 | ||
Physical Address | 0x5000 10B8 | Instance | 0x5000 10B8 |
Description | |||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | BAW_D3 | Insertion 3 BAW delta frequency: D = round((f/48e6-1)*2^22) Default value holds log information from production test. |
RO | 0xXXXX | ||
15:8 | BAW_T3 | Insertion 3 BAW temp sensor readout, in degrees C, relative to 27C: T = round(t-27) Default value holds log information from production test. |
RO | 0xXX | ||
7:0 | BAW_DT3 | Insertion 3 BAW delta T readout over VDDS, in 0.25 degrees C steps: DT = round ((4*(t at VDDS=3.8V))-round((4*(t at VDDS=1.8V)) Default value holds log information from production test. |
RO | 0xXX |
Address Offset | 0x0000 00BC | ||
Physical Address | 0x5000 10BC | Instance | 0x5000 10BC |
Description | |||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | BAW_D2 | Insertion 2 BAW delta frequency: D = round((f/48e6-1)*2^22) Default value holds log information from production test. |
RO | 0xXXXX | ||
15:8 | BAW_T2 | Insertion 2 BAW temp sensor readout, in degrees C, relative to 27C: T = round(t-27) Default value holds log information from production test. |
RO | 0xXX | ||
7:0 | BAW_DT2 | Insertion 2 BAW delta T readout over VDDS, in 0.25 degrees C steps: DT = round ((4*(t at VDDS=3.8V))-round((4*(t at VDDS=1.8V)) Default value holds log information from production test. |
RO | 0xXX |
Address Offset | 0x0000 00C0 | ||
Physical Address | 0x5000 10C0 | Instance | 0x5000 10C0 |
Description | |||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | BAW_D1 | Insertion 1 BAW delta frequency: D = round((f/48e6-1)*2^22) Default value holds log information from production test. |
RO | 0xXXXX | ||
15:8 | BAW_T1 | Insertion 1 BAW temp sensor readout, in degrees C, relative to 27C: T = round(t-27) Default value holds log information from production test. |
RO | 0xXX | ||
7:0 | BAW_DT1 | Insertion 1 BAW delta T readout over VDDS, in 0.25 degrees C steps: DT = round ((4*(t at VDDS=3.8V))-round((4*(t at VDDS=1.8V)) Default value holds log information from production test. |
RO | 0xXX |
Address Offset | 0x0000 00C4 | ||
Physical Address | 0x5000 10C4 | Instance | 0x5000 10C4 |
Description | Configuration of RF Frontend in Divide-by-5 Mode Divide-by-5 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | IFAMP_IB | Trim value used for ADI_0_RF:IFAMPCTL3.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
27:24 | LNA_IB | Trim value for ADI_0_RF:LNACTL2.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
23:19 | IFAMP_TRIM | Trim value for ADI_0_RF:IFAMPCTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
18:14 | CTL_PA0_TRIM | Trim value for ADI_0_RF:PACTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
13:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
6:0 | RFLDO_TRIM_OUTPUT | Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 1111 |
Address Offset | 0x0000 00C8 | ||
Physical Address | 0x5000 10C8 | Instance | 0x5000 10C8 |
Description | Configuration of RF Frontend in Divide-by-6 Mode Divide-by-6 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | IFAMP_IB | Trim value used for ADI_0_RF:IFAMPCTL3.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
27:24 | LNA_IB | Trim value for ADI_0_RF:LNACTL2.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
23:19 | IFAMP_TRIM | Trim value for ADI_0_RF:IFAMPCTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
18:14 | CTL_PA0_TRIM | Trim value for ADI_0_RF:PACTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
13:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
6:0 | RFLDO_TRIM_OUTPUT | Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 1111 |
Address Offset | 0x0000 00CC | ||
Physical Address | 0x5000 10CC | Instance | 0x5000 10CC |
Description | Configuration of RF Frontend in Divide-by-10 Mode Divide-by-10 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | IFAMP_IB | Trim value used for ADI_0_RF:IFAMPCTL3.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
27:24 | LNA_IB | Trim value for ADI_0_RF:LNACTL2.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
23:19 | IFAMP_TRIM | Trim value for ADI_0_RF:IFAMPCTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
18:14 | CTL_PA0_TRIM | Trim value for ADI_0_RF:PACTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
13:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
6:0 | RFLDO_TRIM_OUTPUT | Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 1111 |
Address Offset | 0x0000 00D0 | ||
Physical Address | 0x5000 10D0 | Instance | 0x5000 10D0 |
Description | Configuration of RF Frontend in Divide-by-12 Mode Divide-by-12 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | IFAMP_IB | Trim value used for ADI_0_RF:IFAMPCTL3.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
27:24 | LNA_IB | Trim value for ADI_0_RF:LNACTL2.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
23:19 | IFAMP_TRIM | Trim value for ADI_0_RF:IFAMPCTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
18:14 | CTL_PA0_TRIM | Trim value for ADI_0_RF:PACTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
13:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
6:0 | RFLDO_TRIM_OUTPUT | Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 1111 |
Address Offset | 0x0000 00D4 | ||
Physical Address | 0x5000 10D4 | Instance | 0x5000 10D4 |
Description | Configuration of RF Frontend in Divide-by-15 Mode Divide-by-15 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | IFAMP_IB | Trim value used for ADI_0_RF:IFAMPCTL3.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
27:24 | LNA_IB | Trim value for ADI_0_RF:LNACTL2.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
23:19 | IFAMP_TRIM | Trim value for ADI_0_RF:IFAMPCTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
18:14 | CTL_PA0_TRIM | Trim value for ADI_0_RF:PACTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
13:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
6:0 | RFLDO_TRIM_OUTPUT | Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 1111 |
Address Offset | 0x0000 00D8 | ||
Physical Address | 0x5000 10D8 | Instance | 0x5000 10D8 |
Description | Configuration of RF Frontend in Divide-by-30 Mode Divide-by-30 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | IFAMP_IB | Trim value used for ADI_0_RF:IFAMPCTL3.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
27:24 | LNA_IB | Trim value for ADI_0_RF:LNACTL2.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xF | ||
23:19 | IFAMP_TRIM | Trim value for ADI_0_RF:IFAMPCTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
18:14 | CTL_PA0_TRIM | Trim value for ADI_0_RF:PACTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b1 1111 | ||
13:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 | ||
6:0 | RFLDO_TRIM_OUTPUT | Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 1111 |
Address Offset | 0x0000 00DC | ||
Physical Address | 0x5000 10DC | Instance | 0x5000 10DC |
Description | Configuration of Synthesizer in Divide-by-5 Mode Divide-by-5 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
27:12 | RFC_MDM_DEMIQMC0 | Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFFFF | ||
11:6 | LDOVCO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 | ||
5:0 | SLDO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 00E0 | ||
Physical Address | 0x5000 10E0 | Instance | 0x5000 10E0 |
Description | Configuration of Synthesizer in Divide-by-6 Mode Divide-by-6 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
27:12 | RFC_MDM_DEMIQMC0 | Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFFFF | ||
11:6 | LDOVCO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 | ||
5:0 | SLDO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 00E4 | ||
Physical Address | 0x5000 10E4 | Instance | 0x5000 10E4 |
Description | Configuration of Synthesizer in Divide-by-10 Mode Divide-by-10 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
27:12 | RFC_MDM_DEMIQMC0 | Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFFFF | ||
11:6 | LDOVCO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 | ||
5:0 | SLDO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 00E8 | ||
Physical Address | 0x5000 10E8 | Instance | 0x5000 10E8 |
Description | Configuration of Synthesizer in Divide-by-12 Mode Divide-by-12 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
27:12 | RFC_MDM_DEMIQMC0 | Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFFFF | ||
11:6 | LDOVCO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 | ||
5:0 | SLDO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 00EC | ||
Physical Address | 0x5000 10EC | Instance | 0x5000 10EC |
Description | Configuration of Synthesizer in Divide-by-15 Mode Divide-by-15 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
27:12 | RFC_MDM_DEMIQMC0 | Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFFFF | ||
11:6 | LDOVCO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 | ||
5:0 | SLDO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 00F0 | ||
Physical Address | 0x5000 10F0 | Instance | 0x5000 10F0 |
Description | Configuration of Synthesizer in Divide-by-30 Mode Divide-by-30 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
27:12 | RFC_MDM_DEMIQMC0 | Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFFFF | ||
11:6 | LDOVCO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 | ||
5:0 | SLDO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 00F4 | ||
Physical Address | 0x5000 10F4 | Instance | 0x5000 10F4 |
Description | Configuration of IFADC in Divide-by-5 Mode Divide-by-5 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 | ||
16:9 | RSSI_OFFSET | Value for RSSI measured in production test. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFF | ||
8:6 | QUANTCTLTHRES | Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 | ||
5:0 | DACTRIM | Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 00F8 | ||
Physical Address | 0x5000 10F8 | Instance | 0x5000 10F8 |
Description | Configuration of IFADC in Divide-by-6 Mode Divide-by-6 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 | ||
16:9 | RSSI_OFFSET | Value for RSSI measured in production test. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFF | ||
8:6 | QUANTCTLTHRES | Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 | ||
5:0 | DACTRIM | Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 00FC | ||
Physical Address | 0x5000 10FC | Instance | 0x5000 10FC |
Description | Configuration of IFADC in Divide-by-10 Mode Divide-by-10 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 | ||
16:9 | RSSI_OFFSET | Value for RSSI measured in production test. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFF | ||
8:6 | QUANTCTLTHRES | Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 | ||
5:0 | DACTRIM | Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x5000 1100 | Instance | 0x5000 1100 |
Description | Configuration of IFADC in Divide-by-12 Mode Divide-by-12 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 | ||
16:9 | RSSI_OFFSET | Value for RSSI measured in production test. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFF | ||
8:6 | QUANTCTLTHRES | Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 | ||
5:0 | DACTRIM | Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x5000 1104 | Instance | 0x5000 1104 |
Description | Configuration of IFADC in Divide-by-15 Mode Divide-by-15 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 | ||
16:9 | RSSI_OFFSET | Value for RSSI measured in production test. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFF | ||
8:6 | QUANTCTLTHRES | Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 | ||
5:0 | DACTRIM | Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x5000 1108 | Instance | 0x5000 1108 |
Description | Configuration of IFADC in Divide-by-30 Mode Divide-by-30 mode is only available for CC13xx. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:17 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 1111 1111 1111 | ||
16:9 | RSSI_OFFSET | Value for RSSI measured in production test. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xFF | ||
8:6 | QUANTCTLTHRES | Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b111 | ||
5:0 | DACTRIM | Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 1111 |
Address Offset | 0x0000 0118 | ||
Physical Address | 0x5000 1118 | Instance | 0x5000 1118 |
Description | Shadow of EFUSE:DIE_ID_0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ID_31_0 | Shadow of EFUSE:DIE_ID_0, ie efuse row number 3 Default value depends on eFuse value. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 011C | ||
Physical Address | 0x5000 111C | Instance | 0x5000 111C |
Description | Shadow of EFUSE:DIE_ID_1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ID_63_32 | Shadow of EFUSE:DIE_ID_1, ie efuse row number 4 Default value depends on eFuse value. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 0120 | ||
Physical Address | 0x5000 1120 | Instance | 0x5000 1120 |
Description | Shadow of EFUSE:DIE_ID_2 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ID_95_64 | Shadow of EFUSE:DIE_ID_2, ie efuse row number 5 Default value depends on eFuse value. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 0124 | ||
Physical Address | 0x5000 1124 | Instance | 0x5000 1124 |
Description | Shadow of EFUSE:DIE_ID_3 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ID_127_96 | Shadow of EFUSE:DIE_ID_3, ie efuse row number 6 Default value depends on eFuse value. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 0138 | ||
Physical Address | 0x5000 1138 | Instance | 0x5000 1138 |
Description | Shadow of EFUSE:OSC_BIAS_LDO_TRIM | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:29 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value depends on eFuse value. |
RO | 0xX | ||
28:27 | SET_RCOSC_HF_COARSE_RESISTOR | Shadow of EFUSE:OSC_BIAS_LDO_TRIM.SET_RCOSC_HF_COARSE_RESISTOR, ie in efuse row number 11 Default value depends on eFuse value. |
RO | 0xX | ||
26:23 | TRIMMAG | Shadow of EFUSE:OSC_BIAS_LDO_TRIM.TRIMMAG, ie in efuse row number 11 Default value depends on eFuse value. |
RO | 0xX | ||
22:18 | TRIMIREF | Shadow of EFUSE:OSC_BIAS_LDO_TRIM.TRIMIREF, ie in efuse row number 11 Default value depends on eFuse value. |
RO | 0xXX | ||
17:16 | ITRIM_DIG_LDO | Shadow of EFUSE:OSC_BIAS_LDO_TRIM.ITRIM_DIG_LDO, ie in efuse row number 11 Default value depends on eFuse value. |
RO | 0xX | ||
15:12 | VTRIM_DIG | Shadow of EFUSE:OSC_BIAS_LDO_TRIM.VTRIM_DIG, ie in efuse row number 11 Default value depends on eFuse value. |
RO | 0xX | ||
11:8 | VTRIM_COARSE | Shadow of EFUSE:OSC_BIAS_LDO_TRIM.VTRIM_COARSE, ie in efuse row number 11 Default value depends on eFuse value. |
RO | 0xX | ||
7:0 | RCOSCHF_CTRIM | Shadow of EFUSE:OSC_BIAS_LDO_TRIM.RCOSCHF_CTRIM, ie in efuse row number 11 Default value depends on eFuse value. |
RO | 0xXX |
Address Offset | 0x0000 013C | ||
Physical Address | 0x5000 113C | Instance | 0x5000 113C |
Description | Shadow of EFUSE:ANA_TRIM | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:27 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value depends on eFuse value. |
RO | 0xXX | ||
26:25 | BOD_BANDGAP_TRIM_CNF | Shadow of EFUSE:ANA_TRIM.BOD_BANDGAP_TRIM_CNF, ie in efuse row number 12 Default value depends on eFuse value. |
RO | 0xX | ||
24 | VDDR_ENABLE_PG1 | Shadow of EFUSE:ANA_TRIM.VDDR_ENABLE_PG1, ie in efuse row number 12 Default value depends on eFuse value. |
RO | X | ||
23 | VDDR_OK_HYS | Shadow of EFUSE:ANA_TRIM.VDDR_OK_HYS, ie in efuse row number 12 Default value depends on eFuse value. |
RO | X | ||
22:21 | IPTAT_TRIM | Shadow of EFUSE:ANA_TRIM.IPTAT_TRIM, ie in efuse row number 12 Default value depends on eFuse value. |
RO | 0xX | ||
20:16 | VDDR_TRIM | Shadow of EFUSE:ANA_TRIM.VDDR_TRIM, ie in efuse row number 12 Default value depends on eFuse value. |
RO | 0xXX | ||
15:11 | TRIMBOD_INTMODE | Shadow of EFUSE:ANA_TRIM.TRIMBOD_INTMODE, ie in efuse row number 12 Default value depends on eFuse value. |
RO | 0xXX | ||
10:6 | TRIMBOD_EXTMODE | Shadow of EFUSE:ANA_TRIM.TRIMBOD_EXTMODE, ie in efuse row number 12 Default value depends on eFuse value. |
RO | 0xXX | ||
5:0 | TRIMTEMP | Shadow of EFUSE:ANA_TRIM.TRIMTEMP, ie in efuse row number 12 Default value depends on eFuse value. |
RO | 0xXX |
Address Offset | 0x0000 0164 | ||
Physical Address | 0x5000 1164 | Instance | 0x5000 1164 |
Description | |||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | LOT_NUMBER | Number of the manufacturing lot that produced this unit. Default value holds log information from production test. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 016C | ||
Physical Address | 0x5000 116C | Instance | 0x5000 116C |
Description | |||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | XCOORDINATE | X coordinate of this unit on the wafer. Default value holds log information from production test. |
RO | 0xXXXX | ||
15:0 | YCOORDINATE | Y coordinate of this unit on the wafer. Default value holds log information from production test. |
RO | 0xXXXX |
Address Offset | 0x0000 0170 | ||
Physical Address | 0x5000 1170 | Instance | 0x5000 1170 |
Description | Flash Erase and Program Setup Time | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | PSU | Program setup time in cycles. Value will be written to FLASH:FSM_PE_OSU.PGM_OSU by the flash device driver when an erase/program operation is initiated. | RO | 0x17 | ||
23:16 | ESU | Erase setup time in cycles. Value will be written to FLASH:FSM_PE_OSU.ERA_OSU by the flash device driver when an erase/program operation is initiated. | RO | 0x33 | ||
15:8 | PVSU | Program verify setup time in cycles. Value will be written to FLASH:FSM_PE_VSU.PGM_VSU by the flash device driver when an erase/program operation is initiated. | RO | 0x1A | ||
7:0 | EVSU | Erase verify setup time in cycles. Value will be written to FLASH:FSM_PE_VSU.ERA_VSU by the flash device driver when an erase/program operation is initiated. | RO | 0x33 |
Address Offset | 0x0000 0174 | ||
Physical Address | 0x5000 1174 | Instance | 0x5000 1174 |
Description | Flash Compaction, Execute, Program and Read | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RVSU | Repeat verify setup time in cycles. Used for repeated verifies during program and erase. Value will be written to FLASH:FSM_EX_VAL.REP_VSU by the flash device driver when an erase/program operation is initiated. | RO | 0x0A | ||
23:16 | PV_ACCESS | Program verify EXECUTEZ->data valid time in half-microseconds. Value will be converted to number of FCLK cycles by by flash device driver and the converted value is written to FLASH:FSM_EX_VAL.EXE_VALD when an erase/program operation is initiated.. | RO | 0x0A | ||
15:12 | A_EXEZ_SETUP | Address->EXECUTEZ setup time in cycles. Value will be written to FLASH:FSM_CMP_VSU.ADD_EXZ by the flash device driver when an erase/program operation is initiated.. | RO | 0x2 | ||
11:0 | CVSU | Compaction verify setup time in cycles. | RO | 0x000 |
Address Offset | 0x0000 0178 | ||
Physical Address | 0x5000 1178 | Instance | 0x5000 1178 |
Description | Flash Program, Read, and Program Verify | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | PH | Program hold time in half-microseconds after SAFELV goes low. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_P_OH.PGM_OH when an erase/program operation is initiated. | RO | 0x02 | ||
23:16 | RH | Read hold/mode transition time in cycles. Value will be written to the RD_H field bits[7:0] of the FSM_RD_H register in the flash module by the flash device driver when an erase/program operation is initiated. | RO | 0x6E | ||
15:8 | PVH | Program verify hold time in half-microseconds after SAFELV goes low. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_PE_VH.PGM_VH when an erase/program operation is initiated. | RO | 0x02 | ||
7:0 | PVH2 | Program verify row switch time in half-microseconds. | RO | 0x00 |
Address Offset | 0x0000 017C | ||
Physical Address | 0x5000 117C | Instance | 0x5000 117C |
Description | Flash Erase Hold and Sequence | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | EH | Erase hold time in half-microseconds after SAFELV goes low. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_ERA_OH.ERA_OH when an erase/program operation is initiated. | RO | 0x02 | ||
23:16 | SEQ | Pump sequence control. | RO | 0x00 | ||
15:12 | VSTAT | Max number of HCLK cycles allowed for pump brown-out. Value will be written to FLASH:FSM_VSTAT.VSTAT_CNT when an erase/program operation is initiated. | RO | 0xF | ||
11:0 | SM_FREQUENCY | Max FCLK frequency allowed for program, erase, and verify reads. | RO | 0x000 |
Address Offset | 0x0000 0180 | ||
Physical Address | 0x5000 1180 | Instance | 0x5000 1180 |
Description | Flash VHV Erase | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | VHV_E_START | Starting VHV-Erase CT for stairstep erase. Value will be written to FLASH:FSM_PRG_PUL.BEG_EC_LEVEL when an erase/program operation is initiated. | RO | 0x0000 | ||
15:0 | VHV_E_STEP_HIGHT | Number of VHV CTs to step after each erase pulse (up to the max). The actual FMC register value should be one less than this since the FMC starts counting from zero. Value will be written to FLASH:FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT when an erase/program operation is initiated. | RO | 0x0001 |
Address Offset | 0x0000 0184 | ||
Physical Address | 0x5000 1184 | Instance | 0x5000 1184 |
Description | Flash Program Pulse | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | PUMP_SU | Pump read->non-read mode transition time in half-microseconds (mainly for FPES). | RO | 0x00 | ||
23:16 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds trim value from production test. |
RO | 0xXX | ||
15:0 | MAX_PP | Max program pulse limit per program operation. Value will be written to FLASH:FSM_PRG_PUL.MAX_PRG_PUL when an erase/program operation is initiated. | RO | 0x0014 |
Address Offset | 0x0000 0188 | ||
Physical Address | 0x5000 1188 | Instance | 0x5000 1188 |
Description | Flash Program and Erase Pulse | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MAX_EP | Max erase pulse limit per erase operation. Value will be written to FLASH:FSM_ERA_PUL.MAX_ERA_PUL when an erase/program operation is initiated. | RO | 0x0FA0 | ||
15:0 | PROGRAM_PW | Program pulse width in half-microseconds. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_PRG_PW.PROG_PUL_WIDTH when a erase/program operation is initiated. | RO | 0x0010 |
Address Offset | 0x0000 018C | ||
Physical Address | 0x5000 118C | Instance | 0x5000 118C |
Description | Flash Erase Pulse Width | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ERASE_PW | Erase pulse width in half-microseconds. Value will be converted to number of FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_ERA_PW.FSM_ERA_PW when a erase/program operation is initiated. | RO | 0x0000 0FA0 |
Address Offset | 0x0000 0190 | ||
Physical Address | 0x5000 1190 | Instance | 0x5000 1190 |
Description | Flash VHV | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
27:24 | TRIM13_P | Value will be written to FLASH:FVHVCT2.TRIM13_P by the flash device driver when an erase/program operation is initiated. Default value holds trim value from production test. |
RO | 0xX | ||
23:20 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
19:16 | VHV_P | Value will be written to FLASH:FVHVCT2.VHVCT_P by the flash device driver when an erase/program operation is initiated. Default value holds trim value from production test. |
RO | 0xX | ||
15:12 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
11:8 | TRIM13_E | Value will be written to FLASH:FVHVCT1.TRIM13_E by the flash device driver when an erase/program operation is initiated. Default value holds trim value from production test. |
RO | 0xX | ||
7:4 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
3:0 | VHV_E | Value will be written to FLASH:FVHVCT1.VHVCT_E by the flash device driver when an erase/program operation is initiated | RO | 0x4 |
Address Offset | 0x0000 0194 | ||
Physical Address | 0x5000 1194 | Instance | 0x5000 1194 |
Description | Flash VHV Program Verify | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
27:24 | TRIM13_PV | Value will be written to FLASH:FVHVCT1.TRIM13_PV by the flash device driver when an erase/program operation is initiated. Default value holds trim value from production test. |
RO | 0xX | ||
23:20 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 | ||
19:16 | VHV_PV | Value will be written to FLASH:FVHVCT1.VHVCT_PV by the flash device driver when an erase/program operation is initiated. | RO | 0x8 | ||
15:8 | VCG2P5 | Control gate voltage during read, read margin, and erase verify. Value will be written to FLASH:FVNVCT.VCG2P5CT by the flash device driver when an erase/program operation is initiated. Default value holds trim value from production test. |
RO | 0xXX | ||
7:0 | VINH | Inhibit voltage applied to unselected columns during programming. | RO | 0x01 |
Address Offset | 0x0000 0198 | ||
Physical Address | 0x5000 1198 | Instance | 0x5000 1198 |
Description | Flash Voltages | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | VSL_P | Sourceline voltage applied to the selected block during programming. Value will be written to FLASH:FVSLP.VSL_P by the flash device driver when an erase/program operation is initiated. Default value holds trim value from production test. |
RO | 0xXX | ||
23:16 | VWL_P | Wordline voltage applied to the selected half-row during programming. Value will be written to FLASH:FVWLCT.VWLCT_P by the flash device driver when an erase/program operation is initiated. Default value holds trim value from production test. |
RO | 0xXX | ||
15:8 | V_READ | Wordline voltage applied to the selected block during reads and verifies. Value will be written to FLASH:FVREADCT.VREADCT by the flash device driver when an erase/program operation is initiated. Default value holds trim value from production test. |
RO | 0xXX | ||
7:0 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds trim value from production test. |
RO | 0xXX |
Address Offset | 0x0000 0294 | ||
Physical Address | 0x5000 1294 | Instance | 0x5000 1294 |
Description | User Identification. Reading this register or the ICEPICK_DEVICE_ID register is the only support way of identifying a device. The value of this register will be written to AON_WUC:JTAGUSERCODE by boot FW while in safezone. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | PG_REV | Field used to distinguish revisions of the device. Default value holds log information from production test. |
RO | 0xX | ||
27:26 | VER | Version number. 0x0: Bits [25:12] of this register has the stated meaning. Any other setting indicate a different encoding of these bits. Default value differs depending on partnumber. |
RO | 0xX | ||
25:23 | RESERVED23 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value differs depending on partnumber. |
RO | 0xX | ||
22:19 | SEQUENCE | Sequence. Used to differentiate between marketing/orderable product where other fields of USER_ID is the same (temp range, flash size, voltage range etc) Default value differs depending on partnumber. |
RO | 0xX | ||
18:16 | PKG | Package type. 0x0: 4x4mm 0x1: 5x5mm 0x2: 7x7mm Others values are reserved for future use. Default value differs depending on partnumber. |
RO | 0xX | ||
15:12 | PROTOCOL | Protocols supported. 0x1: BLE 0x2: RF4CE 0x4: Zigbee/6lowpan 0x8: Proprietary More than one protocol can be supported on same device - values above are then combined. Default value differs depending on partnumber. |
RO | 0xX | ||
11:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value differs depending on partnumber. |
RO | 0xXXX |
Address Offset | 0x0000 02B0 | ||
Physical Address | 0x5000 12B0 | Instance | 0x5000 12B0 |
Description | Flash OTP Data 3 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:23 | EC_STEP_SIZE | Value will be written to FLASH:FSM_STEP_SIZE.EC_STEP_SIZE by the flash device driver when a erase/program operation is initiated. | RO | 0b0 0000 0000 | ||
22 | DO_PRECOND | Value will be written to FLASH:FSM_ST_MACHINE.DO_PRECOND by the flash device driver when a erase/program operation is initiated. Note that during a Total Erase operation the flash bank will always be erased with Precondition enabled independent of the value of this FCFG1 bit field. |
RO | 0 | ||
21:18 | MAX_EC_LEVEL | Value will be written to FLASH:FSM_ERA_PUL.MAX_EC_LEVEL by the flash device driver when a erase/program operation is initiated. | RO | 0x4 | ||
17:16 | TRIM_1P7 | Value will be written to FLASH:FSEQPMP.TRIM_1P7 by the flash device driver when a erase/program operation is initiated. | RO | 0b01 | ||
15:8 | FLASH_SIZE | Value will be written to FLASH:FLASH_SIZE.SECTORS by the boot FW while in safe zone. This register will be write protected by the boot FW by setting FLASH:CFG.CONFIGURED. Default value differs depending on partnumber. |
RO | 0xXX | ||
7:0 | WAIT_SYSCODE | Value will be written to FLASH:WAIT_SYSCODE.WAIT_SYSCODE by boot FW code while in safezone. | RO | 0x03 |
Address Offset | 0x0000 02B4 | ||
Physical Address | 0x5000 12B4 | Instance | 0x5000 12B4 |
Description | Misc Analog Trim | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | RCOSCHFCTRIMFRACT_EN | Value will be written to DDI_0_OSC:CTL1.RCOSCHFCTRIMFRACT_EN by boot FW while in safezone. | RO | 1 | ||
30:26 | RCOSCHFCTRIMFRACT | Value will be written to DDI_0_OSC:CTL1.RCOSCHFCTRIMFRACT by boot FW while in safezone. Default value holds trim value from production test. |
RO | 0xXX | ||
25 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 1 | ||
24:23 | SET_RCOSC_HF_FINE_RESISTOR | Value will be written to DDI_0_OSC:ATESTCTL.SET_RCOSC_HF_FINE_RESISTOR by boot FW while in safezone. | RO | 0b00 | ||
22 | ATESTLF_UDIGLDO_IBIAS_TRIM | Value will be written DDI_0_OSC:ATESTCTL.ATESTLF_UDIGLDO_IBIAS_TRIM by boot FW while in safezone. | RO | 1 | ||
21:16 | NANOAMP_RES_TRIM | Value will be written to DDI_0_OSC:ADCDOUBLERNANOAMPCTL.NANOAMP_RES_TRIM by boot FW while in safezone. Default value holds trim value from production test. |
RO | 0xXX | ||
15:12 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
11 | DITHER_EN | Value will be written to ADI_3_REFSYS:DCDCCTL5.DITHER_EN by boot FW while in safezone. | RO | 0 | ||
10:8 | DCDC_IPEAK | Value will be written to ADI_3_REFSYS:DCDCCTL5.IPEAK by boot FW while in safezone. | RO | 0b100 | ||
7:6 | DEAD_TIME_TRIM | Value will be written to ADI_3_REFSYS:DCDCCTL4.DEADTIME_TRIM by boot FW while in safezone. | RO | 0b01 | ||
5:3 | DCDC_LOW_EN_SEL | Value will be written to ADI_3_REFSYS:DCDCCTL4.LOW_EN_SEL by boot FW while in safezone. | RO | 0b111 | ||
2:0 | DCDC_HIGH_EN_SEL | Value will be written to ADI_3_REFSYS:DCDCCTL4.HIGH_EN_SEL by boot FW while in safezone. | RO | 0b111 |
Address Offset | 0x0000 02B8 | ||
Physical Address | 0x5000 12B8 | Instance | 0x5000 12B8 |
Description | LDO Trim | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:29 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 | ||
28:24 | VDDR_TRIM_SLEEP | Value will be written to ADI_3_REFSYS:DCDCCTL1.VDDR_TRIM_SLEEP by boot FW while in safezone. Default value holds trim value from production test. |
RO | 0xXX | ||
23:19 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b1 1111 | ||
18:16 | GLDO_CURSRC | Value will be written to ADI_3_REFSYS:DCDCCTL0.GLDO_ISRC by boot FW while in safezone. | RO | 0b000 | ||
15:13 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 | ||
12:11 | ITRIM_DIGLDO_LOAD | Value will be written to ADI_2_REFSYS:SOCLDOCTL3.ITRIM_DIGLDO_LOAD by boot FW while in safezone. | RO | 0b00 | ||
10:8 | ITRIM_UDIGLDO | Value will be written to ADI_2_REFSYS:SOCLDOCTL3.ITRIM_UDIGLDO by boot FW while in safezone. | RO | 0b000 | ||
7:3 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b1 1111 | ||
2:0 | VTRIM_DELTA | Value will be written to ADI_2_REFSYS:SOCLDOCTL2.VTRIM_DELTA by boot FW while in safezone. | RO | 0b011 |
Address Offset | 0x0000 02E8 | ||
Physical Address | 0x5000 12E8 | Instance | 0x5000 12E8 |
Description | MAC BLE Address 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR_0_31 | The first 32-bits of the 64-bit MAC BLE address Default value holds trim value from production test. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 02EC | ||
Physical Address | 0x5000 12EC | Instance | 0x5000 12EC |
Description | MAC BLE Address 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR_32_63 | The last 32-bits of the 64-bit MAC BLE address Default value holds trim value from production test. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 02F0 | ||
Physical Address | 0x5000 12F0 | Instance | 0x5000 12F0 |
Description | MAC IEEE 802.15.4 Address 0 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR_0_31 | The first 32-bits of the 64-bit MAC 15.4 address Default value holds trim value from production test. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 02F4 | ||
Physical Address | 0x5000 12F4 | Instance | 0x5000 12F4 |
Description | MAC IEEE 802.15.4 Address 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | ADDR_32_63 | The last 32-bits of the 64-bit MAC 15.4 address Default value holds trim value from production test. |
RO | 0xXXXX XXXX |
Address Offset | 0x0000 0308 | ||
Physical Address | 0x5000 1308 | Instance | 0x5000 1308 |
Description | Flash OTP Data 4 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | STANDBY_MODE_SEL_INT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write operation is initiated. | RO | 1 | ||
30:29 | STANDBY_PW_SEL_INT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write operation is initiated. | RO | 0b00 | ||
28 | DIS_STANDBY_INT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation is initiated. | RO | 1 | ||
27 | DIS_IDLE_INT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is initiated. | RO | 1 | ||
26:24 | VIN_AT_X_INT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write operation is initiated. | RO | 0b000 | ||
23 | STANDBY_MODE_SEL_EXT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_MODE_SEL by flash device driver FW when a flash write operation is initiated. | RO | 1 | ||
22:21 | STANDBY_PW_SEL_EXT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_PW_SEL by flash device driver FW when a flash write operation is initiated. | RO | 0b00 | ||
20 | DIS_STANDBY_EXT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_STANDBY by flash device driver FW when a flash write operation is initiated. | RO | 1 | ||
19 | DIS_IDLE_EXT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is initiated. | RO | 1 | ||
18:16 | VIN_AT_X_EXT_WRT | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:FSEQPMP.VIN_AT_X by flash device driver FW when a flash write operation is initiated. | RO | 0b000 | ||
15 | STANDBY_MODE_SEL_INT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 1 | ||
14:13 | STANDBY_PW_SEL_INT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 0b00 | ||
12 | DIS_STANDBY_INT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 1 | ||
11 | DIS_IDLE_INT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 1 | ||
10:8 | VIN_AT_X_INT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 0, this value will be written to FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 0b111 | ||
7 | STANDBY_MODE_SEL_EXT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_MODE_SEL both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 1 | ||
6:5 | STANDBY_PW_SEL_EXT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.STANDBY_PW_SEL both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 0b00 | ||
4 | DIS_STANDBY_EXT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_STANDBY both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 1 | ||
3 | DIS_IDLE_EXT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_IDLE both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 1 | ||
2:0 | VIN_AT_X_EXT_RD | If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. | RO | 0b111 |
Address Offset | 0x0000 030C | ||
Physical Address | 0x5000 130C | Instance | 0x5000 130C |
Description | Miscellaneous Trim Parameters | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF FFFF | ||
7:0 | TEMPVSLOPE | Signed byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits. | RO | 0x33 |
Address Offset | 0x0000 0310 | ||
Physical Address | 0x5000 1310 | Instance | 0x5000 1310 |
Description | RCOSC HF Temperature Compensation | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | FINE_RESISTOR | Change in FINE_RESISTOR trim | RO | 0x00 | ||
23:16 | CTRIM | Change in CTRIM trim | RO | 0x00 | ||
15:8 | CTRIMFRACT_QUAD | Temp compensation quadratic CTRIMFRACT | RO | 0x00 | ||
7:0 | CTRIMFRACT_SLOPE | Number of CTRIMFRACT codes per 20 degrees C from default temperature | RO | 0x03 |
Address Offset | 0x0000 0318 | ||
Physical Address | 0x5000 1318 | Instance | 0x5000 1318 |
Description | IcePick Device Identification Reading this register or the USER_ID register is the only support way of identifying a device. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | PG_REV | Field used to distinguish revisions of the device. | RO | 0x8 | ||
27:12 | WAFER_ID | Field used to identify silicon die. | RO | 0xB99A | ||
11:0 | MANUFACTURER_ID | Manufacturer code. 0x02F: Texas Instruments |
RO | 0x02F |
Address Offset | 0x0000 031C | ||
Physical Address | 0x5000 131C | Instance | 0x5000 131C |
Description | Factory Configuration (FCFG1) Revision | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | REV | The revision number of the FCFG1 layout. This value will be read by application SW in order to determine which FCFG1 parameters that have valid values. This revision number must be incremented by 1 before any devices are to be produced if the FCFG1 layout has changed since the previous production of devices. Value migth change without warning. |
RO | 0x0000 0023 |
Address Offset | 0x0000 0320 | ||
Physical Address | 0x5000 1320 | Instance | 0x5000 1320 |
Description | Misc OTP Data | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RCOSC_HF_ITUNE | Trim value that migth become into use for cc26xx PG2.2 and cc13xx PG2.0. Trim value for DDI_0_OSC:RCOSCHFCTL.RCOSCHF_ITUNE_TRIM. | RO | 0x0 | ||
27:20 | RCOSC_HF_CRIM | Trim value that migth become into use for cc26xx PG2.2 and cc13xx PG2.0. Trim value for DDI_0_OSC:RCOSCHFCTL.RCOSCHF_CTRIM. | RO | 0x00 | ||
19:15 | PER_M | Trim value for AON_WUC:OSCCFG.PER_M. | RO | 0b0 0001 | ||
14:12 | PER_E | Trim value for AON_WUC:OSCCFG.PER_E. | RO | 0b100 | ||
11:8 | PO_TAIL_RES_TRIM | Trim value for DLO_DTX:PLLCTL1.PO_TAIL_RES_TRIM. | RO | 0x6 | ||
7:0 | TEST_PROGRAM_REV | The revision of the test program used in the production process when FCFG1 was programmed. Value migth change without warning. Default value holds log information from production test. |
RO | 0xXX |
Address Offset | 0x0000 0344 | ||
Physical Address | 0x5000 1344 | Instance | 0x5000 1344 |
Description | IO Configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b1 1111 1111 1111 1111 XXXX XXX0 | ||
6:0 | GPIO_CNT | This value is written to IOC:CFG.GPIO_CNT by boot FW while in safezone. Default value differs depending on partnumber. |
RO | 0xXX |
Address Offset | 0x0000 034C | ||
Physical Address | 0x5000 134C | Instance | 0x5000 134C |
Description | Configuration of IF_ADC | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | FF2ADJ | Trim value for ADI_0_RF:IFADCLFCFG1.FF2ADJ. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0x3 | ||
27:24 | FF3ADJ | Trim value for ADI_0_RF:IFADCLFCFG1.FF3ADJ. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0x4 | ||
23:20 | INT3ADJ | Trim value for ADI_0_RF:IFADCLFCFG0.INT3ADJ. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0x6 | ||
19:16 | FF1ADJ | Trim value for ADI_0_RF:IFADCLFCFG0.FF1ADJ. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0x0 | ||
15:14 | AAFCAP | Trim value for ADI_0_RF:IFADCCTL0.AAFCAP. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b11 | ||
13:10 | INT2ADJ | Trim value for ADI_0_RF:IFADCCTL0.INT2ADJ. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0xD | ||
9:5 | IFDIGLDO_TRIM_OUTPUT | Trim value for ADI_0_RF:IFDLDO2.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. |
RO | 0xXX | ||
4:0 | IFANALDO_TRIM_OUTPUT | Trim value for ADI_0_RF:IFALDO2.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. |
RO | 0xXX |
Address Offset | 0x0000 0350 | ||
Physical Address | 0x5000 1350 | Instance | 0x5000 1350 |
Description | Configuration of OSC | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:30 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 | ||
29:26 | XOSC_HF_ROW_Q12 | Trim value for DDI_0_OSC:ANABYPASSVAL1.XOSC_HF_ROW_Q12. | RO | 0xF | ||
25:10 | XOSC_HF_COLUMN_Q12 | Trim value for DDI_0_OSC:ANABYPASSVAL1.XOSC_HF_COLUMN_Q12. | RO | 0x003F | ||
9:2 | RCOSCLF_CTUNE_TRIM | Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_CTUNE_TRIM. Default value holds trim value from production test. |
RO | 0xXX | ||
1:0 | RCOSCLF_RTUNE_TRIM | Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_RTUNE_TRIM. | RO | 0b00 |
Address Offset | 0x0000 0354 | ||
Physical Address | 0x5000 1354 | Instance | 0x5000 1354 |
Description | Configuration of RF Frontend in Divide-by-2 Mode | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | IFAMP_IB | Trim value for ADI_0_RF:IFAMPCTL3.IB. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0x7 | ||
27:24 | LNA_IB | Trim value for [ANATOP_MMAP::ADI_0_RF:LNACTL2:IB]. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. |
RO | 0xX | ||
23:19 | IFAMP_TRIM | Trim value for ADI_0_RF:IFAMPCTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b0 0000 | ||
18:14 | CTL_PA0_TRIM | Trim value for ADI_0_RF:PACTL0.TRIM. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. |
RO | 0xXX | ||
13 | PATRIMCOMPLETE_N | Status of PA trim 0: Trimmed 1: Not trimmed Default value holds trim value from production test. |
RO | X | ||
12:7 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 1111 | ||
6:0 | RFLDO_TRIM_OUTPUT | Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. |
RO | 0xXX |
Address Offset | 0x0000 0358 | ||
Physical Address | 0x5000 1358 | Instance | 0x5000 1358 |
Description | Configuration of Synthesizer in Divide-by-2 Mode | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:28 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xF | ||
27:12 | RFC_MDM_DEMIQMC0 | Trim value for RFC_MDM:DEMIQMC0.GAINFACTOR and RFC_MDM:DEMIQMC0.PHASEFACTOR Value is read by RF Core ROM FW during RF Core initialization only on cc13xx. |
RO | 0xFFFF | ||
11:6 | LDOVCO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:VCOLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. |
RO | 0xXX | ||
5:0 | SLDO_TRIM_OUTPUT | Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. |
RO | 0xXX |
Address Offset | 0x0000 035C | ||
Physical Address | 0x5000 135C | Instance | 0x5000 135C |
Description | AUX_ADC Gain in Absolute Reference Mode | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds log information from production test. |
RO | 0xXXXX | ||
15:0 | SOC_ADC_ABS_GAIN_TEMP1 | SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated in production test.. Default value holds log information from production test. |
RO | 0xXXXX |
Address Offset | 0x0000 0360 | ||
Physical Address | 0x5000 1360 | Instance | 0x5000 1360 |
Description | AUX_ADC Gain in Relative Reference Mode | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | RESERVED16 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds trim value from production test. |
RO | 0xXXXX | ||
15:0 | SOC_ADC_REL_GAIN_TEMP1 | SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated in production test.. Default value holds trim value from production test. |
RO | 0xXXXX |
Address Offset | 0x0000 0368 | ||
Physical Address | 0x5000 1368 | Instance | 0x5000 1368 |
Description | AUX_ADC Temperature Offsets in Absolute Reference Mode | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds trim value from production test. |
RO | 0xXX | ||
23:16 | SOC_ADC_REL_OFFSET_TEMP1 | SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test.. Default value holds trim value from production test. |
RO | 0xXX | ||
15:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds trim value from production test. |
RO | 0xXX | ||
7:0 | SOC_ADC_ABS_OFFSET_TEMP1 | SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test.. Default value holds trim value from production test. |
RO | 0xXX |
Address Offset | 0x0000 036C | ||
Physical Address | 0x5000 136C | Instance | 0x5000 136C |
Description | AUX_ADC Reference Trim and Offset for External Reference Mode | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0bXX XXXX XXXX 11XX XXXX XXXX XX10 | ||
5:0 | SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 | Value to write in ADI_4_AUX:ADCREF1.VTRIM at temperature 1 (30C). Default value holds trim value from production test. |
RO | 0xXX |
Address Offset | 0x0000 0370 | ||
Physical Address | 0x5000 1370 | Instance | 0x5000 1370 |
Description | Ampltude Compensation Threashold 1 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0xFF | ||
23:18 | HPMRAMP3_LTH | HPM Ramp3 low amplitude threshhold. In HPM_RAMP3, if amp > HPMRAMP3_LTH && amp < HPMRAMP3_HTH then move on HPM_UPDATE. |
RO | 0b01 1110 | ||
17:16 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 | ||
15:10 | HPMRAMP3_HTH | In HPM_RAMP3, if amp > HPMRAMP3_LTH && amp < HPMRAMP3_HTH then move on to HPM_UPDATE. | RO | 0b10 0000 | ||
9:6 | IBIASCAP_LPTOHP_OL_CNT | During XOSC mode transition, CAP trim and IBIAS trim should be modified by this amount. IBIAS and CAP trim open loop count. CAP_REM is remainder of the CAP that is left to reach the final cap value. | RO | 0xA | ||
5:0 | HPMRAMP1_TH | During XOSC mode transition, CAP trim and IBIAS trim should be modified by this amount. IBIAS and CAP trim open loop count. CAP_REM is remainder of the CAP that is left to reach the final cap value. | RO | 0b00 1110 |
Address Offset | 0x0000 0374 | ||
Physical Address | 0x5000 1374 | Instance | 0x5000 1374 |
Description | Ampltude Compensation Threashold 2 | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:26 | LPMUPDATE_LTH | LPM Update low amplitude threshhold. if amp > LPMUPDATE_LTH && amp < LPMUPDATE_HTH then move on. |
RO | 0b01 1010 | ||
25:24 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 | ||
23:18 | LPMUPDATE_HTM | LPM Update high amplitude threshhold. if amp > LPMUPDATE_LTH && amp < LPMUPDATE_HTH then move on. |
RO | 0b10 0010 | ||
17:16 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 | ||
15:10 | ADC_COMP_AMPTH_LPM | When ADC is forced in comparator mode, this value is used as OPAMP's threshold during LPM_UPDATE mode. Actual amplitude is compared against this threshhold to generate 1-bit adc_threshholdmet indicator output. | RO | 0b00 0000 | ||
9:8 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 | ||
7:2 | ADC_COMP_AMPTH_HPM | When ADC is forced in comparator mode, this value is used as OPAMP's threshold during HPM_UPDATE mode. Actual amplitude is compared against this threshhold to generate 1-bit adc_threshholdmet indicator output. | RO | 0b00 0000 | ||
1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 |
Address Offset | 0x0000 0378 | ||
Physical Address | 0x5000 1378 | Instance | 0x5000 1378 |
Description | Amplitude Compensation Control | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 1 | ||
30 | AMPCOMP_REQ_MODE | Trim value for DDI_0_OSC:AMPCOMPCTL.AMPCOMP_REQ_MODE. | RO | 1 | ||
29:24 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 1111 | ||
23:20 | IBIAS_OFFSET | Offset values of XOSC IBIAS trim. IBIAS trim value would always be greater than or equal to this offset in both HPM and LPM. | RO | 0x1 | ||
19:16 | IBIAS_INIT | Initial value of XOSC IBIAS trim. During ramping up, IBIAS is set to IBIAS_OFFSET + IBIAS_INIT. | RO | 0x8 | ||
15:8 | LPM_IBIAS_WAIT_CNT_FINAL | FSM waits for ddi_lpm_ibias_wait_cnt_final clock cycles in IDAC_DECREMENT_WITH_MEASURE states in order to compensate slow response of the xtal. 8-bits. | RO | 0x3F | ||
7:4 | CAP_STEP | Step size of XOSC CAP trim (both Q1 and Q2) during XOSC mode transition. Can vary from 6 to 12. Other values are possible but not valid. | RO | 0x4 | ||
3:0 | IBIASCAP_HPTOLP_OL_CNT | During HPM to LPM transition, CAP trim and IBIAS trim should be modified by this amount. IBIAS and CAP trim open loop count. CAP_REM is remainder of the CAP that is left to reach the final cap value. Do not need to program this. CAP_TRIM = CAP_INIT - CAP_STEP*IBIASCAP_HPTOLP_OL_CNT - CAP_REM; IBIAS_TRIM = IBIAS_INIT - 1*IBIASCAP_HPTOLP_OL_CNT; Here, cap_init is decimal conversion of cap_init_col and cap_init_row. |
RO | 0x7 |
Address Offset | 0x0000 037C | ||
Physical Address | 0x5000 137C | Instance | 0x5000 137C |
Description | Analog Bypass Value for OSC | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:14 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 1111 1111 1111 1111 | ||
13:0 | XOSC_HF_IBIASTHERM | Value of xosc_hf_ibiastherm when oscdig is bypassed. | RO | 0b00 0011 1111 1111 |
Address Offset | 0x0000 0380 | ||
Physical Address | 0x5000 1380 | Instance | 0x5000 1380 |
Description | Configuration of IFADC in Divide-by-2 Mode | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:18 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 1111 1111 1111 | ||
17 | RSSITRIMCOMPLETE_N | Status of RSSI trim 0: Trimmed 1: Not trimmed Default value holds trim value from production test. |
RO | X | ||
16:9 | RSSI_OFFSET | Value for RSSI measured in production test. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. |
RO | 0xXX | ||
8:6 | QUANTCTLTHRES | Trim value for ADI_0_RF:IFADCQUANT0.TH. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b101 | ||
5:0 | DACTRIM | Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. |
RO | 0b00 1101 |
Address Offset | 0x0000 0388 | ||
Physical Address | 0x5000 1388 | Instance | 0x5000 1388 |
Description | Voltage Trim | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:29 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 | ||
28:24 | VDDR_TRIM_HH | Trim value for 1.94V VDDR found in production test (for CC13xx high PA output power only). | RO | 0b1 1111 | ||
23:21 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 | ||
20:16 | VDDR_TRIM_H | Trim value for 1.85V VDDR found in production test (for external VDDR load mode) | RO | 0b1 1111 | ||
15:13 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 | ||
12:8 | VDDR_TRIM_SLEEP_H | Trim value for 1.75V VDDR recharge target found in production test (for external VDDR load mode). | RO | 0b1 1111 | ||
7:5 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 | ||
4:0 | TRIMBOD_H | Trim value for 2.0V VDDS BOD target found in production test. Default value holds trim value from production test. |
RO | 0xXX |
Address Offset | 0x0000 038C | ||
Physical Address | 0x5000 138C | Instance | 0x5000 138C |
Description | OSC Configuration | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:30 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b11 | ||
29 | ADC_SH_VBUF_EN | Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. | RO | 1 | ||
28 | ADC_SH_MODE_EN | Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. | RO | 1 | ||
27 | ATESTLF_RCOSCLF_IBIAS_TRIM | Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. | RO | 0 | ||
26:25 | XOSCLF_REGULATOR_TRIM | Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. | RO | 0b00 | ||
24:21 | XOSCLF_CMIRRWR_RATIO | Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. | RO | 0x0 | ||
20:19 | XOSC_HF_FAST_START | Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. This trim value is not relevant for PG1 devices. |
RO | 0b01 | ||
18 | XOSC_OPTION | 0: XOSC_HF unavailable (may not be bonded out) 1: XOSC_HF available (default) Default value differs depending on partnumber. |
RO | X | ||
17 | BAW_OPTION | 0: BAW available 1: BAW unavailable (default) Default value differs depending on partnumber. |
RO | X | ||
16 | BAW_BIAS_HOLD_MODE_EN | Enable signal for bias sample and hold mode. Written to ADI_2_REFSYS:BAWCTL2.BIAS_HOLD_MODE_EN. | RO | X | ||
15:12 | BAW_CURRMIRR_RATIO | Set current mirror ratio in BAW. Controls amount of current flowing in BAW oscillator core. Written to ADI_2_REFSYS:BAWCTL2.CURRMIRR_RATIO. Default value holds trim value from production test. |
RO | 0xX | ||
11:8 | BAW_BIAS_RES_SET | Adjust the BAW bias resistor to set the current in the BAW core. Two's complement encoding. Written to ADI_2_REFSYS:BAWCTL1.BIAS_RES_SET. Default value holds trim value from production test. |
RO | 0xX | ||
7 | BAW_FILTER_EN | Enables a low pass filter around 1 kHz in the bias. Written to ADI_2_REFSYS:BAWCTL0.FILTER_EN. Default value holds trim value from production test. |
RO | X | ||
6:5 | BAW_BIAS_RECHARGE_DELAY | This field sets the recharge delay for sample and hold mode. Written to ADI_2_REFSYS:BAWCTL0.BIAS_RECHARGE_DLY. Default value holds trim value from production test. |
RO | 0xX | ||
4:3 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds trim value from production test. |
RO | 0xX | ||
2:1 | BAW_SERIES_CAP | Cap to set BAW into proper mode. Written to ADI_2_REFSYS:BAWCTL0.SERIES_CAP. Default value holds trim value from production test. |
RO | 0xX | ||
0 | BAW_DIV3_BYPASS | Bypass div3 for divider, for divide ratio of 17.5. Written to ADI_2_REFSYS:BAWCTL0.DIV3_BYPASS. 0: Divide by 52.5 for use with 2520 MHz BAW 1: Divide by 17.5 for use with 840 MHz BAW Default value holds trim value from production test. |
RO | X |
Address Offset | 0x0000 0394 | ||
Physical Address | 0x5000 1394 | Instance | 0x5000 1394 |
Description | Capasitor Trim | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | FLUX_CAP_0P28_TRIM | Reserved storage of measurement value on 0.28um pitch FLUX CAP (measured in production test) | RO | 0xFFFF | ||
15:0 | FLUX_CAP_0P4_TRIM | Reserved storage of measurement value on 0.4um pitch FLUX CAP (measured in production test) | RO | 0xFFFF |
Address Offset | 0x0000 0398 | ||
Physical Address | 0x5000 1398 | Instance | 0x5000 1398 |
Description | Misc OSC Control | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:29 | RESERVED | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b111 | ||
28:27 | PEAK_DET_ITRIM | Trim value for DDI_0_OSC:XOSCHFCTL.PEAK_DET_ITRIM. | RO | 0b00 | ||
26:24 | HP_BUF_ITRIM | Trim value for DDI_0_OSC:XOSCHFCTL.HP_BUF_ITRIM. | RO | 0b000 | ||
23:22 | LP_BUF_ITRIM | Trim value for DDI_0_OSC:XOSCHFCTL.LP_BUF_ITRIM. | RO | 0b00 | ||
21:20 | DBLR_LOOP_FILTER_RESET_VOLTAGE | Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.DBLR_LOOP_FILTER_RESET_VOLTAGE. | RO | 0b00 | ||
19:10 | HPM_IBIAS_WAIT_CNT | Trim value for DDI_0_OSC:RADCEXTCFG.HPM_IBIAS_WAIT_CNT. | RO | 0b01 0000 0000 | ||
9:4 | LPM_IBIAS_WAIT_CNT | Trim value for DDI_0_OSC:RADCEXTCFG.LPM_IBIAS_WAIT_CNT. | RO | 0b11 1111 | ||
3:0 | IDAC_STEP | Trim value for DDI_0_OSC:RADCEXTCFG.IDAC_STEP. | RO | 0x8 |
Address Offset | 0x0000 039C | ||
Physical Address | 0x5000 139C | Instance | 0x5000 139C |
Description | Power Down Current Control 20C | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DELTA_CACHE_REF | Additional maximum current, in units of 1uA, with cache retention | RO | 0x08 | ||
23:16 | DELTA_RFMEM_RET | Additional maximum current, in 1uA units, with RF memory retention | RO | 0x0B | ||
15:8 | DELTA_XOSC_LPM | Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode | RO | 0xA6 | ||
7:0 | BASELINE | Worst-case baseline maximum powerdown current, in units of 0.5uA | RO | 0x08 |
Address Offset | 0x0000 03A0 | ||
Physical Address | 0x5000 13A0 | Instance | 0x5000 13A0 |
Description | Power Down Current Control 35C | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DELTA_CACHE_REF | Additional maximum current, in units of 1uA, with cache retention | RO | 0x0C | ||
23:16 | DELTA_RFMEM_RET | Additional maximum current, in 1uA units, with RF memory retention | RO | 0x10 | ||
15:8 | DELTA_XOSC_LPM | Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode | RO | 0xA5 | ||
7:0 | BASELINE | Worst-case baseline maximum powerdown current, in units of 0.5uA | RO | 0x0A |
Address Offset | 0x0000 03A4 | ||
Physical Address | 0x5000 13A4 | Instance | 0x5000 13A4 |
Description | Power Down Current Control 50C | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DELTA_CACHE_REF | Additional maximum current, in units of 1uA, with cache retention | RO | 0x12 | ||
23:16 | DELTA_RFMEM_RET | Additional maximum current, in 1uA units, with RF memory retention | RO | 0x18 | ||
15:8 | DELTA_XOSC_LPM | Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode | RO | 0xA2 | ||
7:0 | BASELINE | Worst-case baseline maximum powerdown current, in units of 0.5uA | RO | 0x0D |
Address Offset | 0x0000 03A8 | ||
Physical Address | 0x5000 13A8 | Instance | 0x5000 13A8 |
Description | Power Down Current Control 65C | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DELTA_CACHE_REF | Additional maximum current, in units of 1uA, with cache retention | RO | 0x1C | ||
23:16 | DELTA_RFMEM_RET | Additional maximum current, in 1uA units, with RF memory retention | RO | 0x25 | ||
15:8 | DELTA_XOSC_LPM | Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode | RO | 0x9C | ||
7:0 | BASELINE | Worst-case baseline maximum powerdown current, in units of 0.5uA | RO | 0x14 |
Address Offset | 0x0000 03AC | ||
Physical Address | 0x5000 13AC | Instance | 0x5000 13AC |
Description | Power Down Current Control 80C | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DELTA_CACHE_REF | Additional maximum current, in units of 1uA, with cache retention | RO | 0x2E | ||
23:16 | DELTA_RFMEM_RET | Additional maximum current, in 1uA units, with RF memory retention | RO | 0x3B | ||
15:8 | DELTA_XOSC_LPM | Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode | RO | 0x90 | ||
7:0 | BASELINE | Worst-case baseline maximum powerdown current, in units of 0.5uA | RO | 0x21 |
Address Offset | 0x0000 03B0 | ||
Physical Address | 0x5000 13B0 | Instance | 0x5000 13B0 |
Description | Power Down Current Control 95C | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DELTA_CACHE_REF | Additional maximum current, in units of 1uA, with cache retention | RO | 0x4C | ||
23:16 | DELTA_RFMEM_RET | Additional maximum current, in 1uA units, with RF memory retention | RO | 0x62 | ||
15:8 | DELTA_XOSC_LPM | Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode | RO | 0x7A | ||
7:0 | BASELINE | Worst-case baseline maximum powerdown current, in units of 0.5uA | RO | 0x3B |
Address Offset | 0x0000 03B4 | ||
Physical Address | 0x5000 13B4 | Instance | 0x5000 13B4 |
Description | Power Down Current Control 110C | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DELTA_CACHE_REF | Additional maximum current, in units of 1uA, with cache retention | RO | 0x78 | ||
23:16 | DELTA_RFMEM_RET | Additional maximum current, in 1uA units, with RF memory retention | RO | 0x9E | ||
15:8 | DELTA_XOSC_LPM | Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode | RO | 0x70 | ||
7:0 | BASELINE | Worst-case baseline maximum powerdown current, in units of 0.5uA | RO | 0x6B |
Address Offset | 0x0000 03B8 | ||
Physical Address | 0x5000 13B8 | Instance | 0x5000 13B8 |
Description | Power Down Current Control 125C | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:24 | DELTA_CACHE_REF | Additional maximum current, in units of 1uA, with cache retention | RO | 0xAD | ||
23:16 | DELTA_RFMEM_RET | Additional maximum current, in 1uA units, with RF memory retention | RO | 0xE1 | ||
15:8 | DELTA_XOSC_LPM | Additional maximum current, in units of 1uA, with XOSC_HF on in low-power mode | RO | 0x80 | ||
7:0 | BASELINE | Worst-case baseline maximum powerdown current, in units of 0.5uA | RO | 0x9A |
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