const Cache_PC |
|
Permit Caching
#define Cache_PC (UInt32)1
const Cache_PCX |
|
Permit caching in external cache
#define Cache_PCX (UInt32)4
const Cache_PFX |
|
Prefetchable by external engines
#define Cache_PFX (UInt32)8
const Cache_WTE |
|
Write through enabled
#define Cache_WTE (UInt32)2
enum Cache_L1Size |
|
Level 1 cache size type definition. Can be used for both L1D & L1P
typedef enum Cache_L1Size {
Cache_L1Size_0K,
// Amount of cache is 0K, Amount of SRAM is 32K
Cache_L1Size_4K,
// Amount of cache is 4K, Amount of SRAM is 28K
Cache_L1Size_8K,
// Amount of cache is 8K, Amount of SRAM is 24K
Cache_L1Size_16K,
// Amount of cache is 16K, Amount of SRAM is 16K
Cache_L1Size_32K
// Amount of cache is 32K, Amount of SRAM is 0K
} Cache_L1Size;
enum Cache_L2Size |
|
Level 2 cache size type definition
typedef enum Cache_L2Size {
Cache_L2Size_0K,
// L2 is all SRAM
Cache_L2Size_32K,
// Amount of cache is 32K
Cache_L2Size_64K,
// Amount of cache is 64K
Cache_L2Size_128K,
// Amount of cache is 128K
Cache_L2Size_256K,
// Amount of cache is 256K
Cache_L2Size_512K,
// Amount of cache is 512K
Cache_L2Size_1024K
// Amount of cache is 1024K
} Cache_L2Size;
enum Cache_Mar |
|
MAR register setting type definition
typedef enum Cache_Mar {
Cache_Mar_DISABLE,
// The Permit Copy bit of MAR register is disabled
Cache_Mar_ENABLE
// The Permit Copy bit of MAR register is enabled
} Cache_Mar;
enum Cache_Mode |
|
Lists of cache modes for L1/L2 caches
typedef enum Cache_Mode {
Cache_Mode_FREEZE,
// No new cache lines are allocated
Cache_Mode_BYPASS,
// All access result in long-distance access
Cache_Mode_NORMAL
// Normal operation of cache
} Cache_Mode;
enum Cache_Type |
|
Lists of bitmask cache types
typedef enum Cache_Type {
Cache_Type_L1P,
// Level 1 Program cache
Cache_Type_L1D,
// Level 1 Data cache
Cache_Type_L1,
// Level 1 caches
Cache_Type_L2P,
// Level 2 Program cache
Cache_Type_L2D,
// Level 2 Data cache
Cache_Type_L2,
// Level 2 caches
Cache_Type_ALLP,
// All Program caches
Cache_Type_ALLD,
// All Data caches
Cache_Type_ALL
// All caches
} Cache_Type;
struct Cache_Size |
|
Structure for specifying all cache sizes
typedef struct Cache_Size {
// L1 Program cache size
// L1 Data data size
// L2 cache size
} Cache_Size;
Cache_disable() // module-wide |
|
Disables the 'type' cache(s)
Void Cache_disable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
DETAILS
Disabling of L2 cache is currently not supported.
Cache_enable() // module-wide |
|
Enables all cache(s)
Void Cache_enable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
Cache_getMar() // module-wide |
|
Gets the MAR register for the specified base address
UInt32 Cache_getMar(Ptr baseAddr);
ARGUMENTS
baseAddr
address for which MAR is requested
RETURNS
value of MAR register
Cache_getMode() // module-wide |
|
Get mode of a cache
ARGUMENTS
type
bit mask of cache type
RETURNS
mode of specified level of cache
Cache_getSize() // module-wide |
|
Get sizes of all caches
ARGUMENTS
size
pointer to structure of type Cache_Size
Cache_inv() // module-wide |
|
Invalidate the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
in range are invalidated for all the 'type' caches
Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_invL1pAll() // module-wide |
|
Invalidate all of L1 Program cache
DETAILS
Performs a global invalidate of L1P cache.
Polls the L1P invalidate register until done.
Cache_setMar() // module-wide |
|
Set MAR register(s) that corresponds to the specified address range
Void Cache_setMar(Ptr baseAddr, SizeT byteSize, UInt32 value);
ARGUMENTS
baseAddr
start address for which to set MAR
byteSize
size (in bytes) of memory block
value
value for setting MAR register
DETAILS
All cached entries in L1 and L2 are written back and invalidated.
NOTE
The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on
C66x CorePac devices.
Cache_setMode() // module-wide |
|
Set mode of a cache
ARGUMENTS
type
bit mask of cache type
mode
mode of cache
RETURNS
previous mode of cache
Cache_setSize() // module-wide |
|
Set sizes of all caches
ARGUMENTS
size
pointer to structure of type Cache_Size
Cache_wait() // module-wide |
|
Wait for a previous cache operation to complete
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache
operation is not truly complete until it has worked its way
through all buffering and all memory writes have landed in the
source memory.
Cache_wb() // module-wide |
|
Writes back a range of memory from all cache(s)
Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
within the range are left valid in the 'type' caches and the data
within the range will be written back to the source memory.
Cache_wbAll() // module-wide |
|
Write back all caches
DETAILS
Perform a global write back. There is no effect on program cache.
All data cache lines are left valid.
Perform a global write back. There is no effect on L1P cache.
All cache lines are left valid in L1D cache and dirty lines in L1D cache
are written back to L2 or external. All cache lines are left valid in
L2 cache and dirty lines in L2 cache are written back to external.
This function does not wait for write back operation to perculate
through the whole memory system before returing. Call Cache_wait(),
after this function if necessary.
Cache_wbInv() // module-wide |
|
Writes back and invalidates the range of memory within the
specified starting address and byte count. The range of
addresses operated on gets quantized to whole cache lines in
each cache. All lines within the range are written back to the
source memory and then invalidated for all 'type' caches
Void Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_wbInvAll() // module-wide |
|
Write back invalidate all caches
DETAILS
Performs a global write back and invalidate. All cache lines
are written out to physical memory and then invalidated.
Performs a global write back and invalidate. All cache lines are
invalidated in L1P cache. All dirty cache lines are written back to L2
or external and then invalidated in L1D cache. All dirty cache lines
are written back to external and then invalidated in L2 cache.
This function does not wait for write back operation to perculate
through the whole memory system before returing. Call Cache_wait(),
after this function if necessary.
Cache_wbInvL1dAll() // module-wide |
|
Write back invalidate L1D cache
Void Cache_wbInvL1dAll();
DETAILS
Performs a global write back and invalidate of L1D cache.
All dirty cache lines are written back to L2 or
external and then invalidated in L1D cache.
This function does not wait for write back operation to perculate
through the whole memory system before returing. Call Cache_wait(),
after this function if necessary.
Cache_wbL1dAll() // module-wide |
|
Write back L1D cache
DETAILS
Perform a global write back of L1D cache. There is no effect on L1P
or L2 cache. All cache lines are left valid in L1D cache and the
dirty lines in L1D cache are written back to L2 or external.
This function does not wait for write back operation to perculate
through the whole memory system before returing. Call Cache_wait(),
after this function if necessary.
Module-Wide Built-Ins |
|
// Get this module's unique id
Bool Cache_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Cache_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Cache_Module_getMask();
// Returns the diagnostics mask for this module
Void Cache_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
const Cache.PC |
|
Permit Caching
C SYNOPSIS
const Cache.PCX |
|
Permit caching in external cache
C SYNOPSIS
const Cache.PFX |
|
Prefetchable by external engines
C SYNOPSIS
const Cache.WTE |
|
Write through enabled
C SYNOPSIS
enum Cache.L1Size |
|
Level 1 cache size type definition. Can be used for both L1D & L1P
values of type Cache.L1Size
const Cache.L1Size_0K;
// Amount of cache is 0K, Amount of SRAM is 32K
const Cache.L1Size_4K;
// Amount of cache is 4K, Amount of SRAM is 28K
const Cache.L1Size_8K;
// Amount of cache is 8K, Amount of SRAM is 24K
const Cache.L1Size_16K;
// Amount of cache is 16K, Amount of SRAM is 16K
const Cache.L1Size_32K;
// Amount of cache is 32K, Amount of SRAM is 0K
C SYNOPSIS
enum Cache.L2Size |
|
Level 2 cache size type definition
values of type Cache.L2Size
const Cache.L2Size_0K;
// L2 is all SRAM
const Cache.L2Size_32K;
// Amount of cache is 32K
const Cache.L2Size_64K;
// Amount of cache is 64K
const Cache.L2Size_128K;
// Amount of cache is 128K
const Cache.L2Size_256K;
// Amount of cache is 256K
const Cache.L2Size_512K;
// Amount of cache is 512K
const Cache.L2Size_1024K;
// Amount of cache is 1024K
C SYNOPSIS
enum Cache.Mar |
|
MAR register setting type definition
values of type Cache.Mar
const Cache.Mar_DISABLE;
// The Permit Copy bit of MAR register is disabled
const Cache.Mar_ENABLE;
// The Permit Copy bit of MAR register is enabled
C SYNOPSIS
enum Cache.Mode |
|
Lists of cache modes for L1/L2 caches
values of type Cache.Mode
const Cache.Mode_FREEZE;
// No new cache lines are allocated
const Cache.Mode_BYPASS;
// All access result in long-distance access
const Cache.Mode_NORMAL;
// Normal operation of cache
C SYNOPSIS
enum Cache.Type |
|
Lists of bitmask cache types
values of type Cache.Type
const Cache.Type_L1P;
// Level 1 Program cache
const Cache.Type_L1D;
// Level 1 Data cache
const Cache.Type_L1;
// Level 1 caches
const Cache.Type_L2P;
// Level 2 Program cache
const Cache.Type_L2D;
// Level 2 Data cache
const Cache.Type_L2;
// Level 2 caches
const Cache.Type_ALLP;
// All Program caches
const Cache.Type_ALLD;
// All Data caches
const Cache.Type_ALL;
// All caches
C SYNOPSIS
struct Cache.Size |
|
Structure for specifying all cache sizes
var obj = new Cache.Size;
// L1 Program cache size
// L1 Data data size
// L2 cache size
C SYNOPSIS
metaonly config Cache.common$ // module-wide |
|
Common module configuration parameters
DETAILS
All modules have this configuration parameter. Its name
contains the '$' character to ensure it does not conflict with
configuration parameters declared by the module. This allows
new configuration parameters to be added in the future without
any chance of breaking existing modules.
metaonly Cache.getMarMeta() // module-wide |
|
Gets the current MAR value for the specified base address
Cache.getMarMeta(Ptr baseAddr) returns UInt32
ARGUMENTS
baseAddr
address for which MAR value is requested
RETURNS
MAR value for specified address
metaonly Cache.setMarMeta() // module-wide |
|
Set MAR register(s) that corresponds to the specified address range
Cache.setMarMeta(Ptr baseAddr, SizeT byteSize, UInt32 value) returns Void
ARGUMENTS
baseAddr
start address for which to set MAR
byteSize
size (in bytes) of memory block
value
value for setting MAR register
DETAILS
The 'pc' ("Permit Caching") field is enabled for all memory regions
in the device platform. Only set the fields of the Mar structure
which need to be modified. Any field not set retains its reset value.
NOTE
The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on
C66x CorePac devices.