This module manages the data and instruction caches on Cortex A8
processors.
It provides a list of functions that perform cache operations. The
functions operate on a per cache line except for the 'All' functions
which operate on the entire cache specified. Any Address that is not
aligned to a cache line gets rounded down to the address of
the nearest cache line.
The L1 data and program caches as well as the L2 cache are enabled
by default early during the startup sequence (prior to any
Module_startup()s).
Data caching requires the MMU to be enabled and the cacheable
attribute of the section/page descriptor for a corresponding
memory region to be enabled.
Program caching does not require the MMU to be enabled and therefore
occurs when the L1 program cache is enabled.
const Cache_sizeL1dCacheLine |
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Size of L1 data cache Line
#define Cache_sizeL1dCacheLine (UInt)64
const Cache_sizeL1pCacheLine |
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Size of L1 program cache Line
#define Cache_sizeL1pCacheLine (UInt)64
const Cache_sizeL2CacheLine |
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Size of L2 cache Line
#define Cache_sizeL2CacheLine (UInt)64
enum Cache_Type |
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Lists of bitmask cache types
typedef enum Cache_Type {
Cache_Type_L1P,
// Level 1 Program cache
Cache_Type_L1D,
// Level 1 Data cache
Cache_Type_L1,
// Level 1 caches
Cache_Type_L2P,
// Level 2 Program cache
Cache_Type_L2D,
// Level 2 Data cache
Cache_Type_L2,
// Level 2 caches
Cache_Type_ALLP,
// All Program caches
Cache_Type_ALLD,
// All Data caches
Cache_Type_ALL
// All caches
} Cache_Type;
config Cache_A_badBlockLength // module-wide |
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Asserted in Cache_lock
extern const Assert_Id Cache_A_badBlockLength;
config Cache_A_blockCrossesPage // module-wide |
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Asserted in Cache_lock
extern const Assert_Id Cache_A_blockCrossesPage;
config Cache_branchPredictionEnabled // module-wide |
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Enable Branch Prediction at startup, default is true
extern const Bool Cache_branchPredictionEnabled;
DETAILS
This flag controls whether Branch Prediction should be automatically
enabled or disabled during system startup.
NOTE
Upon reset, the A8's Program Flow Prediction (Branch Prediction)
feature is disabled.
config Cache_enableCache // module-wide |
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Enable L1 and L2 data and program caches
extern const Bool Cache_enableCache;
DETAILS
To enable a subset of the caches, set this parameter
to 'false' and call Cache_enable() within main, passing it only
the
Cache_Type(s) to be enabled.
Data caching requires the MMU and the memory section/page
descriptor cacheable attribute to be enabled.
config Cache_unlockL2Cache // module-wide |
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Unlock all 8 L2 cache ways at startup, default is true
extern const Bool Cache_unlockL2Cache;
DETAILS
Ordinarily, the L2 cache ways should all be unlocked at
system startup.
During development using CCS, if the application exits
while L2 cache ways are locked, the soft-reset function
DOES NOT unlock the L2 cache ways. To overcome this problem,
the L2 cache ways are unlocked during Cache module startup.
If for any reason this behavior is undesirable, setting this
config parameter to false will disable the automatic unlocking
of the L2 cache ways.
Cache_disable() // module-wide |
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Disables the 'type' cache(s)
Void Cache_disable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
Cache_disableBP() // module-wide |
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Disable Branch Prediction
DETAILS
Calling this API will disable branch prediction.
NOTE
Upon reset, the A8's Program Flow Prediction (Branch Prediction)
feature is disabled.
Cache_enable() // module-wide |
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Enables all cache(s)
Void Cache_enable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
Cache_enableBP() // module-wide |
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Enable Branch Prediction
DETAILS
Calling this API will enable branch prediction.
NOTE
Upon reset, the A8's Program Flow Prediction (Branch Prediction)
feature is disabled.
Cache_inv() // module-wide |
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Invalidate the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
in range are invalidated for all the 'type' caches
Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_invL1dAll() // module-wide |
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Invalidate all of L1 data cache
DETAILS
This function should be used with caution. In general, the
L1 data cache may contain some stack variable or valid data
that should not be invalidated. This function should be used
only when all contents of L1 data cache is unwanted.
Cache_invL1pAll() // module-wide |
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Invalidate all of L1 program cache
Cache_lock() // module-wide |
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Loads and locks a memory block into the L2 cache
UInt Cache_lock(Ptr blockPtr, SizeT byteCnt);
ARGUMENTS
blockPtr
start address of range to be locked
byteCnt
number of bytes to be locked
RETURNS
key = bitmask of L2 cache "way" used
DETAILS
A block of memory is loaded into the L2 cache and
a corresponding L2 cache "way" is locked.
The memory block is loaded into cache one L2 cache line at time.
The returned key is a bitmask of the L2 cache "way"
used to lock the memory block.
This key should be passed in
a subsequent call to
Cache_unlock()
if the memory block is to be unlocked.
If the key returned is zero, then the lock operation failed
due to insufficient cache "ways" remaining to perform the operation.
The locking algorithm requires at least two unlocked cache ways:
one for the memory block, and one for the locking code itself.
As the A8 L2 cache is always an 8 way cache, locking a cache way
consumes 1/8 of the total L2 cache, regardless of the actual memory
block size. For instance, if the size of L2 cache is 256K bytes,
locking ANY size memory block into a way will tie up 32K bytes
of L2 cache.
The byteCnt argument must be less than or equal to an L2 "way"
size.
Locking memory blocks larger than a way page size requires
calling this API multiple times.
An assert is generated if this rule is violated.
The memory block must not cross an L2 "way" page boundary.
Locking memory blocks that cross way page boundaries requires
calling this API multiple times.
An assert is generated if this rule is violated.
Except for the normal L1 instruction cache behavior
during code execution, the L1 instruction cache is
unaffected by this API.
The L1 data cache will be temporarily polluted by the contents
of the referenced memory block.
NOTE
Interrupts are disabled for the entire time the memory block
is being loaded into cache. For this reason, use of this API
is probably best at system intialization time
(ie: within 'main()').
Cache_unlock() // module-wide |
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Unlocks an L2 cache way
Void Cache_unlock(UInt key);
ARGUMENTS
key
key returned by lock.
DETAILS
Unlocks the L2 cache "way" locked by
Cache_lock().
NOTE
multiple L2 cache "ways" can be unlocked simultaneously by "or-ing"
together the bitmasks returned from several invocations of Cache_lock().
Cache_wait() // module-wide |
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Wait for a previous cache operation to complete
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache
operation is not truly complete until it has worked its way
through all buffering and all memory writes have landed in the
source memory.
Cache_wb() // module-wide |
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Writes back a range of memory from all cache(s)
Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
within the range are left valid in the 'type' caches and the data
within the range will be written back to the source memory.
Cache_wbAll() // module-wide |
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Write back all caches
DETAILS
Perform a global write back. There is no effect on program cache.
All data cache lines are left valid.
Cache_wbInv() // module-wide |
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Writes back and invalidates the range of memory within the
specified starting address and byte count. The range of
addresses operated on gets quantized to whole cache lines in
each cache. All lines within the range are written back to the
source memory and then invalidated for all 'type' caches
Void Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_wbInvAll() // module-wide |
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Write back invalidate all caches
DETAILS
Performs a global write back and invalidate. All cache lines
are written out to physical memory and then invalidated.
Module-Wide Built-Ins |
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// Get this module's unique id
Bool Cache_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Cache_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Cache_Module_getMask();
// Returns the diagnostics mask for this module
Void Cache_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module