This module manages the data and instruction caches on Cortex A15
processors.
It provides a list of functions that perform cache operations. The
functions operate on a per cache line except for the 'All' functions
which operate on the entire cache specified. Any Address that is not
aligned to a cache line gets rounded down to the address of
the nearest cache line.
The L1 data and program caches as well as the L2 cache are enabled
by default early during the startup sequence (prior to any
Module_startup()s).
Data caching requires the MMU to be enabled and the cacheable
attribute of the section/page descriptor for a corresponding
memory region to be enabled.
Program caching does not require the MMU to be enabled and therefore
occurs when the L1 program cache is enabled.
Note: The invalidate instruction is implemented as a clean/invalidate
instruction on A15. Therefore, calls to Cache_inv()/Cache_invAll()
will behave like Cache_wbInv()/Cache_wbInvAll() on A15.
const Cache_sizeL1dCacheLine |
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Size of L1 data cache Line in bytes
#define Cache_sizeL1dCacheLine (UInt)64
const Cache_sizeL1pCacheLine |
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Size of L1 program cache Line in bytes
#define Cache_sizeL1pCacheLine (UInt)64
const Cache_sizeL2CacheLine |
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Size of L2 cache Line in bytes
#define Cache_sizeL2CacheLine (UInt)64
enum Cache_Type |
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Lists of bitmask cache types
typedef enum Cache_Type {
Cache_Type_L1P,
// Level 1 Program cache
Cache_Type_L1D,
// Level 1 Data cache
Cache_Type_L1,
// Level 1 caches
Cache_Type_L2P,
// Level 2 Program cache
Cache_Type_L2D,
// Level 2 Data cache
Cache_Type_L2,
// Level 2 caches
Cache_Type_ALLP,
// All Program caches
Cache_Type_ALLD,
// All Data caches
Cache_Type_ALL
// All caches
} Cache_Type;
config Cache_A_badBlockLength // module-wide |
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Asserted in Cache_lock
extern const Assert_Id Cache_A_badBlockLength;
config Cache_A_blockCrossesPage // module-wide |
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Asserted in Cache_lock
extern const Assert_Id Cache_A_blockCrossesPage;
config Cache_A_cacheDisableUnsupported // module-wide |
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Assert raised when attempting to disable L1 data or L2 unified cache
extern const Assert_Id Cache_A_cacheDisableUnsupported;
DETAILS
When running in SMP mode, the inter-core lock is implemented using
ldrex/strex instructions and requires the hardware to implement a
global monitor to work. Some devices like Keystone 2, do not implement
a global monitor (only a local monitor). On such devices, the
cache coherency logic (snoop control unit) along with the local monitors
can effectively work like a global monitor. Therefore, it is important
that the caches are not disabled as that would disable cache coherency
on the particular core and cause the inter-core lock to not work.
config Cache_A_cacheEnableUnsupported // module-wide |
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Assert raised when attempting to enable L1 data or L2 unified cache
extern const Assert_Id Cache_A_cacheEnableUnsupported;
DETAILS
It is not recommended for the user code to anable/disable the caches
when running in SMP mode. Please see the documentation
here for more details.
config Cache_branchPredictionEnabled // module-wide |
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Enable Branch Prediction at startup, default is true
extern const Bool Cache_branchPredictionEnabled;
DETAILS
This flag controls whether Branch Prediction should be automatically
enabled or disabled during system startup.
NOTE
Upon reset, the A15's Program Flow Prediction (Branch Prediction)
feature is disabled.
config Cache_enableCache // module-wide |
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Enable L1 and L2 data and program caches
extern const Bool Cache_enableCache;
DETAILS
To enable a subset of the caches, set this parameter
to 'false' and call Cache_enable() within main, passing it only
the
Cache_Type(s) to be enabled.
Data caching requires the MMU and the memory section/page
descriptor cacheable attribute to be enabled.
config Cache_errata798870 // module-wide |
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Enable workaround for ARM errata 798870
extern const Bool Cache_errata798870;
DETAILS
Errata 798870 brief description:
A memory read can stall indefinitely in the L2 cache
Cache_disable() // module-wide |
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Disables the 'type' cache(s)
Void Cache_disable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
DETAILS
This function is not fully supported when running in SMP mode. Only
L1 program cache disable is supported. Attempting to disable the L1
data and/or L2 cache will cause an assertion failure.
Here's a brief explanation of why caches should not be disabled.
When running in SMP mode, the inter-core lock is implemented using
ldrex/strex instructions and requires the hardware to implement a
global monitor to work properly. Some devices like Keystone 2,
do not implement a global monitor (only a local monitor). On such
devices, the cache coherency logic (snoop control unit) along with
the local monitors can effectively work like a global monitor.
Therefore, it is important that the caches are not disabled as that
would disable cache coherency on the particular core and cause the
inter-core lock to not work.
Cache_disableBP() // module-wide |
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Disable Branch Prediction
DETAILS
Calling this API will disable branch prediction.
NOTE
Upon reset, the A15's Program Flow Prediction (Branch Prediction)
feature is disabled.
Cache_enable() // module-wide |
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Enables all cache(s)
Void Cache_enable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
DETAILS
This function is not fully supported when running in SMP mode. Only
L1 program cache enable is supported. Attempting to enable the L1
data and/or L2 cache will cause an assertion failure. The caches are
enabled during the startup sequence if
enableCache
config param is set to true. Since disabling the caches at runtime
is not fully supported, the cache enable function is not fully
supported.
Please see
Cache_disable() cdoc for more a detailed
explanation of why disabling the caches is harmful and not supported.
Cache_enableBP() // module-wide |
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Enable Branch Prediction
DETAILS
Calling this API will enable branch prediction.
NOTE
Upon reset, the A15's Program Flow Prediction (Branch Prediction)
feature is disabled.
Cache_inv() // module-wide |
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Invalidate the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
in range are invalidated for all the 'type' caches
Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_invL1pAll() // module-wide |
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Invalidate all of L1 program cache
Cache_preLoad() // module-wide |
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Loads a memory block into the L2 cache
Void Cache_preLoad(Ptr blockPtr, SizeT byteCnt);
ARGUMENTS
blockPtr
start address of range to be loaded
byteCnt
number of bytes to be loaded
DETAILS
A block of memory is loaded into the L2 cache.
The memory block is loaded into cache one L2 cache line at time.
The byteCnt argument must be less than or equal to an L2 cache
size. An assert is generated if this rule is violated.
Except for the normal L1 instruction cache behavior
during code execution, the L1 instruction cache is
unaffected by this API.
The L1 data cache will be temporarily polluted by the contents
of the referenced memory block.
NOTE
Interrupts are disabled for the entire time the memory block
is being loaded into cache. For this reason, use of this API
is probably best at system intialization time
(ie: within 'main()').
Cache_wait() // module-wide |
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Wait for a previous cache operation to complete
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache
operation is not truly complete until it has worked its way
through all buffering and all memory writes have landed in the
source memory.
Cache_wb() // module-wide |
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Writes back a range of memory from all cache(s)
Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
within the range are left valid in the 'type' caches and the data
within the range will be written back to the source memory.
Cache_wbAll() // module-wide |
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Write back all caches
DETAILS
Perform a global write back. There is no effect on program cache.
All data cache lines are left valid.
This function writes back the data cache to the point of coherency.
On a Cortex-A15, point of coherency is the main memory implying that
this function will write back the L1 data cache (on this core) followed
by the L2 unified cache that is shared by all cores in the MPCore
sub-system.
When running in SMP mode, it is not recommended to call this function
as it does not guarantee that the L1 data caches on all other cores
will be written back before writing back the unified L2 cache. This
function should only be called if all other cores are in a power down
state or if their local L1 caches are disabled i.e. they do not have
any dirty L1 cache lines.
Cache_wbAllLoUIS() // module-wide |
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Write back data cache to PoU for an Inner Shareable domain
DETAILS
This function writes back the L1 data cache. There is no effect
on program cache. All data cache lines are left valid.
On Cortex-A15, this function will write back the local CPU's
L1 data cache to the L2 cache but not beyond. Calling this function
has no affect on the local L1 caches of all other cores in the MPCore
sub-system. This API should be called with Hwis and/or Tasking disabled
to guarantee the write back operation is complete.
Cache_wbInv() // module-wide |
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Writes back and invalidates the range of memory within the
specified starting address and byte count. The range of
addresses operated on gets quantized to whole cache lines in
each cache. All lines within the range are written back to the
source memory and then invalidated for all 'type' caches
Void Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_wbInvAll() // module-wide |
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Write back invalidate all caches
DETAILS
Performs a global write back and invalidate. All cache lines
are written out to physical memory and then invalidated.
This function writes back and invalidates the data cache to the point
of coherency. On a Cortex-A15, point of coherency is the main memory
implying that this function will write back and invalidate the L1 data
cache (on this core) followed by the L2 unified cache that is shared
by all cores in the MPCore sub-system.
When running in SMP mode, it is not recommended to call this function
as it does not guarantee that the L1 data caches on all other cores
will be flushed before flushing the unified L2 cache. This function
should only be called if all other cores are in a power down state or
if their local L1 caches are disabled i.e. they do not have any dirty
L1 cache lines.
Cache_wbInvAllLoUIS() // module-wide |
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Write back invalidate data cache to PoU for an Inner Shareable domain
Void Cache_wbInvAllLoUIS();
DETAILS
On Cortex-A15, this function will write back and invalidate the local
CPU's L1 data cache to the L2 cache but not beyond. Calling this
function has no affect on the local L1 caches of all other cores in the
MPCore sub-system. This API should be called with Hwis and/or Tasking
disabled to guarantee the write back invalidate operation is complete.
Module-Wide Built-Ins |
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// Get this module's unique id
Bool Cache_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Cache_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Cache_Module_getMask();
// Returns the diagnostics mask for this module
Void Cache_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module