module ti.catalog.msp430.peripherals.communication.USI

values of type USI.USIIFGCC_t// USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0

const USI.USIIFGCC_OFF// USIIFG automatically cleared on USICNTx update;

const USI.USIIFGCC// USIIFG is not cleared automatically;

values of type USI.USIIFG_t// USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0

const USI.USIIFG_OFF// No interrupt pending;

const USI.USIIFG// Interrupt pending;

values of type USI.USILSB_t// LSB first select. This bit controls the direction of the receive and transmit shift register

const USI.USILSB_OFF// MSB first;

const USI.USILSB// LSB first;

values of type USI.USIMST_t// Master select

const USI.USIMST_OFF// Slave mode;

const USI.USIMST// Master mode;

values of type USI.USIOE_t// Data output enable

const USI.USIOE_OFF// Output disabled;

const USI.USIOE// Output enabled;

values of type USI.USIPE5_t// USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode

const USI.USIPE5_OFF// USI function disabled;

const USI.USIPE5// USI function enabled;

values of type USI.USIPE6_t// USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode

const USI.USIPE6_OFF// USI function disabled;

const USI.USIPE6// USI function enabled;

values of type USI.USIPE7_t// USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode

const USI.USIPE7_OFF// USI function disabled;

const USI.USIPE7// USI function enabled;

values of type USI.USISCLREL_t// SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected

const USI.USISCLREL_OFF// SCL line is held low if USIIFG is set;

const USI.USISCLREL// SCL line is released;

values of type USI.USISSEL_t// Clock source select. Not used in slave mode

const USI.USISSEL_0// SCLK (Not used in SPI mode);

const USI.USISSEL_1// ACLK;

const USI.USISSEL_2// SMCLK;

const USI.USISSEL_3// SMCLK;

const USI.USISSEL_4// USISWCLK bit;

const USI.USISSEL_5// TACCR0;

const USI.USISSEL_6// TACCR1;

const USI.USISSEL_7// TACCR2 (Reserved on MSP430F20xx devices);

values of type USI.USISTP_t// STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0

const USI.USISTP_OFF// No STOP condition received;

const USI.USISTP// STOP condition received;

values of type USI.USISTTIE_t// START condition interrupt-enable

const USI.USISTTIE_OFF// Interrupt on START condition disabled;

const USI.USISTTIE// Interrupt on START condition enabled;

values of type USI.USISTTIFG_t// START condition interrupt flag

const USI.USISTTIFG_OFF// No START condition received. No interrupt pending;

const USI.USISTTIFG// START condition received. Interrupt pending;

values of type USI.USISWCLK_t// Software clock

const USI.USISWCLK_OFF// Input clock is low;

const USI.USISWCLK// Input clock is high;

values of type USI.USISWRST_t// USI software reset

const USI.USISWRST_OFF// USI released for operation;

const USI.USISWRST// USI logic held in reset state;

var obj = new USI.ForceSetDefaultRegister_t// Force Set Default Register;

obj.register = String ...

obj.regForceSet = Bool ...

var obj = new USI.USICKCTL_t// ;

obj.USIDIV// Clock divider select 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 = IUSI.USIDIV_t ...

obj.USISSEL// Clock source select. Not used in slave mode. 000 SCLK (Not used in SPI mode) 001 ACLK 010 SMCLK 011 SMCLK 100 USISWCLK bit 101 TACCR0 110 TACCR1 111 TACCR2 (Reserved on MSP430F20xx devices) = IUSI.USISSEL_t ...

obj.USICKPL// Clock polarity select 0 Inactive state is low 1 Inactive state is high = IUSI.USICKPL_t ...

obj.USISWCLK// Software clock 0 Input clock is low 1 Input clock is high = IUSI.USISWCLK_t ...

var obj = new USI.USICNT_t// ;

obj.USISCLREL// SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected. 0 SCL line is held low if USIIFG is set 1 SCL line is released = IUSI.USISCLREL_t ...

obj.USI16B// 16-bit shift register enable 0 8-bit shift register mode. Low byte register USISRL is used. 1 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously = IUSI.USI16B_t ...

obj.USIIFGCC// USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0. 0 USIIFG automatically cleared on USICNTx update 1 USIIFG is not cleared automatically = IUSI.USIIFGCC_t ...

obj.USICNT4// USI bit count bit 4 The USICNTx bits set the number of bits to be received or transmitted = IUSI.USICNT4_t ...

obj.USICNT3// USI bit count bit 3 The USICNTx bits set the number of bits to be received or transmitted = IUSI.USICNT3_t ...

obj.USICNT2// USI bit count bit 2 The USICNTx bits set the number of bits to be received or transmitted = IUSI.USICNT2_t ...

obj.USICNT1// USI bit count bit 1 The USICNTx bits set the number of bits to be received or transmitted = IUSI.USICNT1_t ...

obj.USICNT0// USI bit count bit 0 The USICNTx bits set the number of bits to be received or transmitted = IUSI.USICNT0_t ...

var obj = new USI.USICTL0_t// ;

obj.USIPE7// USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled = IUSI.USIPE7_t ...

obj.USIPE6// USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled = IUSI.USIPE6_t ...

obj.USIPE5// USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode. 0 USI function disabled 1 USI function enabled = IUSI.USIPE5_t ...

obj.USILSB// LSB first select. This bit controls the direction of the receive and transmit shift register. 0 MSB first 1 LSB first = IUSI.USILSB_t ...

obj.USIMST// Master select 0 Slave mode 1 Master mode = IUSI.USIMST_t ...

obj.USIGE// Output latch control 0 Output latch enable depends on shift clock 1 Output latch always enabled and transparent = IUSI.USIGE_t ...

obj.USIOE// Data output enable 0 Output disabled 1 Output enabled = IUSI.USIOE_t ...

obj.USISWRST// USI software reset 0 USI released for operation. 1 USI logic held in reset state = IUSI.USISWRST_t ...

var obj = new USI.USICTL1_t// ;

obj.USICKPH// Clock phase select 0 Data is changed on the first SCLK edge and captured on the following edge. 1 Data is captured on the first SCLK edge and changed on the following edge = IUSI.USICKPH_t ...

obj.USII2C// I2C mode enable 0 I2C mode disabled 1 I2C mode enabled = IUSI.USII2C_t ...

obj.USISTTIE// START condition interrupt-enable 0 Interrupt on START condition disabled 1 Interrupt on START condition enabled = IUSI.USISTTIE_t ...

obj.USIIE// USI counter interrupt enable 0 Interrupt disabled 1 Interrupt enabled = IUSI.USIIE_t ...

obj.USIAL// Arbitration lost 0 No arbitration lost condition 1 Arbitration lost = IUSI.USIAL_t ...

obj.USISTP// STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No STOP condition received 1 STOP condition received = IUSI.USISTP_t ...

obj.USISTTIFG// START condition interrupt flag 0 No START condition received. No interrupt pending. 1 START condition received. Interrupt pending = IUSI.USISTTIFG_t ...

obj.USIIFG// USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No interrupt pending 1 Interrupt pending = IUSI.USIIFG_t ...

var obj = new USI.regIntVect_t// Interrupt vector description;

obj.registerName = String ...

obj.registerDescription = String ...

obj.isrToggleString = String ...

obj.priorityName = String ...

obj.interruptEnable = Bool ...

obj.interruptHandler = Bool ...

obj.priority = Int ...

module-wide functions

USI.getAll// Find all peripherals of a certain type() returns IPeripheral.Instance[]

USI.getRegisters// Find all registers defined by the peripheral() returns String[]

per-instance config parameters

var params = new USI.Params// Instance config-params object;

params.USICKCTL// USI Clock Control Register = USI.USICKCTL_t {

USIDIV: IUSI.USIDIV_0,

USISSEL: IUSI.USISSEL_0,

USICKPL: IUSI.USICKPL_OFF,

USISWCLK: IUSI.USISWCLK_OFF

};

params.USICNT// USI Bit Counter Register = USI.USICNT_t {

USISCLREL: IUSI.USISCLREL_OFF,

USI16B: IUSI.USI16B_OFF,

USIIFGCC: IUSI.USIIFGCC_OFF,

USICNT4: IUSI.USICNT4_OFF,

USICNT3: IUSI.USICNT3_OFF,

USICNT2: IUSI.USICNT2_OFF,

USICNT1: IUSI.USICNT1_OFF,

USICNT0: IUSI.USICNT0_OFF

};

params.USICTL0// USI Control Register 0 = USI.USICTL0_t {

USIPE7: IUSI.USIPE7_OFF,

USIPE6: IUSI.USIPE6_OFF,

USIPE5: IUSI.USIPE5_OFF,

USILSB: IUSI.USILSB_OFF,

USIMST: IUSI.USIMST_OFF,

USIGE: IUSI.USIGE_OFF,

USIOE: IUSI.USIOE_OFF,

USISWRST: IUSI.USISWRST

};

params.USICTL1// USI Control Register 1 = USI.USICTL1_t {

USICKPH: IUSI.USICKPH_OFF,

USII2C: IUSI.USII2C_OFF,

USISTTIE: IUSI.USISTTIE_OFF,

USIIE: IUSI.USIIE_OFF,

USIAL: IUSI.USIAL_OFF,

USISTP: IUSI.USISTP_OFF,

USISTTIFG: IUSI.USISTTIFG_OFF,

USIIFG: IUSI.USIIFG

};

params.forceSetDefaultRegister// Determine if each Register needs to be forced set or not = USI.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.interruptSource// USI interrupt enables = USI.regIntVect_t[2] undefined;

params.name// Specific peripheral name given by the device = String undefined;

params.owner// String specifying the entity that manages the peripheral = String undefined;

per-instance creation

var inst = USI.create// Create an instance-object(IClock.Instance clock, params);

per-instance functions

inst.getUSIIE// Gets USIIE register() returns Bool

inst.getUSISTTIE// Gets USISTTIE register() returns Bool

inst.setUSIIE// Sets USIIE register(Bool set) returns Bool

inst.setUSISTTIE// Sets USISTTIE register(Bool set) returns Bool

enum USI.USI16B_t

index URL

16-bit shift register enable

XDCscript usage meta-domain

values of type USI.USI16B_t

const USI.USI16B_OFF;

// 8-bit shift register mode. Low byte register USISRL is used

const USI.USI16B;

// 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously

enum USI.USIAL_t

index URL

Arbitration lost

XDCscript usage meta-domain

values of type USI.USIAL_t

const USI.USIAL_OFF;

// No arbitration lost condition

const USI.USIAL;

// Arbitration lost

enum USI.USICKPH_t

index URL

Clock phase select

XDCscript usage meta-domain

values of type USI.USICKPH_t

const USI.USICKPH_OFF;

// Data is changed on the first SCLK edge and captured on the following edge

const USI.USICKPH;

// Data is captured on the first SCLK edge and changed on the following edge

enum USI.USICKPL_t

index URL

Clock polarity select

XDCscript usage meta-domain

values of type USI.USICKPL_t

const USI.USICKPL_OFF;

// Inactive state is low

const USI.USICKPL;

// Inactive state is high

enum USI.USICNT0_t

index URL

USI bit count - Bit0

XDCscript usage meta-domain

values of type USI.USICNT0_t

const USI.USICNT0_OFF;

// USI bit count

const USI.USICNT0;

// USI bit count

enum USI.USICNT1_t

index URL

USI bit count - Bit1

XDCscript usage meta-domain

values of type USI.USICNT1_t

const USI.USICNT1_OFF;

// USI bit count

const USI.USICNT1;

// USI bit count

enum USI.USICNT2_t

index URL

USI bit count - Bit2

XDCscript usage meta-domain

values of type USI.USICNT2_t

const USI.USICNT2_OFF;

// USI bit count

const USI.USICNT2;

// USI bit count

enum USI.USICNT3_t

index URL

USI bit count - Bit3

XDCscript usage meta-domain

values of type USI.USICNT3_t

const USI.USICNT3_OFF;

// USI bit count

const USI.USICNT3;

// USI bit count

enum USI.USICNT4_t

index URL

USI bit count - Bit4

XDCscript usage meta-domain

values of type USI.USICNT4_t

const USI.USICNT4_OFF;

// USI bit count

const USI.USICNT4;

// USI bit count

enum USI.USIDIV_t

index URL

Clock divider select

XDCscript usage meta-domain

values of type USI.USIDIV_t

const USI.USIDIV_0;

// Divide by 1

const USI.USIDIV_1;

// Divide by 2

const USI.USIDIV_2;

// Divide by 4

const USI.USIDIV_3;

// Divide by 8

const USI.USIDIV_4;

// Divide by 16

const USI.USIDIV_5;

// Divide by 32

const USI.USIDIV_6;

// Divide by 64

const USI.USIDIV_7;

// Divide by 128

enum USI.USIGE_t

index URL

Output latch control

XDCscript usage meta-domain

values of type USI.USIGE_t

const USI.USIGE_OFF;

// Output latch enable depends on shift clock

const USI.USIGE;

// Output latch always enabled and transparent

enum USI.USII2C_t

index URL

I2C mode enable

XDCscript usage meta-domain

values of type USI.USII2C_t

const USI.USII2C_OFF;

// I2C mode disabled

const USI.USII2C;

// I2C mode enabled

enum USI.USIIE_t

index URL

USI counter interrupt enable

XDCscript usage meta-domain

values of type USI.USIIE_t

const USI.USIIE_OFF;

// Interrupt disabled

const USI.USIIE;

// Interrupt enabled

enum USI.USIIFGCC_t

index URL

USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0

XDCscript usage meta-domain

values of type USI.USIIFGCC_t

const USI.USIIFGCC_OFF;

// USIIFG automatically cleared on USICNTx update

const USI.USIIFGCC;

// USIIFG is not cleared automatically

enum USI.USIIFG_t

index URL

USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0

XDCscript usage meta-domain

values of type USI.USIIFG_t

const USI.USIIFG_OFF;

// No interrupt pending

const USI.USIIFG;

// Interrupt pending

enum USI.USILSB_t

index URL

LSB first select. This bit controls the direction of the receive and transmit shift register

XDCscript usage meta-domain

values of type USI.USILSB_t

const USI.USILSB_OFF;

// MSB first

const USI.USILSB;

// LSB first

enum USI.USIMST_t

index URL

Master select

XDCscript usage meta-domain

values of type USI.USIMST_t

const USI.USIMST_OFF;

// Slave mode

const USI.USIMST;

// Master mode

enum USI.USIOE_t

index URL

Data output enable

XDCscript usage meta-domain

values of type USI.USIOE_t

const USI.USIOE_OFF;

// Output disabled

const USI.USIOE;

// Output enabled

enum USI.USIPE5_t

index URL

USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode

XDCscript usage meta-domain

values of type USI.USIPE5_t

const USI.USIPE5_OFF;

// USI function disabled

const USI.USIPE5;

// USI function enabled

enum USI.USIPE6_t

index URL

USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode

XDCscript usage meta-domain

values of type USI.USIPE6_t

const USI.USIPE6_OFF;

// USI function disabled

const USI.USIPE6;

// USI function enabled

enum USI.USIPE7_t

index URL

USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode

XDCscript usage meta-domain

values of type USI.USIPE7_t

const USI.USIPE7_OFF;

// USI function disabled

const USI.USIPE7;

// USI function enabled

enum USI.USISCLREL_t

index URL

SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected

XDCscript usage meta-domain

values of type USI.USISCLREL_t

const USI.USISCLREL_OFF;

// SCL line is held low if USIIFG is set

const USI.USISCLREL;

// SCL line is released

enum USI.USISSEL_t

index URL

Clock source select. Not used in slave mode

XDCscript usage meta-domain

values of type USI.USISSEL_t

const USI.USISSEL_0;

// SCLK (Not used in SPI mode)

const USI.USISSEL_1;

// ACLK

const USI.USISSEL_2;

// SMCLK

const USI.USISSEL_3;

// SMCLK

const USI.USISSEL_4;

// USISWCLK bit

const USI.USISSEL_5;

// TACCR0

const USI.USISSEL_6;

// TACCR1

const USI.USISSEL_7;

// TACCR2 (Reserved on MSP430F20xx devices)

enum USI.USISTP_t

index URL

STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0

XDCscript usage meta-domain

values of type USI.USISTP_t

const USI.USISTP_OFF;

// No STOP condition received

const USI.USISTP;

// STOP condition received

enum USI.USISTTIE_t

index URL

START condition interrupt-enable

XDCscript usage meta-domain

values of type USI.USISTTIE_t

const USI.USISTTIE_OFF;

// Interrupt on START condition disabled

const USI.USISTTIE;

// Interrupt on START condition enabled

enum USI.USISTTIFG_t

index URL

START condition interrupt flag

XDCscript usage meta-domain

values of type USI.USISTTIFG_t

const USI.USISTTIFG_OFF;

// No START condition received. No interrupt pending

const USI.USISTTIFG;

// START condition received. Interrupt pending

enum USI.USISWCLK_t

index URL

Software clock

XDCscript usage meta-domain

values of type USI.USISWCLK_t

const USI.USISWCLK_OFF;

// Input clock is low

const USI.USISWCLK;

// Input clock is high

enum USI.USISWRST_t

index URL

USI software reset

XDCscript usage meta-domain

values of type USI.USISWRST_t

const USI.USISWRST_OFF;

// USI released for operation

const USI.USISWRST;

// USI logic held in reset state

struct USI.ForceSetDefaultRegister_t

index URL

Force Set Default Register

XDCscript usage meta-domain

var obj = new USI.ForceSetDefaultRegister_t;

obj.register = String ...

obj.regForceSet = Bool ...

DETAILS

Type to store if each register needs to be forced initialized even if the register is in default state.

SEE

ForceSetDefaultRegister_t

struct USI.USICKCTL_t

index URL

XDCscript usage meta-domain

var obj = new USI.USICKCTL_t;

obj.USIDIV = IUSI.USIDIV_t ...

// Clock divider select 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128

obj.USISSEL = IUSI.USISSEL_t ...

// Clock source select. Not used in slave mode. 000 SCLK (Not used in SPI mode) 001 ACLK 010 SMCLK 011 SMCLK 100 USISWCLK bit 101 TACCR0 110 TACCR1 111 TACCR2 (Reserved on MSP430F20xx devices)

obj.USICKPL = IUSI.USICKPL_t ...

// Clock polarity select 0 Inactive state is low 1 Inactive state is high

obj.USISWCLK = IUSI.USISWCLK_t ...

// Software clock 0 Input clock is low 1 Input clock is high

struct USI.USICNT_t

index URL

XDCscript usage meta-domain

var obj = new USI.USICNT_t;

obj.USISCLREL = IUSI.USISCLREL_t ...

// SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected. 0 SCL line is held low if USIIFG is set 1 SCL line is released

obj.USI16B = IUSI.USI16B_t ...

// 16-bit shift register enable 0 8-bit shift register mode. Low byte register USISRL is used. 1 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously

obj.USIIFGCC = IUSI.USIIFGCC_t ...

// USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0. 0 USIIFG automatically cleared on USICNTx update 1 USIIFG is not cleared automatically

obj.USICNT4 = IUSI.USICNT4_t ...

// USI bit count bit 4 The USICNTx bits set the number of bits to be received or transmitted

obj.USICNT3 = IUSI.USICNT3_t ...

// USI bit count bit 3 The USICNTx bits set the number of bits to be received or transmitted

obj.USICNT2 = IUSI.USICNT2_t ...

// USI bit count bit 2 The USICNTx bits set the number of bits to be received or transmitted

obj.USICNT1 = IUSI.USICNT1_t ...

// USI bit count bit 1 The USICNTx bits set the number of bits to be received or transmitted

obj.USICNT0 = IUSI.USICNT0_t ...

// USI bit count bit 0 The USICNTx bits set the number of bits to be received or transmitted

struct USI.USICTL0_t

index URL

XDCscript usage meta-domain

var obj = new USI.USICTL0_t;

obj.USIPE7 = IUSI.USIPE7_t ...

// USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled

obj.USIPE6 = IUSI.USIPE6_t ...

// USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled

obj.USIPE5 = IUSI.USIPE5_t ...

// USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode. 0 USI function disabled 1 USI function enabled

obj.USILSB = IUSI.USILSB_t ...

// LSB first select. This bit controls the direction of the receive and transmit shift register. 0 MSB first 1 LSB first

obj.USIMST = IUSI.USIMST_t ...

// Master select 0 Slave mode 1 Master mode

obj.USIGE = IUSI.USIGE_t ...

// Output latch control 0 Output latch enable depends on shift clock 1 Output latch always enabled and transparent

obj.USIOE = IUSI.USIOE_t ...

// Data output enable 0 Output disabled 1 Output enabled

obj.USISWRST = IUSI.USISWRST_t ...

// USI software reset 0 USI released for operation. 1 USI logic held in reset state

struct USI.USICTL1_t

index URL

XDCscript usage meta-domain

var obj = new USI.USICTL1_t;

obj.USICKPH = IUSI.USICKPH_t ...

// Clock phase select 0 Data is changed on the first SCLK edge and captured on the following edge. 1 Data is captured on the first SCLK edge and changed on the following edge

obj.USII2C = IUSI.USII2C_t ...

// I2C mode enable 0 I2C mode disabled 1 I2C mode enabled

obj.USISTTIE = IUSI.USISTTIE_t ...

// START condition interrupt-enable 0 Interrupt on START condition disabled 1 Interrupt on START condition enabled

obj.USIIE = IUSI.USIIE_t ...

// USI counter interrupt enable 0 Interrupt disabled 1 Interrupt enabled

obj.USIAL = IUSI.USIAL_t ...

// Arbitration lost 0 No arbitration lost condition 1 Arbitration lost

obj.USISTP = IUSI.USISTP_t ...

// STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No STOP condition received 1 STOP condition received

obj.USISTTIFG = IUSI.USISTTIFG_t ...

// START condition interrupt flag 0 No START condition received. No interrupt pending. 1 START condition received. Interrupt pending

obj.USIIFG = IUSI.USIIFG_t ...

// USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No interrupt pending 1 Interrupt pending

struct USI.regIntVect_t

index URL

Interrupt vector description

XDCscript usage meta-domain

var obj = new USI.regIntVect_t;

obj.registerName = String ...

obj.registerDescription = String ...

obj.isrToggleString = String ...

obj.priorityName = String ...

obj.interruptEnable = Bool ...

obj.interruptHandler = Bool ...

obj.priority = Int ...

DETAILS

Type to describe a single interrupt vector pin and all its possible configurations.

SEE

regIntVect_t

USI.getAll() // module-wide

index URL

Find all peripherals of a certain type

XDCscript usage meta-domain

USI.getAll() returns IPeripheral.Instance[]

DETAILS

The type of the peripherals returned is defined by the type of the caller.

RETURNS

Returns an array of IPeripheral instances

USI.getRegisters() // module-wide

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Find all registers defined by the peripheral

XDCscript usage meta-domain

USI.getRegisters() returns String[]

RETURNS

Returns an array of register names

Instance Config Parameters

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XDCscript usage meta-domain

var params = new USI.Params;

// Instance config-params object

params.USICKCTL = USI.USICKCTL_t {

// USI Clock Control Register

USIDIV: IUSI.USIDIV_0,

USISSEL: IUSI.USISSEL_0,

USICKPL: IUSI.USICKPL_OFF,

USISWCLK: IUSI.USISWCLK_OFF

};

params.USICNT = USI.USICNT_t {

// USI Bit Counter Register

USISCLREL: IUSI.USISCLREL_OFF,

USI16B: IUSI.USI16B_OFF,

USIIFGCC: IUSI.USIIFGCC_OFF,

USICNT4: IUSI.USICNT4_OFF,

USICNT3: IUSI.USICNT3_OFF,

USICNT2: IUSI.USICNT2_OFF,

USICNT1: IUSI.USICNT1_OFF,

USICNT0: IUSI.USICNT0_OFF

};

params.USICTL0 = USI.USICTL0_t {

// USI Control Register 0

USIPE7: IUSI.USIPE7_OFF,

USIPE6: IUSI.USIPE6_OFF,

USIPE5: IUSI.USIPE5_OFF,

USILSB: IUSI.USILSB_OFF,

USIMST: IUSI.USIMST_OFF,

USIGE: IUSI.USIGE_OFF,

USIOE: IUSI.USIOE_OFF,

USISWRST: IUSI.USISWRST

};

params.USICTL1 = USI.USICTL1_t {

// USI Control Register 1

USICKPH: IUSI.USICKPH_OFF,

USII2C: IUSI.USII2C_OFF,

USISTTIE: IUSI.USISTTIE_OFF,

USIIE: IUSI.USIIE_OFF,

USIAL: IUSI.USIAL_OFF,

USISTP: IUSI.USISTP_OFF,

USISTTIFG: IUSI.USISTTIFG_OFF,

USIIFG: IUSI.USIIFG

};

params.forceSetDefaultRegister = USI.ForceSetDefaultRegister_t[] [

// Determine if each Register needs to be forced set or not

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.interruptSource = USI.regIntVect_t[2] undefined;

// USI interrupt enables

params.name = String undefined;

// Specific peripheral name given by the device

params.owner = String undefined;

// String specifying the entity that manages the peripheral

config USI.USICKCTL // instance

index URL

USI Clock Control Register

XDCscript usage meta-domain

var params = new USI.Params;

...

params.USICKCTL = USI.USICKCTL_t {

USIDIV: IUSI.USIDIV_0,

USISSEL: IUSI.USISSEL_0,

USICKPL: IUSI.USICKPL_OFF,

USISWCLK: IUSI.USISWCLK_OFF

};

config USI.USICNT // instance

index URL

USI Bit Counter Register

XDCscript usage meta-domain

var params = new USI.Params;

...

params.USICNT = USI.USICNT_t {

USISCLREL: IUSI.USISCLREL_OFF,

USI16B: IUSI.USI16B_OFF,

USIIFGCC: IUSI.USIIFGCC_OFF,

USICNT4: IUSI.USICNT4_OFF,

USICNT3: IUSI.USICNT3_OFF,

USICNT2: IUSI.USICNT2_OFF,

USICNT1: IUSI.USICNT1_OFF,

USICNT0: IUSI.USICNT0_OFF

};

config USI.USICTL0 // instance

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USI Control Register 0

XDCscript usage meta-domain

var params = new USI.Params;

...

params.USICTL0 = USI.USICTL0_t {

USIPE7: IUSI.USIPE7_OFF,

USIPE6: IUSI.USIPE6_OFF,

USIPE5: IUSI.USIPE5_OFF,

USILSB: IUSI.USILSB_OFF,

USIMST: IUSI.USIMST_OFF,

USIGE: IUSI.USIGE_OFF,

USIOE: IUSI.USIOE_OFF,

USISWRST: IUSI.USISWRST

};

config USI.USICTL1 // instance

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USI Control Register 1

XDCscript usage meta-domain

var params = new USI.Params;

...

params.USICTL1 = USI.USICTL1_t {

USICKPH: IUSI.USICKPH_OFF,

USII2C: IUSI.USII2C_OFF,

USISTTIE: IUSI.USISTTIE_OFF,

USIIE: IUSI.USIIE_OFF,

USIAL: IUSI.USIAL_OFF,

USISTP: IUSI.USISTP_OFF,

USISTTIFG: IUSI.USISTTIFG_OFF,

USIIFG: IUSI.USIIFG

};

config USI.forceSetDefaultRegister // instance

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Determine if each Register needs to be forced set or not

XDCscript usage meta-domain

var params = new USI.Params;

...

const params.forceSetDefaultRegister = USI.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

config USI.interruptSource // instance

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USI interrupt enables

XDCscript usage meta-domain

var params = new USI.Params;

...

params.interruptSource = USI.regIntVect_t[2] undefined;

config USI.name // instance

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Specific peripheral name given by the device

XDCscript usage meta-domain

var params = new USI.Params;

...

params.name = String undefined;

DETAILS

Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.

config USI.owner // instance

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String specifying the entity that manages the peripheral

XDCscript usage meta-domain

var params = new USI.Params;

...

params.owner = String undefined;

Instance Creation

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XDCscript usage meta-domain

var params = new USI.Params;

// Allocate instance config-params