interface xdc.runtime.knl.ICacheSupport
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Interface for OS specific back-end

The xdc.runtime.knl package contains modules that provide typical OS services. These xdc.runtime.knl modules require proxies to be bound to an OS specific delegate. This specifies the interface to be implemented by the OS specific delegate for xdc.runtime.knl.Cache module.
XDCspec summary sourced in xdc/runtime/knl/ICacheSupport.xdc
interface ICacheSupport {  ...
// inherits xdc.runtime.IModule
XDCspec declarations sourced in xdc/runtime/knl/ICacheSupport.xdc
package xdc.runtime.knl;
 
interface ICacheSupport {
module-wide config parameters
    metaonly config Types.Common$ common$// Common module configuration parameters;
module-wide functions
    Bool inv// Invalidates range of memory(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
    Bool wait// Wait for a previous cache operation to complete(Error.Block *eb);
    Bool wb// Writes a range of memory from all cache(s)(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
    Bool wbInv// Writes back and invalidates range fo memory(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
}
 
metaonly config ICacheSupport.common$  // module-wide
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Common module configuration parameters

XDCspec declarations sourced in xdc/runtime/knl/ICacheSupport.xdc
metaonly config Types.Common$ common$;
 
DETAILS
All modules have this configuration parameter. Its name contains the '$' character to ensure it does not conflict with configuration parameters declared by the module. This allows new configuration parameters to be added in the future without any chance of breaking existing modules.
 
ICacheSupport.inv()  // module-wide
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Invalidates range of memory

XDCspec declarations sourced in xdc/runtime/knl/ICacheSupport.xdc
Bool inv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
wait — wait until the operation is completed
eb — error block
DETAILS
Invalidate the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines in range are invalidated for all the 'type' caches.
RETURNS
true for success; false for error.
 
ICacheSupport.wait()  // module-wide
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Wait for a previous cache operation to complete

XDCspec declarations sourced in xdc/runtime/knl/ICacheSupport.xdc
Bool wait(Error.Block *eb);
 
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache operation is not truly complete until it has worked its way through all buffering and all memory writes have landed in the source memory.
RETURNS
true for success; false for error.
 
ICacheSupport.wb()  // module-wide
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Writes a range of memory from all cache(s)

XDCspec declarations sourced in xdc/runtime/knl/ICacheSupport.xdc
Bool wb(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
wait — wait until the operation is completed
eb — error block
DETAILS
Writes the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are left valid in the 'type' caches and the data within the range will be written to the source memory.
RETURNS
true for success; false for error.
 
ICacheSupport.wbInv()  // module-wide
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Writes back and invalidates range fo memory

XDCspec declarations sourced in xdc/runtime/knl/ICacheSupport.xdc
Bool wbInv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
 
ARGUMENTS
blockPtr — start address of range to be invalidated
byteCnt — number of bytes to be invalidated
wait — wait until the operation is completed
eb — error block
DETAILS
Writes and invalidates the range of memory within the specified starting address and byte count. The range of addresses operated on gets quantized to whole cache lines in each cache. All lines within the range are written to the source memory and then invalidated for all 'type' caches.
RETURNS
true for success; false for error.
generated on Thu, 27 Sep 2012 23:21:08 GMT