enum ADC10.ADC10BUSY_t |
|
XDCscript usage |
meta-domain |
values of type ADC10.ADC10BUSY_t
const ADC10.ADC10BUSY_OFF;
// No operation is active
const ADC10.ADC10BUSY;
// A sequence, sample, or conversion is active
enum ADC10.ADC10CT_t |
|
Data transfer modes
XDCscript usage |
meta-domain |
values of type ADC10.ADC10CT_t
const ADC10.ADC10CT_OFF;
// Data is transferred is stopped after every conversion
const ADC10.ADC10CT;
// Data is transferred continuously after every conversion
SEE
enum ADC10.ADC10DF_t |
|
ADC10 output as 2's complement
XDCscript usage |
meta-domain |
values of type ADC10.ADC10DF_t
const ADC10.ADC10DF_OFF;
// ADC10 Data Format as binary
const ADC10.ADC10DF;
// ADC10 Data Format as 2's complement
enum ADC10.ADC10DIV_t |
|
ADC10 Clock Divider
XDCscript usage |
meta-domain |
values of type ADC10.ADC10DIV_t
const ADC10.ADC10DIV_0;
// Divide by 1
const ADC10.ADC10DIV_1;
// Divide by 2
const ADC10.ADC10DIV_2;
// Divide by 3
const ADC10.ADC10DIV_3;
// Divide by 4
const ADC10.ADC10DIV_4;
// Divide by 5
const ADC10.ADC10DIV_5;
// Divide by 6
const ADC10.ADC10DIV_6;
// Divide by 7
const ADC10.ADC10DIV_7;
// Divide by 8
enum ADC10.ADC10IE_t |
|
ADC10 Interrupt Enable
XDCscript usage |
meta-domain |
values of type ADC10.ADC10IE_t
const ADC10.ADC10IE_OFF;
// Disable ADC interrupt
const ADC10.ADC10IE;
// Enable ADC interrupt
enum ADC10.ADC10IFG_t |
|
ADC10 Interrupt Flag
XDCscript usage |
meta-domain |
values of type ADC10.ADC10IFG_t
const ADC10.ADC10IFG_OFF;
// Clear ADC interrupt flag
const ADC10.ADC10IFG;
// Set ADC interrupt flag
enum ADC10.ADC10ON_t |
|
ADC10 On/Enable
XDCscript usage |
meta-domain |
values of type ADC10.ADC10ON_t
const ADC10.ADC10ON_OFF;
// Switch Off ADC10
const ADC10.ADC10ON;
// Switch On ADC10
enum ADC10.ADC10SC_t |
|
ADC10 Start Conversion
XDCscript usage |
meta-domain |
values of type ADC10.ADC10SC_t
const ADC10.ADC10SC_OFF;
// No conversion
const ADC10.ADC10SC;
// Start ADC conversion manually
enum ADC10.ADC10SHT_t |
|
ADC10 Sample Hold Select 0
XDCscript usage |
meta-domain |
values of type ADC10.ADC10SHT_t
const ADC10.ADC10SHT_0;
// 4 x ADC10CLKs
const ADC10.ADC10SHT_1;
// 8 x ADC10CLKs
const ADC10.ADC10SHT_2;
// 16 x ADC10CLKs
const ADC10.ADC10SHT_3;
// 64 x ADC10CLKs
enum ADC10.ADC10SR_t |
|
ADC10 Sampling Rate 0:200ksps / 1:50ksps
XDCscript usage |
meta-domain |
values of type ADC10.ADC10SR_t
const ADC10.ADC10SR_OFF;
// Reference buffer supports up to ~200 ksps
const ADC10.ADC10SR;
// Reference buffer supports up to ~50 ksps
enum ADC10.ADC10SSEL_t |
|
ADC10 Clock Source
XDCscript usage |
meta-domain |
values of type ADC10.ADC10SSEL_t
const ADC10.ADC10SSEL_0;
// ADC10OSC
const ADC10.ADC10SSEL_1;
// ACLK
const ADC10.ADC10SSEL_2;
// MCLK
const ADC10.ADC10SSEL_3;
// SMCLK
enum ADC10.ADC10TB_t |
|
Block data transfer modes
XDCscript usage |
meta-domain |
values of type ADC10.ADC10TB_t
const ADC10.ADC10TB_OFF;
// One-block transfer mode
const ADC10.ADC10TB;
// Two-block transfer mode
SEE
enum ADC10.CONSEQ_t |
|
Types of conversion
XDCscript usage |
meta-domain |
values of type ADC10.CONSEQ_t
const ADC10.CONSEQ_0;
// Single channel single conversion
const ADC10.CONSEQ_1;
// Sequence of channels
const ADC10.CONSEQ_2;
// Repeat single channel
const ADC10.CONSEQ_3;
// Repeat sequence of channels
enum ADC10.ENC_t |
|
ADC10 Enable Conversion
XDCscript usage |
meta-domain |
values of type ADC10.ENC_t
const ADC10.ENC_OFF;
// Disable ADC
const ADC10.ENC;
// Enable ADC
enum ADC10.INCH_t |
|
ADC10 Channel Selection
XDCscript usage |
meta-domain |
values of type ADC10.INCH_t
const ADC10.INCH_0;
// ADC Channel 0
const ADC10.INCH_1;
// ADC Channel 1
const ADC10.INCH_2;
// ADC Channel 2
const ADC10.INCH_3;
// ADC Channel 3
const ADC10.INCH_4;
// ADC Channel 4
const ADC10.INCH_5;
// ADC Channel 5
const ADC10.INCH_6;
// ADC Channel 6
const ADC10.INCH_7;
// ADC Channel 7
const ADC10.INCH_8;
// ADC VeRef+
const ADC10.INCH_9;
// ADC VeRef-
const ADC10.INCH_10;
// Temperature Sensor
const ADC10.INCH_11;
// ADC convert VCC
const ADC10.INCH_12;
// ADC Channel 12
const ADC10.INCH_13;
// ADC Channel 13
const ADC10.INCH_14;
// ADC Channel 14
const ADC10.INCH_15;
// ADC Channel 15
enum ADC10.ISSH_t |
|
ADC10 input signal inversion
XDCscript usage |
meta-domain |
values of type ADC10.ISSH_t
const ADC10.ISSH_OFF;
// Input signal not inverted
const ADC10.ISSH;
// Input signal inverted
enum ADC10.MSC_t |
|
ADC10 Multiple SampleConversion
XDCscript usage |
meta-domain |
values of type ADC10.MSC_t
const ADC10.MSC_OFF;
// Disable multiple sample and conversion
const ADC10.MSC;
// Enable multiple sample and conversion
enum ADC10.REF2_5V_t |
|
ADC10 Ref 0:1.5V / 1:2.5V
XDCscript usage |
meta-domain |
values of type ADC10.REF2_5V_t
const ADC10.REF2_5V_OFF;
// Set reference voltage generator = 1.5V
const ADC10.REF2_5V;
// Set reference voltage generator = 2.5V
enum ADC10.REFBURST_t |
|
ADC10 Reference Burst Mode
XDCscript usage |
meta-domain |
values of type ADC10.REFBURST_t
const ADC10.REFBURST_OFF;
// Reference buffer on continuously
const ADC10.REFBURST;
// Reference buffer on only during sample-and-conversion
enum ADC10.REFON_t |
|
ADC10 Reference on
XDCscript usage |
meta-domain |
values of type ADC10.REFON_t
const ADC10.REFON_OFF;
// Disable ADC reference generator
const ADC10.REFON;
// Enable ADC reference generator
enum ADC10.REFOUT_t |
|
ADC10 Enable output of Ref
XDCscript usage |
meta-domain |
values of type ADC10.REFOUT_t
const ADC10.REFOUT_OFF;
// Reference output off
const ADC10.REFOUT;
// Reference output on
enum ADC10.SHS_t |
|
ADC10 trigger
XDCscript usage |
meta-domain |
values of type ADC10.SHS_t
const ADC10.SHS_0;
// ADC10SC
const ADC10.SHS_1;
// Timer_A OUT1
const ADC10.SHS_2;
// Timer_A OUT0
const ADC10.SHS_3;
// Timer_A OUT2
enum ADC10.SREF_t |
|
ADC10 Reference Select 0
XDCscript usage |
meta-domain |
values of type ADC10.SREF_t
const ADC10.SREF_0;
// VR+ = VCC and VR- = VSS
const ADC10.SREF_1;
// VR+ = VREF+ and VR- = VSS
const ADC10.SREF_2;
// VR+ = VeREF+ and VR- = VSS
const ADC10.SREF_3;
// VR+ = Buffered VeREF+ and VR- = VSS
const ADC10.SREF_4;
// VR+ = VCC and VR- = VREF-/ VeREF-
const ADC10.SREF_5;
// VR+ = VREF+ and VR- = VREF-/ VeREF-
const ADC10.SREF_6;
// VR+ = VeREF+ and VR- = VREF-/ VeREF-
const ADC10.SREF_7;
// VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-
struct ADC10.ADC10CTL0_t |
|
ADC10 Control Register 0
XDCscript usage |
meta-domain |
var obj = new ADC10.ADC10CTL0_t;
// Start conversion. Software-controlled sample-and-conversion start.
ADC10SC and ENC may be set together with one instruction. ADC10SC is
reset automatically.
0 No sample-and-conversion start
1 Start sample-and-conversion
// Enable conversion
0 ADC10 disabled
1 ADC10 enabled
// ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion
result. It is automatically reset when the interrupt request is accepted, or it may
be reset by software. When using the DTC this flag is set when a block of
transfers is completed.
0 No interrupt pending
1 Interrupt pending
// ADC10 interrupt enable
0 Interrupt disabled
1 Interrupt enabled
// ADC10 on
0 ADC10 off
1 ADC10 on
// Reference generator on
0 Reference off
1 Reference on
// Reference-generator voltage. REFON must also be set.
0 1.5 V
1 2.5 V
// Multiple sample and conversion. Valid only for sequence or repeated modes.
0 The sampling requires a rising edge of the SHI signal to trigger each
sample-and-conversion.
1 The first rising edge of the SHI signal triggers the sampling timer, but
further sample-and-conversions are performed automatically as soon
as the prior conversion is completed
// Reference burst.
0 Reference buffer on continuously
1 Reference buffer on only during sample-and-conversion
// Reference output
0 Reference output off
1 Reference output on, use internal reference
voltage externally on pin VREF+
// ADC10 sampling rate. This bit selects the reference buffer drive capability for
the maximum sampling rate. Setting ADC10SR reduces the current
consumption of the reference buffer.
0 Reference buffer supports up to ~200 ksps
1 Reference buffer supports up to ~50 ksps
// ADC10 sample-and-hold time
00 4 x ADC10CLKs
01 8 x ADC10CLKs
10 16 x ADC10CLKs
11 64 x ADC10CLKs
// Select reference
000 VR+ = VCC and VR- = VSS
001 VR+ = VREF+ and VR- = VSS
010 VR+ = VeREF+ and VR- = VSS
011 VR+ = Buffered VeREF+ and VR- = VSS
100 VR+ = VCC and VR- = VREF-/ VeREF-
101 VR+ = VREF+ and VR- = VREF-/ VeREF-
110 VR+ = VeREF+ and VR- = VREF-/ VeREF-
111 VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-
SEE
struct ADC10.ADC10CTL1_t |
|
ADC10 Control Register 1
XDCscript usage |
meta-domain |
var obj = new ADC10.ADC10CTL1_t;
// ADC10 busy. This bit indicates an active sample or conversion operation
0 No operation is active.
1 A sequence, sample, or conversion is active
// Conversion sequence mode select
00 Single-channel-single-conversion
01 Sequence-of-channels
10 Repeat-single-channel
11 Repeat-sequence-of-channels
// ADC10 clock source select
00 ADC10OSC
01 ACLK
10 MCLK
11 SMCLK
// ADC10 clock divider
000 /1
001 /2
010 /3
011 /4
100 /5
101 /6
110 /7
111 /8
// Invert signal sample-and-hold
0 The sample-input signal is not inverted.
1 The sample-input signal is inverted
// ADC10 data format
0 Straight binary
1 2s complement
// Sample-and-hold source select
00 ADC10SC bit
01 Timer_A.OUT1
10 Timer_A.OUT0
11 Timer_A.OUT2 (Timer_A.OUT1 on MSP430x20x2 devices)
// Input channel select. These bits select the channel for a single-conversion or
the highest channel for a sequence of conversions.
0000 A0
0001 A1
0010 A2
0011 A3
0100 A4
0101 A5
0110 A6
0111 A7
1000 VeREF+
1001 VREF-/VeREF-
1010 Temperature sensor
1011 (VCC ??? VSS) / 2
1100 A12
1101 A13
1110 A14
1111 A15
SEE
struct ADC10.ADC10DTC0_t |
|
Data Transfer Control Register 0
XDCscript usage |
meta-domain |
var obj = new ADC10.ADC10DTC0_t;
// ADC10 two-block mode
0 One-block transfer mode
1 Two-block transfer mode
// ADC10 continuous transfer
0 Data transfer stops when one block (one-block mode) or two blocks
(two-block mode) have completed.
1 Data is transferred continuously. DTC operation is stopped only if
ADC10CT cleared, or ADC10SA is written to
SEE
struct ADC10.ForceSetDefaultRegister_t |
|
Force Set Default Register
XDCscript usage |
meta-domain |
var obj = new ADC10.ForceSetDefaultRegister_t;
obj.register = String ...
obj.regForceSet = Bool ...
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct ADC10.regIntVect_t |
|
Interrupt vector description
XDCscript usage |
meta-domain |
var obj = new ADC10.regIntVect_t;
obj.registerName = String ...
obj.registerDescription = String ...
obj.isrToggleString = String ...
obj.priorityName = String ...
obj.interruptEnable = Bool ...
obj.interruptHandler = Bool ...
obj.priority = Int ...
DETAILS
Type to describe a single interrupt vector pin and all its possible
configurations.
SEE
ADC10.getAll() // module-wide |
|
Find all peripherals of a certain type
XDCscript usage |
meta-domain |
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
ADC10.getRegisters() // module-wide |
|
Find all registers defined by the peripheral
XDCscript usage |
meta-domain |
ADC10.getRegisters() returns String[]
RETURNS
Returns an array of register names
Instance Config Parameters |
|
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
// Instance config-params object
params.ADC10AE0 = Bits16 0;
// Analog (Input) Enable Control Register 0
params.ADC10AE1 = Bits16 0;
// Analog (Input) Enable Control Register 1
// Control Register 0
};
// Control Register 1
};
// Data Transfer Control Register 0
};
params.ADC10DTC1 = Bits8 0;
// Data Transfer Control Register 1
params.ADC10SA = Bits16* 0x200;
// Data Transfer Start Address
// Determine if each Register needs to be forced set or not
{
register: "ADC10CTL0",
regForceSet: false
},
{
register: "ADC10CTL1",
regForceSet: false
},
{
register: "ADC10AE0",
regForceSet: false
},
{
register: "ADC10AE1",
regForceSet: false
},
{
register: "ADC10DTC0",
regForceSet: false
},
{
register: "ADC10DTC1",
regForceSet: false
},
{
register: "ADC10SA",
regForceSet: false
}
];
// ADC10 has 1 interrupt enable
params.name = String undefined;
// Specific peripheral name given by the device
params.owner = String undefined;
// String specifying the entity that manages the peripheral
config ADC10.ADC10AE0 // instance |
|
Analog (Input) Enable Control Register 0
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
params.ADC10AE0 = Bits16 0;
DETAILS
Bit n enables the corresponding pin for analog
input. Bit 0 corresponds to A0, bit 1 corresponds to A1, ...
config ADC10.ADC10AE1 // instance |
|
Analog (Input) Enable Control Register 1
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
params.ADC10AE1 = Bits16 0;
DETAILS
Bits 0, 1, 2, and 3 are reserved.
Starting with bit 4, bit n enables pin n+8 for analog
input: Bit 4 corresponds to A12, bit 5 corresponds to A13, ...
config ADC10.ADC10CTL0 // instance |
|
Control Register 0
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
};
config ADC10.ADC10CTL1 // instance |
|
Control Register 1
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
};
config ADC10.ADC10DTC0 // instance |
|
Data Transfer Control Register 0
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
};
config ADC10.ADC10DTC1 // instance |
|
Data Transfer Control Register 1
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
params.ADC10DTC1 = Bits8 0;
DETAILS
This register defines the number of transfers in each block: 0
implies DTC is disabled, 1 through 0xff are valid transfer counts.
config ADC10.ADC10SA // instance |
|
Data Transfer Start Address
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
params.ADC10SA = Bits16* 0x200;
config ADC10.forceSetDefaultRegister // instance |
|
Determine if each Register needs to be forced set or not
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
{
register: "ADC10CTL0",
regForceSet: false
},
{
register: "ADC10CTL1",
regForceSet: false
},
{
register: "ADC10AE0",
regForceSet: false
},
{
register: "ADC10AE1",
regForceSet: false
},
{
register: "ADC10DTC0",
regForceSet: false
},
{
register: "ADC10DTC1",
regForceSet: false
},
{
register: "ADC10SA",
regForceSet: false
}
];
config ADC10.interruptSource // instance |
|
ADC10 has 1 interrupt enable
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
config ADC10.name // instance |
|
Specific peripheral name given by the device
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
params.name = String undefined;
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config ADC10.owner // instance |
|
String specifying the entity that manages the peripheral
XDCscript usage |
meta-domain |
var params = new ADC10.Params;
...
params.owner = String undefined;
Instance Creation |
|
XDCscript usage |
meta-domain |
var params =
new ADC10.
Params;
// Allocate instance config-params
params.config = ...
// Assign individual configs
// Create an instance-object