enum USI.USI16B_t |
![](../../../../../Arrow_up.png) |
16-bit shift register enable
XDCscript usage |
meta-domain |
values of type USI.USI16B_t
const USI.USI16B_OFF;
// 8-bit shift register mode. Low byte register USISRL is used
const USI.USI16B;
// 16-bit shift register mode. Both high and low byte registers USISRL
and USISRH are used. USISR addresses all 16 bits simultaneously
enum USI.USIAL_t |
![](../../../../../Arrow_up.png) |
Arbitration lost
XDCscript usage |
meta-domain |
values of type USI.USIAL_t
const USI.USIAL_OFF;
// No arbitration lost condition
const USI.USIAL;
// Arbitration lost
enum USI.USICKPH_t |
![](../../../../../Arrow_up.png) |
Clock phase select
XDCscript usage |
meta-domain |
values of type USI.USICKPH_t
const USI.USICKPH_OFF;
// Data is changed on the first SCLK edge and captured on the following edge
const USI.USICKPH;
// Data is captured on the first SCLK edge and changed on the following edge
enum USI.USICKPL_t |
![](../../../../../Arrow_up.png) |
Clock polarity select
XDCscript usage |
meta-domain |
values of type USI.USICKPL_t
const USI.USICKPL_OFF;
// Inactive state is low
const USI.USICKPL;
// Inactive state is high
enum USI.USICNT0_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit0
XDCscript usage |
meta-domain |
values of type USI.USICNT0_t
const USI.USICNT0_OFF;
// USI bit count
const USI.USICNT0;
// USI bit count
enum USI.USICNT1_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit1
XDCscript usage |
meta-domain |
values of type USI.USICNT1_t
const USI.USICNT1_OFF;
// USI bit count
const USI.USICNT1;
// USI bit count
enum USI.USICNT2_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit2
XDCscript usage |
meta-domain |
values of type USI.USICNT2_t
const USI.USICNT2_OFF;
// USI bit count
const USI.USICNT2;
// USI bit count
enum USI.USICNT3_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit3
XDCscript usage |
meta-domain |
values of type USI.USICNT3_t
const USI.USICNT3_OFF;
// USI bit count
const USI.USICNT3;
// USI bit count
enum USI.USICNT4_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit4
XDCscript usage |
meta-domain |
values of type USI.USICNT4_t
const USI.USICNT4_OFF;
// USI bit count
const USI.USICNT4;
// USI bit count
enum USI.USIDIV_t |
![](../../../../../Arrow_up.png) |
Clock divider select
XDCscript usage |
meta-domain |
values of type USI.USIDIV_t
const USI.USIDIV_0;
// Divide by 1
const USI.USIDIV_1;
// Divide by 2
const USI.USIDIV_2;
// Divide by 4
const USI.USIDIV_3;
// Divide by 8
const USI.USIDIV_4;
// Divide by 16
const USI.USIDIV_5;
// Divide by 32
const USI.USIDIV_6;
// Divide by 64
const USI.USIDIV_7;
// Divide by 128
enum USI.USIGE_t |
![](../../../../../Arrow_up.png) |
Output latch control
XDCscript usage |
meta-domain |
values of type USI.USIGE_t
const USI.USIGE_OFF;
// Output latch enable depends on shift clock
const USI.USIGE;
// Output latch always enabled and transparent
enum USI.USII2C_t |
![](../../../../../Arrow_up.png) |
I2C mode enable
XDCscript usage |
meta-domain |
values of type USI.USII2C_t
const USI.USII2C_OFF;
// I2C mode disabled
const USI.USII2C;
// I2C mode enabled
enum USI.USIIE_t |
![](../../../../../Arrow_up.png) |
USI counter interrupt enable
XDCscript usage |
meta-domain |
values of type USI.USIIE_t
const USI.USIIE_OFF;
// Interrupt disabled
const USI.USIIE;
// Interrupt enabled
enum USI.USIIFGCC_t |
![](../../../../../Arrow_up.png) |
USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be
cleared automatically when USICNTx is written with a value > 0
XDCscript usage |
meta-domain |
values of type USI.USIIFGCC_t
const USI.USIIFGCC_OFF;
// USIIFG automatically cleared on USICNTx update
const USI.USIIFGCC;
// USIIFG is not cleared automatically
enum USI.USIIFG_t |
![](../../../../../Arrow_up.png) |
USI counter interrupt flag. Set when the USICNTx = 0. Automatically
cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0
XDCscript usage |
meta-domain |
values of type USI.USIIFG_t
const USI.USIIFG_OFF;
// No interrupt pending
const USI.USIIFG;
// Interrupt pending
enum USI.USILSB_t |
![](../../../../../Arrow_up.png) |
LSB first select. This bit controls the direction of the receive and transmit shift register
XDCscript usage |
meta-domain |
values of type USI.USILSB_t
const USI.USILSB_OFF;
// MSB first
const USI.USILSB;
// LSB first
enum USI.USIMST_t |
![](../../../../../Arrow_up.png) |
Master select
XDCscript usage |
meta-domain |
values of type USI.USIMST_t
const USI.USIMST_OFF;
// Slave mode
const USI.USIMST;
// Master mode
enum USI.USIOE_t |
![](../../../../../Arrow_up.png) |
Data output enable
XDCscript usage |
meta-domain |
values of type USI.USIOE_t
const USI.USIOE_OFF;
// Output disabled
const USI.USIOE;
// Output enabled
enum USI.USIPE5_t |
![](../../../../../Arrow_up.png) |
USI SCLK port enable.
Input in SPI slave mode, or I2C mode, output in SPI master mode
XDCscript usage |
meta-domain |
values of type USI.USIPE5_t
const USI.USIPE5_OFF;
// USI function disabled
const USI.USIPE5;
// USI function enabled
enum USI.USIPE6_t |
![](../../../../../Arrow_up.png) |
USI SDO/SCL port enable.
Output in SPI mode, input or open drain output in I2C mode
XDCscript usage |
meta-domain |
values of type USI.USIPE6_t
const USI.USIPE6_OFF;
// USI function disabled
const USI.USIPE6;
// USI function enabled
enum USI.USIPE7_t |
![](../../../../../Arrow_up.png) |
USI SDI/SDA port enable.
Input in SPI mode, input or open drain output in I2C mode
XDCscript usage |
meta-domain |
values of type USI.USIPE7_t
const USI.USIPE7_OFF;
// USI function disabled
const USI.USIPE7;
// USI function enabled
enum USI.USISCLREL_t |
![](../../../../../Arrow_up.png) |
SCL release. The SCL line is released from low to idle. USISCLREL is
cleared if a START condition is detected
XDCscript usage |
meta-domain |
values of type USI.USISCLREL_t
const USI.USISCLREL_OFF;
// SCL line is held low if USIIFG is set
const USI.USISCLREL;
// SCL line is released
enum USI.USISSEL_t |
![](../../../../../Arrow_up.png) |
Clock source select. Not used in slave mode
XDCscript usage |
meta-domain |
values of type USI.USISSEL_t
const USI.USISSEL_0;
// SCLK (Not used in SPI mode)
const USI.USISSEL_1;
// ACLK
const USI.USISSEL_2;
// SMCLK
const USI.USISSEL_3;
// SMCLK
const USI.USISSEL_4;
// USISWCLK bit
const USI.USISSEL_5;
// TACCR0
const USI.USISSEL_6;
// TACCR1
const USI.USISSEL_7;
// TACCR2 (Reserved on MSP430F20xx devices)
enum USI.USISTP_t |
![](../../../../../Arrow_up.png) |
STOP condition received. USISTP is automatically cleared if USICNTx is
loaded with a value > 0 when USIIFGCC = 0
XDCscript usage |
meta-domain |
values of type USI.USISTP_t
const USI.USISTP_OFF;
// No STOP condition received
const USI.USISTP;
// STOP condition received
enum USI.USISTTIE_t |
![](../../../../../Arrow_up.png) |
START condition interrupt-enable
XDCscript usage |
meta-domain |
values of type USI.USISTTIE_t
const USI.USISTTIE_OFF;
// Interrupt on START condition disabled
const USI.USISTTIE;
// Interrupt on START condition enabled
enum USI.USISTTIFG_t |
![](../../../../../Arrow_up.png) |
START condition interrupt flag
XDCscript usage |
meta-domain |
values of type USI.USISTTIFG_t
const USI.USISTTIFG_OFF;
// No START condition received. No interrupt pending
const USI.USISTTIFG;
// START condition received. Interrupt pending
enum USI.USISWCLK_t |
![](../../../../../Arrow_up.png) |
Software clock
XDCscript usage |
meta-domain |
values of type USI.USISWCLK_t
const USI.USISWCLK_OFF;
// Input clock is low
const USI.USISWCLK;
// Input clock is high
enum USI.USISWRST_t |
![](../../../../../Arrow_up.png) |
USI software reset
XDCscript usage |
meta-domain |
values of type USI.USISWRST_t
const USI.USISWRST_OFF;
// USI released for operation
const USI.USISWRST;
// USI logic held in reset state
struct USI.ForceSetDefaultRegister_t |
![](../../../../../Arrow_up.png) |
Force Set Default Register
XDCscript usage |
meta-domain |
var obj = new USI.ForceSetDefaultRegister_t;
obj.register = String ...
obj.regForceSet = Bool ...
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct USI.USICKCTL_t |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var obj = new USI.USICKCTL_t;
// Clock divider select
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
// Clock source select. Not used in slave mode.
000 SCLK (Not used in SPI mode)
001 ACLK
010 SMCLK
011 SMCLK
100 USISWCLK bit
101 TACCR0
110 TACCR1
111 TACCR2 (Reserved on MSP430F20xx devices)
// Clock polarity select
0 Inactive state is low
1 Inactive state is high
// Software clock
0 Input clock is low
1 Input clock is high
struct USI.USICNT_t |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var obj = new USI.USICNT_t;
// SCL release. The SCL line is released from low to idle. USISCLREL is
cleared if a START condition is detected.
0 SCL line is held low if USIIFG is set
1 SCL line is released
// 16-bit shift register enable
0 8-bit shift register mode. Low byte register USISRL is used.
1 16-bit shift register mode. Both high and low byte registers USISRL
and USISRH are used. USISR addresses all 16 bits simultaneously
// USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be
cleared automatically when USICNTx is written with a value > 0.
0 USIIFG automatically cleared on USICNTx update
1 USIIFG is not cleared automatically
// USI bit count bit 4
The USICNTx bits set the number of bits to be received or transmitted
// USI bit count bit 3
The USICNTx bits set the number of bits to be received or transmitted
// USI bit count bit 2
The USICNTx bits set the number of bits to be received or transmitted
// USI bit count bit 1
The USICNTx bits set the number of bits to be received or transmitted
// USI bit count bit 0
The USICNTx bits set the number of bits to be received or transmitted
struct USI.USICTL0_t |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var obj = new USI.USICTL0_t;
// USI SDI/SDA port enable.
Input in SPI mode, input or open drain output in I2C mode.
0 USI function disabled
1 USI function enabled
// USI SDO/SCL port enable.
Output in SPI mode, input or open drain output in I2C mode.
0 USI function disabled
1 USI function enabled
// USI SCLK port enable.
Input in SPI slave mode, or I2C mode, output in SPI master mode.
0 USI function disabled
1 USI function enabled
// LSB first select. This bit controls the direction of the receive and transmit shift register.
0 MSB first
1 LSB first
// Master select
0 Slave mode
1 Master mode
// Output latch control
0 Output latch enable depends on shift clock
1 Output latch always enabled and transparent
// Data output enable
0 Output disabled
1 Output enabled
// USI software reset
0 USI released for operation.
1 USI logic held in reset state
struct USI.USICTL1_t |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var obj = new USI.USICTL1_t;
// Clock phase select
0 Data is changed on the first SCLK edge and captured on the
following edge.
1 Data is captured on the first SCLK edge and changed on the
following edge
// I2C mode enable
0 I2C mode disabled
1 I2C mode enabled
// START condition interrupt-enable
0 Interrupt on START condition disabled
1 Interrupt on START condition enabled
// USI counter interrupt enable
0 Interrupt disabled
1 Interrupt enabled
// Arbitration lost
0 No arbitration lost condition
1 Arbitration lost
// STOP condition received. USISTP is automatically cleared if USICNTx is
loaded with a value > 0 when USIIFGCC = 0.
0 No STOP condition received
1 STOP condition received
// START condition interrupt flag
0 No START condition received. No interrupt pending.
1 START condition received. Interrupt pending
// USI counter interrupt flag. Set when the USICNTx = 0. Automatically
cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0.
0 No interrupt pending
1 Interrupt pending
struct USI.regIntVect_t |
![](../../../../../Arrow_up.png) |
Interrupt vector description
XDCscript usage |
meta-domain |
var obj = new USI.regIntVect_t;
obj.registerName = String ...
obj.registerDescription = String ...
obj.isrToggleString = String ...
obj.priorityName = String ...
obj.interruptEnable = Bool ...
obj.interruptHandler = Bool ...
obj.priority = Int ...
DETAILS
Type to describe a single interrupt vector pin and all its possible
configurations.
SEE
USI.getAll() // module-wide |
![](../../../../../Arrow_up.png) |
Find all peripherals of a certain type
XDCscript usage |
meta-domain |
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
USI.getRegisters() // module-wide |
![](../../../../../Arrow_up.png) |
Find all registers defined by the peripheral
XDCscript usage |
meta-domain |
USI.getRegisters() returns String[]
RETURNS
Returns an array of register names
Instance Config Parameters |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new USI.Params;
// Instance config-params object
// USI Clock Control Register
};
// USI Bit Counter Register
};
// USI Control Register 0
};
// USI Control Register 1
};
// Determine if each Register needs to be forced set or not
{
register: "USICTL0",
regForceSet: false
},
{
register: "USICTL1",
regForceSet: false
},
{
register: "USICKCTL",
regForceSet: false
},
{
register: "USICNT",
regForceSet: false
}
];
// USI interrupt enables
params.name = String undefined;
// Specific peripheral name given by the device
params.owner = String undefined;
// String specifying the entity that manages the peripheral
config USI.USICKCTL // instance |
![](../../../../../Arrow_up.png) |
USI Clock Control Register
XDCscript usage |
meta-domain |
var params = new USI.Params;
...
};
config USI.USICNT // instance |
![](../../../../../Arrow_up.png) |
USI Bit Counter Register
XDCscript usage |
meta-domain |
var params = new USI.Params;
...
};
config USI.USICTL0 // instance |
![](../../../../../Arrow_up.png) |
USI Control Register 0
XDCscript usage |
meta-domain |
var params = new USI.Params;
...
};
config USI.USICTL1 // instance |
![](../../../../../Arrow_up.png) |
USI Control Register 1
XDCscript usage |
meta-domain |
var params = new USI.Params;
...
};
config USI.forceSetDefaultRegister // instance |
![](../../../../../Arrow_up.png) |
Determine if each Register needs to be forced set or not
XDCscript usage |
meta-domain |
var params = new USI.Params;
...
{
register: "USICTL0",
regForceSet: false
},
{
register: "USICTL1",
regForceSet: false
},
{
register: "USICKCTL",
regForceSet: false
},
{
register: "USICNT",
regForceSet: false
}
];
config USI.interruptSource // instance |
![](../../../../../Arrow_up.png) |
USI interrupt enables
XDCscript usage |
meta-domain |
var params = new USI.Params;
...
config USI.name // instance |
![](../../../../../Arrow_up.png) |
Specific peripheral name given by the device
XDCscript usage |
meta-domain |
var params = new USI.Params;
...
params.name = String undefined;
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config USI.owner // instance |
![](../../../../../Arrow_up.png) |
String specifying the entity that manages the peripheral
XDCscript usage |
meta-domain |
var params = new USI.Params;
...
params.owner = String undefined;
Instance Creation |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
// Allocate instance config-params
params.config = ...
// Assign individual configs
// Create an instance-object
USI.getUSIIE() // instance |
![](../../../../../Arrow_up.png) |
Gets USIIE register
XDCscript usage |
meta-domain |
inst.getUSIIE() returns Bool
SEE
USI.getUSISTTIE() // instance |
![](../../../../../Arrow_up.png) |
Gets USISTTIE register
XDCscript usage |
meta-domain |
inst.getUSISTTIE() returns Bool
SEE
USI.setUSIIE() // instance |
![](../../../../../Arrow_up.png) |
Sets USIIE register
XDCscript usage |
meta-domain |
inst.setUSIIE(Bool set) returns Bool
SEE
USI.setUSISTTIE() // instance |
![](../../../../../Arrow_up.png) |
Sets USISTTIE register
XDCscript usage |
meta-domain |
inst.setUSISTTIE(Bool set) returns Bool
SEE