metaonly interface ti.catalog.msp430.peripherals.communication.IUSCI
index URL

Universal Serial Communication Interface

XDCspec summary sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
metaonly interface IUSCI {  ...
// inherits xdc.platform.IPeripheral
instance:  ...
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
package ti.catalog.msp430.peripherals.communication;
 
metaonly interface IUSCI inherits IPeripheral {
module-wide constants & types
    enum UC7BIT_t// Character length. Selects 7-bit or 8-bit character length {
        UC7BIT_OFF// 8-bit,
        UC7BIT// 7-bit
    };
 
    enum UCADDR_t// Address received in address-bit multiprocessor mode {
        UCADDR_OFF// Received character is data,
        UCADDR// Received character is an address
    };
 
    enum UCBRKIE_t// Receive break character interrupt-enable {
        UCBRKIE_OFF// Received break characters do not set UCAxRXIFG,
        UCBRKIE// Received break characters set UCAxRXIFG
    };
 
    enum UCBRK_t// Break detect flag {
        UCBRK_OFF// No break condition,
        UCBRK// Break condition occurred
    };
 
    enum UCBUSY_t// USCI busy. This bit indicates if a transmit or receive operation is in progress {
        UCBUSY_OFF// USCI inactive,
        UCBUSY// USCI transmitting or receiving
    };
 
    enum UCDORM_t// Dormant. Puts USCI into sleep mode {
        UCDORM_OFF// Not dormant. All received characters will set UCAxRXIFG,
        UCDORM// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
    };
 
    enum UCFE_t// Framing error flag {
        UCFE_OFF// 0 No error,
        UCFE// Character received with low stop bit
    };
 
    enum UCIDLE_t// Idle line detected in idle-line multiprocessor mode {
        UCIDLE_OFF// No idle line detected,
        UCIDLE// Idle line detected
    };
 
    enum UCLISTEN_t// Listen enable. The UCLISTEN bit selects loopback mode {
        UCLISTEN_OFF// Disabled,
        UCLISTEN// Enabled. UCAxTXD is internally fed back to the receiver
    };
 
    enum UCMODE_SYNC_t// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1 {
        UCMODE_0// 3-Pin SPI,
        UCMODE_1// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1,
        UCMODE_2// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0,
        UCMODE_3// I2C Mode
    };
 
    enum UCMSB_t// MSB first select. Controls the direction of the receive and transmit shift register {
        UCMSB_OFF// LSB first,
        UCMSB// MSB first
    };
 
    enum UCOE_t// Overrun error flag {
        UCOE_OFF// No error,
        UCOE// Overrun error occurred
    };
 
    enum UCPE_t// Parity error flag. When UCPEN = 0, UCPE is read as 0 {
        UCPE_OFF// No error,
        UCPE// Character received with parity error
    };
 
    enum UCRXEIE_t// Receive erroneous-character interrupt-enable {
        UCRXEIE_OFF// Erroneous characters rejected and UCAxRXIFG is not set,
        UCRXEIE// Erroneous characters received will set UCAxRXIFG
    };
 
    enum UCRXERR_t// Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read {
        UCRXERR_OFF// No receive errors detected,
        UCRXERR// Receive error detected
    };
 
    enum UCSWRST_t// Software reset enable {
        UCSWRST_OFF// Disabled. USCI reset released for operation,
        UCSWRST// Enabled. USCI logic held in reset state
    };
 
    enum UCSYNC_t// Synchronous mode enable {
        UCSYNC_OFF// Asynchronous mode,
        UCSYNC// Synchronous Mode
    };
 
    enum UCTXADDR_t// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode {
        UCTXADDR_OFF// Next frame transmitted is data,
        UCTXADDR// Next frame transmitted is an address
    };
 
    enum UCTXBRK_t// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer {
        UCTXBRK_OFF// Next frame transmitted is not a break,
        UCTXBRK// Next frame transmitted is a break or a break/synch
    };
 
    typedef IPeripheral.Instance IPeripheralArray// [];
    typedef String StringArray// [];
 
    metaonly struct ForceSetDefaultRegister_t// Force Set Default Register {
        String register;
        Bool regForceSet;
    };
 
    metaonly struct regIntVect_t// Interrupt vector description {
        String registerName;
        String registerDescription;
        String isrToggleString;
        String priorityName;
        Bool interruptEnable;
        Bool interruptHandler;
        Int priority;
    };
module-wide functions
    IPeripheral.IPeripheralArray getAll// Find all peripherals of a certain type();
    IPeripheral.StringArray getRegisters// Find all registers defined by the peripheral();
 
 
instance:
per-instance config parameters
    config Float UCLKHz// Stores the UCLK external clock frequency in float = 1000000;
    config String name// Specific peripheral name given by the device;
    config String owner// String specifying the entity that manages the peripheral;
per-instance functions
    Bits8 getUCxxBR0// Returns UCxxBR0 register value based on which module();
    Bits8 getUCxxBR1// Returns UCxxBR1 register value based on which module();
    Bool getUCxxRXIE// Gets UCxxRXIE bit();
    Bool getUCxxTXIE// Gets UCxxTXIE bit();
    Void setUCxxBR0// Sets UCxxBR0 register value based on which module(Bits8 value);
    Void setUCxxBR1// Sets UCxxBR1 register value based on which module(Bits8 value);
    Bool setUCxxRXIE// Sets UCxxRXIE bit(Bool set);
    Bool setUCxxTXIE// Sets UCxxTXIE bit(Bool set);
}
 
enum IUSCI.UC7BIT_t
index URL

Character length. Selects 7-bit or 8-bit character length

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UC7BIT_t {
    UC7BIT_OFF,
    // 8-bit
    UC7BIT
    // 7-bit
};
 
 
enum IUSCI.UCADDR_t
index URL

Address received in address-bit multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCADDR_t {
    UCADDR_OFF,
    // Received character is data
    UCADDR
    // Received character is an address
};
 
 
enum IUSCI.UCBRKIE_t
index URL

Receive break character interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCBRKIE_t {
    UCBRKIE_OFF,
    // Received break characters do not set UCAxRXIFG
    UCBRKIE
    // Received break characters set UCAxRXIFG
};
 
 
enum IUSCI.UCBRK_t
index URL

Break detect flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCBRK_t {
    UCBRK_OFF,
    // No break condition
    UCBRK
    // Break condition occurred
};
 
 
enum IUSCI.UCBUSY_t
index URL

USCI busy. This bit indicates if a transmit or receive operation is in progress

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCBUSY_t {
    UCBUSY_OFF,
    // USCI inactive
    UCBUSY
    // USCI transmitting or receiving
};
 
 
enum IUSCI.UCDORM_t
index URL

Dormant. Puts USCI into sleep mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCDORM_t {
    UCDORM_OFF,
    // Not dormant. All received characters will set UCAxRXIFG
    UCDORM
    // Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
};
 
 
enum IUSCI.UCFE_t
index URL

Framing error flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCFE_t {
    UCFE_OFF,
    // 0 No error
    UCFE
    // Character received with low stop bit
};
 
 
enum IUSCI.UCIDLE_t
index URL

Idle line detected in idle-line multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCIDLE_t {
    UCIDLE_OFF,
    // No idle line detected
    UCIDLE
    // Idle line detected
};
 
 
enum IUSCI.UCLISTEN_t
index URL

Listen enable. The UCLISTEN bit selects loopback mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCLISTEN_t {
    UCLISTEN_OFF,
    // Disabled
    UCLISTEN
    // Enabled. UCAxTXD is internally fed back to the receiver
};
 
 
enum IUSCI.UCMODE_SYNC_t
index URL

USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCMODE_SYNC_t {
    UCMODE_0,
    // 3-Pin SPI
    UCMODE_1,
    // 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
    UCMODE_2,
    // 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
    UCMODE_3
    // I2C Mode
};
 
 
enum IUSCI.UCMSB_t
index URL

MSB first select. Controls the direction of the receive and transmit shift register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCMSB_t {
    UCMSB_OFF,
    // LSB first
    UCMSB
    // MSB first
};
 
 
enum IUSCI.UCOE_t
index URL

Overrun error flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCOE_t {
    UCOE_OFF,
    // No error
    UCOE
    // Overrun error occurred
};
 
 
enum IUSCI.UCPE_t
index URL

Parity error flag. When UCPEN = 0, UCPE is read as 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCPE_t {
    UCPE_OFF,
    // No error
    UCPE
    // Character received with parity error
};
 
 
enum IUSCI.UCRXEIE_t
index URL

Receive erroneous-character interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCRXEIE_t {
    UCRXEIE_OFF,
    // Erroneous characters rejected and UCAxRXIFG is not set
    UCRXEIE
    // Erroneous characters received will set UCAxRXIFG
};
 
 
enum IUSCI.UCRXERR_t
index URL

Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCRXERR_t {
    UCRXERR_OFF,
    // No receive errors detected
    UCRXERR
    // Receive error detected
};
 
 
enum IUSCI.UCSWRST_t
index URL

Software reset enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCSWRST_t {
    UCSWRST_OFF,
    // Disabled. USCI reset released for operation
    UCSWRST
    // Enabled. USCI logic held in reset state
};
 
 
enum IUSCI.UCSYNC_t
index URL

Synchronous mode enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCSYNC_t {
    UCSYNC_OFF,
    // Asynchronous mode
    UCSYNC
    // Synchronous Mode
};
 
 
enum IUSCI.UCTXADDR_t
index URL

Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCTXADDR_t {
    UCTXADDR_OFF,
    // Next frame transmitted is data
    UCTXADDR
    // Next frame transmitted is an address
};
 
 
enum IUSCI.UCTXBRK_t
index URL

Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
enum UCTXBRK_t {
    UCTXBRK_OFF,
    // Next frame transmitted is not a break
    UCTXBRK
    // Next frame transmitted is a break or a break/synch
};
 
 
typedef IUSCI.IPeripheralArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
typedef IPeripheral.Instance IPeripheralArray[];
 
 
typedef IUSCI.StringArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
typedef String StringArray[];
 
 
struct IUSCI.ForceSetDefaultRegister_t
index URL

Force Set Default Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
metaonly struct ForceSetDefaultRegister_t {
    String register;
    Bool regForceSet;
};
 
DETAILS
Type to store if each register needs to be forced initialized even if the register is in default state.
SEE
ForceSetDefaultRegister_t
 
struct IUSCI.regIntVect_t
index URL

Interrupt vector description

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
metaonly struct regIntVect_t {
    String registerName;
    String registerDescription;
    String isrToggleString;
    String priorityName;
    Bool interruptEnable;
    Bool interruptHandler;
    Int priority;
};
 
DETAILS
Type to describe a single interrupt vector pin and all its possible configurations.
SEE
regIntVect_t
 
IUSCI.getAll()  // module-wide
index URL

Find all peripherals of a certain type

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
IPeripheral.IPeripheralArray getAll();
 
DETAILS
The type of the peripherals returned is defined by the type of the caller.
RETURNS
Returns an array of IPeripheral instances
 
IUSCI.getRegisters()  // module-wide
index URL

Find all registers defined by the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
IPeripheral.StringArray getRegisters();
 
RETURNS
Returns an array of register names
 
config IUSCI.UCLKHz  // instance
index URL

Stores the UCLK external clock frequency in float

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
config Float UCLKHz = 1000000;
 
 
config IUSCI.name  // instance
index URL

Specific peripheral name given by the device

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
config String name;
 
DETAILS
Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.
 
config IUSCI.owner  // instance
index URL

String specifying the entity that manages the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
config String owner;
 
 
IUSCI.getUCxxBR0()  // instance
index URL

Returns UCxxBR0 register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
Bits8 getUCxxBR0();
 
SEE
getUCxxBR0
 
IUSCI.getUCxxBR1()  // instance
index URL

Returns UCxxBR1 register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
Bits8 getUCxxBR1();
 
SEE
getUCxxBR1
 
IUSCI.getUCxxRXIE()  // instance
index URL

Gets UCxxRXIE bit

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
Bool getUCxxRXIE();
 
SEE
getUCxxRXIE
 
IUSCI.getUCxxTXIE()  // instance
index URL

Gets UCxxTXIE bit

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
Bool getUCxxTXIE();
 
SEE
getUCxxTXIE
 
IUSCI.setUCxxBR0()  // instance
index URL

Sets UCxxBR0 register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
Void setUCxxBR0(Bits8 value);
 
SEE
setUCxxBR0
 
IUSCI.setUCxxBR1()  // instance
index URL

Sets UCxxBR1 register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
Void setUCxxBR1(Bits8 value);
 
SEE
setUCxxBR1
 
IUSCI.setUCxxRXIE()  // instance
index URL

Sets UCxxRXIE bit

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
Bool setUCxxRXIE(Bool set);
 
SEE
setUCxxRXIE
 
IUSCI.setUCxxTXIE()  // instance
index URL

Sets UCxxTXIE bit

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI.xdc
Bool setUCxxTXIE(Bool set);
 
SEE
setUCxxTXIE
generated on Fri, 14 Sep 2012 21:30:07 GMT