module ti.catalog.msp430.peripherals.clock.UCS

metaonly module ti.catalog.msp430.peripherals.clock.UCS

index URL

MSP430 Unified Clock System

XDCscript usage
Individual elements

XDCscript usage meta-domain sourced in ti/catalog/msp430/peripherals/clock/UCS.xdc

var UCS = xdc.useModule('ti.catalog.msp430.peripherals.clock.UCS');

module-wide constants & types

values of type UCS.ACLKREQEN_t// ACLK clock request enable

const UCS.ACLKREQEN_OFF// ACLK conditional requests are disabled;

const UCS.ACLKREQEN// ACLK conditional requests are enabled;

values of type UCS.DCO0_t// DCO0 Bit

const UCS.DCO0_OFF// Disable DCO0 bit;

const UCS.DCO0// Enable DCO0 bit;

values of type UCS.DCO1_t// DCO1 Bit

const UCS.DCO1_OFF// Disable DCO1 bit;

const UCS.DCO1// Enable DCO1 bit;

values of type UCS.DCO2_t// DCO2 Bit

const UCS.DCO2_OFF// Disable DCO2 bit;

const UCS.DCO2// Enable DCO2 bit;

values of type UCS.DCO3_t// DCO3 Bit

const UCS.DCO3_OFF// Disable DCO3 bit;

const UCS.DCO3// Enable DCO3 bit;

values of type UCS.DCO4_t// DCO4 Bit

const UCS.DCO4_OFF// Disable DCO4 bit;

const UCS.DCO4// Enable DCO4 bit;

values of type UCS.DCOFFG_t// DCO fault flag

const UCS.DCOFFG_OFF// No fault condition present;

const UCS.DCOFFG// DCO fault condition present;

values of type UCS.DCORSEL_t// DCO frequency range select

const UCS.DCORSEL_0// DCORSEL_0;

const UCS.DCORSEL_1// DCORSEL_1;

const UCS.DCORSEL_2// DCORSEL_2;

const UCS.DCORSEL_3// DCORSEL_3;

const UCS.DCORSEL_4// DCORSEL_4;

const UCS.DCORSEL_5// DCORSEL_5;

const UCS.DCORSEL_6// DCORSEL_6;

const UCS.DCORSEL_7// DCORSEL_7;

values of type UCS.DISMOD_t// DISMOD Bit

const UCS.DISMOD_OFF// Modulation enabled;

const UCS.DISMOD// Modulation disabled;

values of type UCS.DIVA_t// ACLK source divider

const UCS.DIVA_0// Divide by 1;

const UCS.DIVA_1// Divide by 2;

const UCS.DIVA_2// Divide by 4;

const UCS.DIVA_3// Divide by 8;

const UCS.DIVA_4// Divide by 16;

const UCS.DIVA_5// Divide by 32;

const UCS.DIVA_6// Reserved;

const UCS.DIVA_7// Reserved;

values of type UCS.DIVM_t// MCLK source divider

const UCS.DIVM_0// Divide by 1;

const UCS.DIVM_1// Divide by 2;

const UCS.DIVM_2// Divide by 4;

const UCS.DIVM_3// Divide by 8;

const UCS.DIVM_4// Divide by 16;

const UCS.DIVM_5// Divide by 32;

const UCS.DIVM_6// Reserved;

const UCS.DIVM_7// Reserved;

values of type UCS.DIVPA_t// ACLK source divider available at external pin

const UCS.DIVPA_0// Divide by 1;

const UCS.DIVPA_1// Divide by 2;

const UCS.DIVPA_2// Divide by 4;

const UCS.DIVPA_3// Divide by 8;

const UCS.DIVPA_4// Divide by 16;

const UCS.DIVPA_5// Divide by 32;

const UCS.DIVPA_6// Reserved;

const UCS.DIVPA_7// Reserved;

values of type UCS.DIVS_t// SMCLK source divider

const UCS.DIVS_0// Divide by 1;

const UCS.DIVS_1// Divide by 2;

const UCS.DIVS_2// Divide by 4;

const UCS.DIVS_3// Divide by 8;

const UCS.DIVS_4// Divide by 16;

const UCS.DIVS_5// Divide by 32;

const UCS.DIVS_6// Reserved;

const UCS.DIVS_7// Reserved;

values of type UCS.FLLD_t// FLL Loop Divider

const UCS.FLLD_0// Multiply Selected Loop Freq. 1;

const UCS.FLLD_1// Multiply Selected Loop Freq. 2;

const UCS.FLLD_2// Multiply Selected Loop Freq. 4;

const UCS.FLLD_3// Multiply Selected Loop Freq. 8;

const UCS.FLLD_4// Multiply Selected Loop Freq. 16;

const UCS.FLLD_5// Multiply Selected Loop Freq. 32;

const UCS.FLLD_6// Multiply Selected Loop Freq. 32;

const UCS.FLLD_7// Multiply Selected Loop Freq. 32;

values of type UCS.FLLN0_t// FLL Multiplier Bit 0

const UCS.FLLN0_OFF// Disable FLLN bit 0;

const UCS.FLLN0// Enable FLLN bit 0;

values of type UCS.FLLN1_t// FLL Multiplier Bit 1

const UCS.FLLN1_OFF// Disable FLLN bit 1;

const UCS.FLLN1// Enable FLLN bit 1;

values of type UCS.FLLN2_t// FLL Multiplier Bit 2

const UCS.FLLN2_OFF// Disable FLLN bit 2;

const UCS.FLLN2// Enable FLLN bit 2;

values of type UCS.FLLN3_t// FLL Multiplier Bit 3

const UCS.FLLN3_OFF// Disable FLLN bit 3;

const UCS.FLLN3// Enable FLLN bit 3;

values of type UCS.FLLN4_t// FLL Multiplier Bit 4

const UCS.FLLN4_OFF// Disable FLLN bit 4;

const UCS.FLLN4// Enable FLLN bit 4;

values of type UCS.FLLN5_t// FLL Multiplier Bit 5

const UCS.FLLN5_OFF// Disable FLLN bit 5;

const UCS.FLLN5// Enable FLLN bit 5;

values of type UCS.FLLN6_t// FLL Multiplier Bit 6

const UCS.FLLN6_OFF// Disable FLLN bit 6;

const UCS.FLLN6// Enable FLLN bit 6;

values of type UCS.FLLN7_t// FLL Multiplier Bit 7

const UCS.FLLN7_OFF// Disable FLLN bit 7;

const UCS.FLLN7// Enable FLLN bit 7;

values of type UCS.FLLN8_t// FLL Multiplier Bit 8

const UCS.FLLN8_OFF// Disable FLLN bit 8;

const UCS.FLLN8// Enable FLLN bit 8;

values of type UCS.FLLN9_t// FLL Multiplier Bit 9

const UCS.FLLN9_OFF// Disable FLLN bit 9;

const UCS.FLLN9// Enable FLLN bit 9;

values of type UCS.FLLREFDIV_t// FLL Reference Divider

const UCS.FLLREFDIV_0// f(FLLREFCLK) / 1;

const UCS.FLLREFDIV_1// f(FLLREFCLK) / 2;

const UCS.FLLREFDIV_2// f(FLLREFCLK) / 4;

const UCS.FLLREFDIV_3// f(FLLREFCLK) / 8;

const UCS.FLLREFDIV_4// f(FLLREFCLK) / 12;

const UCS.FLLREFDIV_5// f(FLLREFCLK) / 16;

const UCS.FLLREFDIV_6// Reserved;

const UCS.FLLREFDIV_7// Reserved;

values of type UCS.MCLKREQEN_t// MCLK clock request enable

const UCS.MCLKREQEN_OFF// MCLK conditional requests are disabled;

const UCS.MCLKREQEN// MCLK conditional requests are enabled;

values of type UCS.MOD0_t// MOD0 Bit

const UCS.MOD0_OFF// Disable MOD0 bit;

const UCS.MOD0// Enable MOD0 bit;

values of type UCS.MOD1_t// MOD1 Bit

const UCS.MOD1_OFF// Disable MOD1 bit;

const UCS.MOD1// Enable MOD1 bit;

values of type UCS.MOD2_t// MOD2 Bit

const UCS.MOD2_OFF// Disable MOD2 bit;

const UCS.MOD2// Enable MOD2 bit;

values of type UCS.MOD3_t// MOD3 Bit

const UCS.MOD3_OFF// Disable MOD3 bit;

const UCS.MOD3// Enable MOD3 bit;

values of type UCS.MOD4_t// MOD4 Bit

const UCS.MOD4_OFF// Disable MOD4 bit;

const UCS.MOD4// Enable MOD4 bit;

values of type UCS.MODOSCREQEN_t// MODOSC clock request enable

const UCS.MODOSCREQEN_OFF// MODOSC conditional requests are disabled;

const UCS.MODOSCREQEN// MODOSC conditional requests are enabled;

values of type UCS.SELA_t// Select the ACLK source

const UCS.SELA_0// XT1CLK;

const UCS.SELA_1// VLOCLK;

const UCS.SELA_2// REFOCLK;

const UCS.SELA_3// DCOCLK;

const UCS.SELA_4// DCOCLKDIV;

const UCS.SELA_5// XT2CLK;

const UCS.SELA_6// Reserved;

const UCS.SELA_7// Reserved;

values of type UCS.SELM_t// Select the MCLK source

const UCS.SELM_0// XT1CLK;

const UCS.SELM_1// VLOCLK;

const UCS.SELM_2// REFOCLK;

const UCS.SELM_3// DCOCLK;

const UCS.SELM_4// DCOCLKDIV;

const UCS.SELM_5// XT2CLK;

const UCS.SELM_6// Reserved;

const UCS.SELM_7// Reserved;

values of type UCS.SELREF_t// FLL Reference Select

const UCS.SELREF_0// FLL Reference by XT1CLK;

const UCS.SELREF_1// Reserved;

const UCS.SELREF_2// FLL Reference by REFOCLK;

const UCS.SELREF_3// Reserved;

const UCS.SELREF_4// Reserved;

const UCS.SELREF_5// FLL Reference by XT2CLK;

const UCS.SELREF_6// Reserved;

const UCS.SELREF_7// Reserved;

values of type UCS.SELS_t// Select the SMCLK source

const UCS.SELS_0// XT1CLK;

const UCS.SELS_1// VLOCLK;

const UCS.SELS_2// REFOCLK;

const UCS.SELS_3// DCOCLK;

const UCS.SELS_4// DCOCLKDIV;

const UCS.SELS_5// XT2CLK;

const UCS.SELS_6// Reserved;

const UCS.SELS_7// Reserved;

values of type UCS.SMCLKOFF_t// SMCLK off

const UCS.SMCLKOFF_OFF// SMCLK on;

const UCS.SMCLKOFF// SMCLK off;

values of type UCS.SMCLKREQEN_t// SMCLK clock request enable

const UCS.SMCLKREQEN_OFF// SMCLK conditional requests are disabled;

const UCS.SMCLKREQEN// SMCLK conditional requests are enabled;

values of type UCS.UCS_CLK_SOURCE_t// Select the clock source

const UCS.UCS_XT1CLK_SELECT// XT1CLK;

const UCS.UCS_VLOCLK_SELECT// VLOCLK;

const UCS.UCS_REFOCLK_SELECT// REFOCLK;

const UCS.UCS_DCOCLK_SELECT// DCOCLK;

const UCS.UCS_DCOCLKDIV_SELECT// DCOCLKDIV;

const UCS.UCS_XT2CLK_SELECT// XT2CLK;

values of type UCS.UCS_CLK_SRC_DIVIDER_t// Select clock source divider

const UCS.UCS_CLOCK_DIVIDER_1// Divide by 1;

const UCS.UCS_CLOCK_DIVIDER_2// Divide by 2;

const UCS.UCS_CLOCK_DIVIDER_4// Divide by 4;

const UCS.UCS_CLOCK_DIVIDER_8// Divide by 8;

const UCS.UCS_CLOCK_DIVIDER_12// Divide by 12;

const UCS.UCS_CLOCK_DIVIDER_16// Divide by 16;

const UCS.UCS_CLOCK_DIVIDER_32// Divide by 32;

values of type UCS.UCS_XCAP_t// XT1 oscillator capacitor select

const UCS.UCS_XCAP_0// ~ 2 pF;

const UCS.UCS_XCAP_1// ~ 5.5 pF;

const UCS.UCS_XCAP_2// ~ 8.5 pF;

const UCS.UCS_XCAP_3// ~ 12 pF;

values of type UCS.XCAP_t// XT1 oscillator capacitor select

const UCS.XCAP_0// XT1 Cap 0;

const UCS.XCAP_1// XT1 Cap 1;

const UCS.XCAP_2// XT1 Cap 2;

const UCS.XCAP_3// XT1 Cap 3;

values of type UCS.XT1BYPASSLV_t// Selects XT1 bypass input swing level

const UCS.XT1BYPASSLV_OFF// Input range from 0 to DVCC;

const UCS.XT1BYPASSLV// Input range from 0 to DVIO;

values of type UCS.XT1BYPASS_t// XT1 bypass select

const UCS.XT1BYPASS_OFF// XT1 sourced internally;

const UCS.XT1BYPASS// XT1 sourced externally from pin;

values of type UCS.XT1DRIVE_t// XT1 oscillator current

const UCS.XT1DRIVE_0// XT1 drive 0;

const UCS.XT1DRIVE_1// XT1 drive 1;

const UCS.XT1DRIVE_2// XT1 drive 2;

const UCS.XT1DRIVE_3// XT1 drive 3;

values of type UCS.XT1HFOFFG_t// XT1 high frequency oscillator fault flag

const UCS.XT1HFOFFG_OFF// No fault condition present;

const UCS.XT1HFOFFG// XT1 HF fault condition present;

values of type UCS.XT1LFOFFG_t// XT1 low frequency oscillator fault flag

const UCS.XT1LFOFFG_OFF// No fault condition present;

const UCS.XT1LFOFFG// XT1 LF fault condition present;

values of type UCS.XT1OFF_t// Turns off the XT1 oscillator

const UCS.XT1OFF_OFF// Enable XT1;

const UCS.XT1OFF// Disable XT1;

values of type UCS.XT2BYPASSLV_t// Selects XT2 bypass input swing level

const UCS.XT2BYPASSLV_OFF// Input range from 0 to DVCC;

const UCS.XT2BYPASSLV// Input range from 0 to DVIO;

values of type UCS.XT2BYPASS_t// XT2 bypass select

const UCS.XT2BYPASS_OFF// XT2 sourced internally;

const UCS.XT2BYPASS// XT2 sourced externally from pin;

values of type UCS.XT2DRIVE_t// XT2 oscillator current

const UCS.XT2DRIVE_0// 4 MHz to 8 MHz;

const UCS.XT2DRIVE_1// 8 MHz to 16 MHz;

const UCS.XT2DRIVE_2// 16 MHz to 24 MHz;

const UCS.XT2DRIVE_3// 24 MHz to 32 MHz;

values of type UCS.XT2OFFG_t// XT2 oscillator fault flag

const UCS.XT2OFFG_OFF// No fault condition present;

const UCS.XT2OFFG// XT2 fault condition present;

values of type UCS.XT2OFF_t// Turns off the XT2 oscillator

const UCS.XT2OFF_OFF// Enable XT2;

const UCS.XT2OFF// Disable XT2;

values of type UCS.XTS_t// XTS mode select

const UCS.XTS_OFF// Low Frequency;

const UCS.XTS// High Frequency;

var obj = new UCS.AvailableClockVariations_t// Available variations of clock in a device;

obj.clockType = String ...

obj.hasClock = Bool ...

var obj = new UCS.ForceSetDefaultRegister_t// Force Set Default Register;

obj.register = String ...

obj.regForceSet = Bool ...

var obj = new UCS.UCSCTL0_t// Unified Clock System Control 0 Register;

obj.DCO0// DCO tap selection bit 0 = UCS.DCO0_t ...

obj.DCO1// DCO tap selection bit 1 = UCS.DCO1_t ...

obj.DCO2// DCO tap selection bit 2 = UCS.DCO2_t ...

obj.DCO3// DCO tap selection bit 3 = UCS.DCO3_t ...

obj.DCO4// DCO tap selection bit 4 = UCS.DCO4_t ...

obj.MOD0// Modulation bit counter bit 0 = UCS.MOD0_t ...

obj.MOD1// Modulation bit counter bit 1 = UCS.MOD1_t ...

obj.MOD2// Modulation bit counter bit 2 = UCS.MOD2_t ...

obj.MOD3// Modulation bit counter bit 3 = UCS.MOD3_t ...

obj.MOD4// Modulation bit counter bit 4 = UCS.MOD4_t ...

var obj = new UCS.UCSCTL1_t// Unified Clock System Control 1 Register;

obj.DCORSEL// DCO frequency range select. These bits select the DCO frequency range of operation defined in the device-specific datasheet = UCS.DCORSEL_t ...

obj.DISMOD// Modulation. This bit enables/disables the modulation. 0 Modulation enabled 1 Modulation disabled = UCS.DISMOD_t ...

var obj = new UCS.UCSCTL2_t// Unified Clock System Control 2 Register;

obj.FLLD// FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits. 000 fDCOCLK/1 001 fDCOCLK/2 010 fDCOCLK/4 011 fDCOCLK/8 100 fDCOCLK/16 101 fDCOCLK/32 110 Reserved for future use. Defaults to fDCOCLK/32 111 Reserved for future use. Defaults to fDCOCLK/32 = UCS.FLLD_t ...

obj.FLLN0// Multiplier bit 0 = UCS.FLLN0_t ...

obj.FLLN1// Multiplier bit 1 = UCS.FLLN1_t ...

obj.FLLN2// Multiplier bit 2 = UCS.FLLN2_t ...

obj.FLLN3// Multiplier bit 3 = UCS.FLLN3_t ...

obj.FLLN4// Multiplier bit 4 = UCS.FLLN4_t ...

obj.FLLN5// Multiplier bit 5 = UCS.FLLN5_t ...

obj.FLLN6// Multiplier bit 6 = UCS.FLLN6_t ...

obj.FLLN7// Multiplier bit 7 = UCS.FLLN7_t ...

obj.FLLN8// Multiplier bit 8 = UCS.FLLN8_t ...

obj.FLLN9// Multiplier bit 9 = UCS.FLLN9_t ...

var obj = new UCS.UCSCTL3_t// Unified Clock System Control 3 Register;

obj.SELREF// FLL reference select. These bits select the FLL reference clock source. 000 XT1CLK 001 Reserved for future use. Defaults to XT1CLK. 010 REFOCLK 011 Reserved for future use. Defaults to REFOCLK. 100 Reserved for future use. Defaults to REFOCLK. 101 XT2CLK when available, otherwise REFOCLK. 110 Reserved for future use. XT2CLK when available, otherwise REFOCLK. 111 No selection. For the 'F543x and 'F541x non-A versions only, this defaults to XT2CLK. Reserved for future use. XT2CLK when available, otherwise REFOCLK = UCS.SELREF_t ...

obj.FLLREFDIV// FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the FLL reference frequency. 000 fFLLREFCLK/1 001 fFLLREFCLK/2 010 fFLLREFCLK/4 011 fFLLREFCLK/8 100 fFLLREFCLK/12 101 fFLLREFCLK/16 110 Reserved for future use. Defaults to fFLLREFCLK/16. 111 Reserved for future use. Defaults to fFLLREFCLK/16 = UCS.FLLREFDIV_t ...

var obj = new UCS.UCSCTL4_t// Unified Clock System Control 4 Register;

obj.SELA// Selects the ACLK source 000 XT1CLK 001 VLOCLK 010 REFOCLK 011 DCOCLK 100 DCOCLKDIV 101 XT2CLK when available, otherwise DCOCLKDIV 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV = UCS.SELA_t ...

obj.SELS// Selects the SMCLK source 000 XT1CLK 001 VLOCLK 010 REFOCLK 011 DCOCLK 100 DCOCLKDIV 101 XT2CLK when available, otherwise DCOCLKDIV 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV = UCS.SELS_t ...

obj.SELM// Selects the MCLK source 000 XT1CLK 001 VLOCLK 010 REFOCLK 011 DCOCLK 100 DCOCLKDIV 101 XT2CLK when available, otherwise DCOCLKDIV 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV = UCS.SELM_t ...

var obj = new UCS.UCSCTL5_t// Unified Clock System Control 5 Register;

obj.DIVPA// ACLK source divider available at external pin. Divides the frequency of ACLK and presents it to an external pin. 000 fACLK/1 001 fACLK/2 010 fACLK/4 011 fACLK/8 100 fACLK/16 101 fACLK/32 110 Reserved for future use. Defaults to fACLK/32. 111 Reserved for future use. Defaults to fACLK/32 = UCS.DIVPA_t ...

obj.DIVA// ACLK source divider. Divides the frequency of the ACLK clock source. 000 fACLK/1 001 fACLK/2 010 fACLK/4 011 fACLK/8 100 fACLK/16 101 fACLK/32 110 Reserved for future use. Defaults to fACLK/32. 111 Reserved for future use. Defaults to fACLK/32 = UCS.DIVA_t ...

obj.DIVS// SMCLK source divider 000 fSMCLK/1 001 fSMCLK/2 010 fSMCLK/4 011 fSMCLK/8 100 fSMCLK/16 101 fSMCLK/32 110 Reserved for future use. Defaults to fSMCLK/32. 111 Reserved for future use. Defaults to fSMCLK/32 = UCS.DIVS_t ...

obj.DIVM// MCLK source divider 000 fMCLK/1 001 fMCLK/2 010 fMCLK/4 011 fMCLK/8 100 fMCLK/16 101 fMCLK/32 110 Reserved for future use. Defaults to fMCLK/32. 111 Reserved for future use. Defaults to fMCLK/32 = UCS.DIVM_t ...

var obj = new UCS.UCSCTL6_t// Unified Clock System Control 6 Register;

obj.XT2DRIVE// The XT2 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. 00 Lowest current consumption. XT2 oscillator operating range is 4 MHz to 8 MHz. 01 Increased drive strength XT2 oscillator. XT2 oscillator operating range is 8 MHz to 16 MHz. 10 Increased drive capability XT2 oscillator. XT2 oscillator operating range is 16 MHz to 24 MHz. 11 Maximum drive capability and maximum current consumption for both XT2 oscillator. XT2 oscillator operating range is 24 MHz to 32 MHz = UCS.XT2DRIVE_t ...

obj.XT2BYPASS// XT2 bypass select 0 XT2 sourced internally 1 XT2 sourced externally from pin = UCS.XT2BYPASS_t ...

obj.XT2OFF// Turns off the XT2 oscillator 0 XT2 is on if XT2 is selected via the port selection and XT2 is not in bypass mode of operation. 1 XT2 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation = UCS.XT2OFF_t ...

obj.XT1DRIVE// The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. 00 Lowest current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 4 MHz to 8 MHz. 01 Increased drive strength for XT1 LF mode. XT1 oscillator operating range in HF mode is 8 MHz to 16 MHz. 10 Increased drive capability for XT1 LF mode. XT1 oscillator operating range in HF mode is 16 MHz to 24 MHz. 11 Maximum drive capability and maximum current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 24 MHz to 32 MHz = UCS.XT1DRIVE_t ...

obj.XTS// XT1 mode select 0 Low-frequency mode. XCAP bits define the capacitance at the XIN and XOUT pins. 1 High-frequency mode. XCAP bits are not used = UCS.XTS_t ...

obj.XT1BYPASS// XT1 bypass select 0 XT1 sourced internally 1 XT1 sourced externally from pin = UCS.XT1BYPASS_t ...

obj.XCAP// Oscillator capacitor selection. These bits select the capacitors applied to the LF crystal or resonator in the LF mode (XTS = 0). The effective capacitance (seen by the crystal) is Ceff (CXIN + 2 pF)/2. It is assumed that CXIN = CXOUT and that a parasitic capacitance of 2 pF is added by the package and the printed circuit board. For details about the typical internal and the effective capacitors, refer to the device-specific data sheet = UCS.XCAP_t ...

obj.SMCLKOFF// SMCLK off. This bit turns off the SMCLK. 0 SMCLK on 1 SMCLK off = UCS.SMCLKOFF_t ...

obj.XT1OFF// XT1 off. This bit turns off the XT1. 0 XT1 is on if XT1 is selected via the port selection and XT1 is not in bypass mode of operation. 1 XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation = UCS.XT1OFF_t ...

var obj = new UCS.UCSCTL7_t// Unified Clock System Control 7 Register;

obj.XT2OFFG// XT2 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT2OFFG is set if a XT2 fault condition exists. XT2OFFG can be cleared via software. If the XT2 fault condition still remains, XT2OFFG is set. 0 No fault condition occurred after the last reset. 1 XT2 fault. An XT2 fault occurred after the last reset = UCS.XT2OFFG_t ...

obj.XT1HFOFFG// XT1 oscillator fault flag (HF mode). If this bit is set, the OFIFG flag is also set. XT1HFOFFG is set if a XT1 fault condition exists. XT1HFOFFG can be cleared via software. If the XT1 fault condition still remains, XT1HFOFFG is set. 0 No fault condition occurred after the last reset. 1 XT1 fault. An XT1 fault occurred after the last reset = UCS.XT1HFOFFG_t ...

obj.XT1LFOFFG// XT1 oscillator fault flag (LF mode). If this bit is set, the OFIFG flag is also set. XT1LFOFFG is set if a XT1 fault condition exists. XT1LFOFFG can be cleared via software. If the XT1 fault condition still remains, XT1LFOFFG is set. 0 No fault condition occurred after the last reset. 1 XT1 fault (LF mode). A XT1 fault occurred after the last reset = UCS.XT1LFOFFG_t ...

obj.DCOFFG// DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or DCO = {31}. DCOFFG can be cleared via software. If the DCO fault condition still remains, DCOFFG is set. 0 No fault condition occurred after the last reset. 1 DCO fault. A DCO fault occurred after the last reset = UCS.DCOFFG_t ...

var obj = new UCS.UCSCTL8_t// Unified Clock System Control 8 Register;

obj.MODOSCREQEN// MODOSC clock request enable. Setting this enables conditional module requests for MODOSC. 0 MODOSC conditional requests are disabled. 1 MODOSC conditional requests are enabled = UCS.MODOSCREQEN_t ...

obj.SMCLKREQEN// SMCLK clock request enable. Setting this enables conditional module requests for SMCLK. 0 SMCLK conditional requests are disabled. 1 SMCLK conditional requests are enabled = UCS.SMCLKREQEN_t ...

obj.MCLKREQEN// MCLK clock request enable. Setting this enables conditional module requests for MCLK 0 MCLK conditional requests are disabled. 1 MCLK conditional requests are enabled = UCS.MCLKREQEN_t ...

obj.ACLKREQEN// ACLK clock request enable. Setting this enables conditional module requests for ACLK 0 ACLK conditional requests are disabled. 1 ACLK conditional requests are enabled = UCS.ACLKREQEN_t ...

var obj = new UCS.UCSCTL9_t// Unified Clock System Control 9 Register;

obj.XT2BYPASSLV// Selects XT2 bypass input swing level. Must be set for reduced swing operation. 0 Input range from 0 to DVCC 1 Input range from 0 to DVIO = UCS.XT2BYPASSLV_t ...

obj.XT1BYPASSLV// Selects XT1 bypass input swing level. Must be set for reduced swing operation. 0 Input range from 0 to DVCC 1 Input range from 0 to DVIO = UCS.XT1BYPASSLV_t ...

module-wide functions

UCS.getAll// Find all peripherals of a certain type() returns IPeripheral.Instance[]

UCS.getRegisters// Find all registers defined by the peripheral() returns String[]

per-instance config parameters

var params = new UCS.Params// Instance config-params object;

params.ACLKHz// ACLK frequency in Hertz = Float undefined;

params.DCOCLKDIVHz// Divided DCO clock frequency in Hertz = Float undefined;

params.DCOCLKHz// DCO clock frequency in Hertz = Float 1000000;

params.MCLKHz// MCLK frequency in Hertz = Float undefined;

params.REFOCLKHz// = Float 32768;

params.SMCLKHz// SMCLK frequency in Hertz = Float undefined;

params.UCSCTL0// Unified Clock System Control 0 Register = UCS.UCSCTL0_t {

DCO0: UCS.DCO0_OFF,

DCO1: UCS.DCO1_OFF,

DCO2: UCS.DCO2_OFF,

DCO3: UCS.DCO3_OFF,

DCO4: UCS.DCO4_OFF,

MOD0: UCS.MOD0_OFF,

MOD1: UCS.MOD1_OFF,

MOD2: UCS.MOD2_OFF,

MOD3: UCS.MOD3_OFF,

MOD4: UCS.MOD4_OFF

};

params.UCSCTL1// Unified Clock System Control 1 Register = UCS.UCSCTL1_t {

DCORSEL: UCS.DCORSEL_2,

DISMOD: UCS.DISMOD_OFF

};

params.UCSCTL2// Unified Clock System Control 2 Register = UCS.UCSCTL2_t {

FLLD: UCS.FLLD_1,

FLLN0: UCS.FLLN0,

FLLN1: UCS.FLLN1,

FLLN2: UCS.FLLN2,

FLLN3: UCS.FLLN3,

FLLN4: UCS.FLLN4,

FLLN5: UCS.FLLN5_OFF,

FLLN6: UCS.FLLN6_OFF,

FLLN7: UCS.FLLN7_OFF,

FLLN8: UCS.FLLN8_OFF,

FLLN9: UCS.FLLN9_OFF

};

params.UCSCTL3// Unified Clock System Control 3 Register = UCS.UCSCTL3_t {

SELREF: UCS.SELREF_0,

FLLREFDIV: UCS.FLLREFDIV_0

};

params.UCSCTL4// Unified Clock System Control 4 Register = UCS.UCSCTL4_t {

SELA: UCS.SELA_0,

SELS: UCS.SELS_4,

SELM: UCS.SELM_4

};

params.UCSCTL5// Unified Clock System Control 5 Register = UCS.UCSCTL5_t {

DIVPA: UCS.DIVPA_0,

DIVA: UCS.DIVA_0,

DIVS: UCS.DIVS_0,

DIVM: UCS.DIVM_0

};

params.UCSCTL6// Unified Clock System Control 6 Register = UCS.UCSCTL6_t {

XT2DRIVE: UCS.XT2DRIVE_3,

XT2BYPASS: UCS.XT2BYPASS_OFF,

XT2OFF: UCS.XT2OFF,

XT1DRIVE: UCS.XT1DRIVE_3,

XTS: UCS.XTS,

XT1BYPASS: UCS.XT1BYPASS,

XCAP: UCS.XCAP_3,

SMCLKOFF: UCS.SMCLKOFF_OFF,

XT1OFF: UCS.XT1OFF

};

params.UCSCTL7// Unified Clock System Control 7 Register = UCS.UCSCTL7_t {

XT2OFFG: UCS.XT2OFFG_OFF,

XT1HFOFFG: UCS.XT1HFOFFG_OFF,

XT1LFOFFG: UCS.XT1LFOFFG,

DCOFFG: UCS.DCOFFG

};

params.UCSCTL8// Unified Clock System Control 8 Register = UCS.UCSCTL8_t {

MODOSCREQEN: UCS.MODOSCREQEN_OFF,

SMCLKREQEN: UCS.SMCLKREQEN,

MCLKREQEN: UCS.MCLKREQEN,

ACLKREQEN: UCS.ACLKREQEN

};

params.UCSCTL9// Unified Clock System Control 9 Register = UCS.UCSCTL9_t {

XT2BYPASSLV: UCS.XT2BYPASSLV_OFF,

XT1BYPASSLV: UCS.XT1BYPASSLV_OFF

};

params.UCS_ACLKREQEN// ACLK clock request enable. Setting this enables conditional module requests for ACLK 0 ACLK conditional requests are disabled. 1 ACLK conditional requests are enabled = UCS.ACLKREQEN_t UCS.ACLKREQEN;

params.UCS_ACLK_SOURCE// ACLK clock source select = UCS.UCS_CLK_SOURCE_t UCS.UCS_XT1CLK_SELECT;

params.UCS_ACLK_SRC_DIVIDER// ACLK clock source divider select = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

params.UCS_FLL_FREQ// Set FLL target frequency = Float 0;

params.UCS_FLL_RATIO// FLLN value = UInt 31;

params.UCS_FLL_REF_CLK_SOURCE// FLL reference clock source select = UCS.UCS_CLK_SOURCE_t UCS.UCS_XT1CLK_SELECT;

params.UCS_FLL_REF_SRC_DIVIDER// FLL reference clock source divider select = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

params.UCS_MCLKREQEN// MCLK clock request enable. Setting this enables conditional module requests for MCLK 0 MCLK conditional requests are disabled. 1 MCLK conditional requests are enabled = UCS.MCLKREQEN_t UCS.MCLKREQEN;

params.UCS_MCLK_SOURCE// MCLK clock source select = UCS.UCS_CLK_SOURCE_t UCS.UCS_DCOCLKDIV_SELECT;

params.UCS_MCLK_SRC_DIVIDER// MCLK clock source divider select = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

params.UCS_MODOSCREQEN// MODOSC clock request enable. Setting this enables conditional module requests for MODOSC. 0 MODOSC conditional requests are disabled. 1 MODOSC conditional requests are enabled = UCS.MODOSCREQEN_t UCS.MODOSCREQEN_OFF;

params.UCS_PACLK_SRC_DIVIDER// External pin ACLK clock source divider select = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

params.UCS_SMCLKOFF// Turns OFF SMCLK using the SMCLKOFF bit 0 SMCLK On 1 SMCLK Off = Bool false;

params.UCS_SMCLKREQEN// SMCLK clock request enable. Setting this enables conditional module requests for SMCLK. 0 SMCLK conditional requests are disabled. 1 SMCLK conditional requests are enabled = UCS.SMCLKREQEN_t UCS.SMCLKREQEN;

params.UCS_SMCLK_SOURCE// SMCLK clock source select = UCS.UCS_CLK_SOURCE_t UCS.UCS_DCOCLKDIV_SELECT;

params.UCS_SMCLK_SRC_DIVIDER// SMCLK clock source divider select = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

params.UCS_XCAP// Set oscillator capacitor. Available only in LF mode. See device-specific datasheet for actual values = UCS.UCS_XCAP_t UCS.UCS_XCAP_3;

params.UCS_XT1BYPASS// Set XT1 in bypass mode. The frequency input at XIN1 pin requires 0 to VCC = Bool false;

params.UCS_XT1_DRIVE// Set XT1 drive strength = UCS.XT1DRIVE_t UCS.XT1DRIVE_3;

params.UCS_XT2BYPASS// Set XT2 in bypass mode. The frequency input at XIN2 pin requires 0 to VCC = Bool false;

params.UCS_XT2_DRIVE// Set XT2 drive strength = UCS.XT2DRIVE_t UCS.XT2DRIVE_3;

params.VLOCLKHz// = Float 12000;

params.WATCHCRYSTALCLKHz// = Float 32768;

params.XT1CLKHz// = Float 0;

params.XT2CLKHz// = Float 0;

params.baseAddr// Address of the peripheral's control register = UInt undefined;

params.baseAddress// UCS base address = String "__MSP430_BASEADDRESS_UCS__";

params.forceSetDefaultRegister// Determine if each Register needs to be forced set or not = UCS.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.hasAllCal// Specify if device has all calibration constants = Bool false;

params.hasHFXT1// Specify if HFXT1 is available on the device = Bool false;

params.hasRosc// Specify if Rosc is available on the device = Bool false;

params.hasVLO// Specify if VLO is available on the device = Bool false;

params.hasXT2// Specify if XT2 is available on the device = Bool false;

params.maxCpuFrequency// Maximum CPU frequency in Hertz = Float 0;

params.name// Specific peripheral name given by the device = String undefined;

params.owner// String specifying the entity that manages the peripheral = String undefined;

per-instance functions

inst.computeDCOCLKHz// Initialize to the nearest available DCO clock frequency(Float DCOCLKHz) returns Void

enum UCS.ACLKREQEN_t

index URL

ACLK clock request enable

XDCscript usage meta-domain

values of type UCS.ACLKREQEN_t

const UCS.ACLKREQEN_OFF;

// ACLK conditional requests are disabled

const UCS.ACLKREQEN;

// ACLK conditional requests are enabled

enum UCS.DCO0_t

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DCO0 Bit

XDCscript usage meta-domain

values of type UCS.DCO0_t

const UCS.DCO0_OFF;

// Disable DCO0 bit

const UCS.DCO0;

// Enable DCO0 bit

enum UCS.DCO1_t

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DCO1 Bit

XDCscript usage meta-domain

values of type UCS.DCO1_t

const UCS.DCO1_OFF;

// Disable DCO1 bit

const UCS.DCO1;

// Enable DCO1 bit

enum UCS.DCO2_t

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DCO2 Bit

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values of type UCS.DCO2_t

const UCS.DCO2_OFF;

// Disable DCO2 bit

const UCS.DCO2;

// Enable DCO2 bit

enum UCS.DCO3_t

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DCO3 Bit

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values of type UCS.DCO3_t

const UCS.DCO3_OFF;

// Disable DCO3 bit

const UCS.DCO3;

// Enable DCO3 bit

enum UCS.DCO4_t

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DCO4 Bit

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values of type UCS.DCO4_t

const UCS.DCO4_OFF;

// Disable DCO4 bit

const UCS.DCO4;

// Enable DCO4 bit

enum UCS.DCOFFG_t

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DCO fault flag

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values of type UCS.DCOFFG_t

const UCS.DCOFFG_OFF;

// No fault condition present

const UCS.DCOFFG;

// DCO fault condition present

enum UCS.DCORSEL_t

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DCO frequency range select

XDCscript usage meta-domain

values of type UCS.DCORSEL_t

const UCS.DCORSEL_0;

// DCORSEL_0

const UCS.DCORSEL_1;

// DCORSEL_1

const UCS.DCORSEL_2;

// DCORSEL_2

const UCS.DCORSEL_3;

// DCORSEL_3

const UCS.DCORSEL_4;

// DCORSEL_4

const UCS.DCORSEL_5;

// DCORSEL_5

const UCS.DCORSEL_6;

// DCORSEL_6

const UCS.DCORSEL_7;

// DCORSEL_7

enum UCS.DISMOD_t

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DISMOD Bit

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values of type UCS.DISMOD_t

const UCS.DISMOD_OFF;

// Modulation enabled

const UCS.DISMOD;

// Modulation disabled

enum UCS.DIVA_t

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ACLK source divider

XDCscript usage meta-domain

values of type UCS.DIVA_t

const UCS.DIVA_0;

// Divide by 1

const UCS.DIVA_1;

// Divide by 2

const UCS.DIVA_2;

// Divide by 4

const UCS.DIVA_3;

// Divide by 8

const UCS.DIVA_4;

// Divide by 16

const UCS.DIVA_5;

// Divide by 32

const UCS.DIVA_6;

// Reserved

const UCS.DIVA_7;

// Reserved

enum UCS.DIVM_t

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MCLK source divider

XDCscript usage meta-domain

values of type UCS.DIVM_t

const UCS.DIVM_0;

// Divide by 1

const UCS.DIVM_1;

// Divide by 2

const UCS.DIVM_2;

// Divide by 4

const UCS.DIVM_3;

// Divide by 8

const UCS.DIVM_4;

// Divide by 16

const UCS.DIVM_5;

// Divide by 32

const UCS.DIVM_6;

// Reserved

const UCS.DIVM_7;

// Reserved

enum UCS.DIVPA_t

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ACLK source divider available at external pin

XDCscript usage meta-domain

values of type UCS.DIVPA_t

const UCS.DIVPA_0;

// Divide by 1

const UCS.DIVPA_1;

// Divide by 2

const UCS.DIVPA_2;

// Divide by 4

const UCS.DIVPA_3;

// Divide by 8

const UCS.DIVPA_4;

// Divide by 16

const UCS.DIVPA_5;

// Divide by 32

const UCS.DIVPA_6;

// Reserved

const UCS.DIVPA_7;

// Reserved

enum UCS.DIVS_t

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SMCLK source divider

XDCscript usage meta-domain

values of type UCS.DIVS_t

const UCS.DIVS_0;

// Divide by 1

const UCS.DIVS_1;

// Divide by 2

const UCS.DIVS_2;

// Divide by 4

const UCS.DIVS_3;

// Divide by 8

const UCS.DIVS_4;

// Divide by 16

const UCS.DIVS_5;

// Divide by 32

const UCS.DIVS_6;

// Reserved

const UCS.DIVS_7;

// Reserved

enum UCS.FLLD_t

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FLL Loop Divider

XDCscript usage meta-domain

values of type UCS.FLLD_t

const UCS.FLLD_0;

// Multiply Selected Loop Freq. 1

const UCS.FLLD_1;

// Multiply Selected Loop Freq. 2

const UCS.FLLD_2;

// Multiply Selected Loop Freq. 4

const UCS.FLLD_3;

// Multiply Selected Loop Freq. 8

const UCS.FLLD_4;

// Multiply Selected Loop Freq. 16

const UCS.FLLD_5;

// Multiply Selected Loop Freq. 32

const UCS.FLLD_6;

// Multiply Selected Loop Freq. 32

const UCS.FLLD_7;

// Multiply Selected Loop Freq. 32

enum UCS.FLLN0_t

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FLL Multiplier Bit 0

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values of type UCS.FLLN0_t

const UCS.FLLN0_OFF;

// Disable FLLN bit 0

const UCS.FLLN0;

// Enable FLLN bit 0

enum UCS.FLLN1_t

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FLL Multiplier Bit 1

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values of type UCS.FLLN1_t

const UCS.FLLN1_OFF;

// Disable FLLN bit 1

const UCS.FLLN1;

// Enable FLLN bit 1

enum UCS.FLLN2_t

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FLL Multiplier Bit 2

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values of type UCS.FLLN2_t

const UCS.FLLN2_OFF;

// Disable FLLN bit 2

const UCS.FLLN2;

// Enable FLLN bit 2

enum UCS.FLLN3_t

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FLL Multiplier Bit 3

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values of type UCS.FLLN3_t

const UCS.FLLN3_OFF;

// Disable FLLN bit 3

const UCS.FLLN3;

// Enable FLLN bit 3

enum UCS.FLLN4_t

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FLL Multiplier Bit 4

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values of type UCS.FLLN4_t

const UCS.FLLN4_OFF;

// Disable FLLN bit 4

const UCS.FLLN4;

// Enable FLLN bit 4

enum UCS.FLLN5_t

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FLL Multiplier Bit 5

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values of type UCS.FLLN5_t

const UCS.FLLN5_OFF;

// Disable FLLN bit 5

const UCS.FLLN5;

// Enable FLLN bit 5

enum UCS.FLLN6_t

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FLL Multiplier Bit 6

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values of type UCS.FLLN6_t

const UCS.FLLN6_OFF;

// Disable FLLN bit 6

const UCS.FLLN6;

// Enable FLLN bit 6

enum UCS.FLLN7_t

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FLL Multiplier Bit 7

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values of type UCS.FLLN7_t

const UCS.FLLN7_OFF;

// Disable FLLN bit 7

const UCS.FLLN7;

// Enable FLLN bit 7

enum UCS.FLLN8_t

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FLL Multiplier Bit 8

XDCscript usage meta-domain

values of type UCS.FLLN8_t

const UCS.FLLN8_OFF;

// Disable FLLN bit 8

const UCS.FLLN8;

// Enable FLLN bit 8

enum UCS.FLLN9_t

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FLL Multiplier Bit 9

XDCscript usage meta-domain

values of type UCS.FLLN9_t

const UCS.FLLN9_OFF;

// Disable FLLN bit 9

const UCS.FLLN9;

// Enable FLLN bit 9

enum UCS.FLLREFDIV_t

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FLL Reference Divider

XDCscript usage meta-domain

values of type UCS.FLLREFDIV_t

const UCS.FLLREFDIV_0;

// f(FLLREFCLK) / 1

const UCS.FLLREFDIV_1;

// f(FLLREFCLK) / 2

const UCS.FLLREFDIV_2;

// f(FLLREFCLK) / 4

const UCS.FLLREFDIV_3;

// f(FLLREFCLK) / 8

const UCS.FLLREFDIV_4;

// f(FLLREFCLK) / 12

const UCS.FLLREFDIV_5;

// f(FLLREFCLK) / 16

const UCS.FLLREFDIV_6;

// Reserved

const UCS.FLLREFDIV_7;

// Reserved

enum UCS.MCLKREQEN_t

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MCLK clock request enable

XDCscript usage meta-domain

values of type UCS.MCLKREQEN_t

const UCS.MCLKREQEN_OFF;

// MCLK conditional requests are disabled

const UCS.MCLKREQEN;

// MCLK conditional requests are enabled

enum UCS.MOD0_t

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MOD0 Bit

XDCscript usage meta-domain

values of type UCS.MOD0_t

const UCS.MOD0_OFF;

// Disable MOD0 bit

const UCS.MOD0;

// Enable MOD0 bit

enum UCS.MOD1_t

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MOD1 Bit

XDCscript usage meta-domain

values of type UCS.MOD1_t

const UCS.MOD1_OFF;

// Disable MOD1 bit

const UCS.MOD1;

// Enable MOD1 bit

enum UCS.MOD2_t

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MOD2 Bit

XDCscript usage meta-domain

values of type UCS.MOD2_t

const UCS.MOD2_OFF;

// Disable MOD2 bit

const UCS.MOD2;

// Enable MOD2 bit

enum UCS.MOD3_t

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MOD3 Bit

XDCscript usage meta-domain

values of type UCS.MOD3_t

const UCS.MOD3_OFF;

// Disable MOD3 bit

const UCS.MOD3;

// Enable MOD3 bit

enum UCS.MOD4_t

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MOD4 Bit

XDCscript usage meta-domain

values of type UCS.MOD4_t

const UCS.MOD4_OFF;

// Disable MOD4 bit

const UCS.MOD4;

// Enable MOD4 bit

enum UCS.MODOSCREQEN_t

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MODOSC clock request enable

XDCscript usage meta-domain

values of type UCS.MODOSCREQEN_t

const UCS.MODOSCREQEN_OFF;

// MODOSC conditional requests are disabled

const UCS.MODOSCREQEN;

// MODOSC conditional requests are enabled

enum UCS.SELA_t

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Select the ACLK source

XDCscript usage meta-domain

values of type UCS.SELA_t

const UCS.SELA_0;

// XT1CLK

const UCS.SELA_1;

// VLOCLK

const UCS.SELA_2;

// REFOCLK

const UCS.SELA_3;

// DCOCLK

const UCS.SELA_4;

// DCOCLKDIV

const UCS.SELA_5;

// XT2CLK

const UCS.SELA_6;

// Reserved

const UCS.SELA_7;

// Reserved

enum UCS.SELM_t

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Select the MCLK source

XDCscript usage meta-domain

values of type UCS.SELM_t

const UCS.SELM_0;

// XT1CLK

const UCS.SELM_1;

// VLOCLK

const UCS.SELM_2;

// REFOCLK

const UCS.SELM_3;

// DCOCLK

const UCS.SELM_4;

// DCOCLKDIV

const UCS.SELM_5;

// XT2CLK

const UCS.SELM_6;

// Reserved

const UCS.SELM_7;

// Reserved

enum UCS.SELREF_t

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FLL Reference Select

XDCscript usage meta-domain

values of type UCS.SELREF_t

const UCS.SELREF_0;

// FLL Reference by XT1CLK

const UCS.SELREF_1;

// Reserved

const UCS.SELREF_2;

// FLL Reference by REFOCLK

const UCS.SELREF_3;

// Reserved

const UCS.SELREF_4;

// Reserved

const UCS.SELREF_5;

// FLL Reference by XT2CLK

const UCS.SELREF_6;

// Reserved

const UCS.SELREF_7;

// Reserved

enum UCS.SELS_t

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Select the SMCLK source

XDCscript usage meta-domain

values of type UCS.SELS_t

const UCS.SELS_0;

// XT1CLK

const UCS.SELS_1;

// VLOCLK

const UCS.SELS_2;

// REFOCLK

const UCS.SELS_3;

// DCOCLK

const UCS.SELS_4;

// DCOCLKDIV

const UCS.SELS_5;

// XT2CLK

const UCS.SELS_6;

// Reserved

const UCS.SELS_7;

// Reserved

enum UCS.SMCLKOFF_t

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SMCLK off

XDCscript usage meta-domain

values of type UCS.SMCLKOFF_t

const UCS.SMCLKOFF_OFF;

// SMCLK on

const UCS.SMCLKOFF;

// SMCLK off

enum UCS.SMCLKREQEN_t

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SMCLK clock request enable

XDCscript usage meta-domain

values of type UCS.SMCLKREQEN_t

const UCS.SMCLKREQEN_OFF;

// SMCLK conditional requests are disabled

const UCS.SMCLKREQEN;

// SMCLK conditional requests are enabled

enum UCS.UCS_CLK_SOURCE_t

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Select the clock source

XDCscript usage meta-domain

values of type UCS.UCS_CLK_SOURCE_t

const UCS.UCS_XT1CLK_SELECT;

// XT1CLK

const UCS.UCS_VLOCLK_SELECT;

// VLOCLK

const UCS.UCS_REFOCLK_SELECT;

// REFOCLK

const UCS.UCS_DCOCLK_SELECT;

// DCOCLK

const UCS.UCS_DCOCLKDIV_SELECT;

// DCOCLKDIV

const UCS.UCS_XT2CLK_SELECT;

// XT2CLK

enum UCS.UCS_CLK_SRC_DIVIDER_t

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Select clock source divider

XDCscript usage meta-domain

values of type UCS.UCS_CLK_SRC_DIVIDER_t

const UCS.UCS_CLOCK_DIVIDER_1;

// Divide by 1

const UCS.UCS_CLOCK_DIVIDER_2;

// Divide by 2

const UCS.UCS_CLOCK_DIVIDER_4;

// Divide by 4

const UCS.UCS_CLOCK_DIVIDER_8;

// Divide by 8

const UCS.UCS_CLOCK_DIVIDER_12;

// Divide by 12

const UCS.UCS_CLOCK_DIVIDER_16;

// Divide by 16

const UCS.UCS_CLOCK_DIVIDER_32;

// Divide by 32

enum UCS.UCS_XCAP_t

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XT1 oscillator capacitor select

XDCscript usage meta-domain

values of type UCS.UCS_XCAP_t

const UCS.UCS_XCAP_0;

// ~ 2 pF

const UCS.UCS_XCAP_1;

// ~ 5.5 pF

const UCS.UCS_XCAP_2;

// ~ 8.5 pF

const UCS.UCS_XCAP_3;

// ~ 12 pF

enum UCS.XCAP_t

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XT1 oscillator capacitor select

XDCscript usage meta-domain

values of type UCS.XCAP_t

const UCS.XCAP_0;

// XT1 Cap 0

const UCS.XCAP_1;

// XT1 Cap 1

const UCS.XCAP_2;

// XT1 Cap 2

const UCS.XCAP_3;

// XT1 Cap 3

enum UCS.XT1BYPASSLV_t

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Selects XT1 bypass input swing level

XDCscript usage meta-domain

values of type UCS.XT1BYPASSLV_t

const UCS.XT1BYPASSLV_OFF;

// Input range from 0 to DVCC

const UCS.XT1BYPASSLV;

// Input range from 0 to DVIO

enum UCS.XT1BYPASS_t

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XT1 bypass select

XDCscript usage meta-domain

values of type UCS.XT1BYPASS_t

const UCS.XT1BYPASS_OFF;

// XT1 sourced internally

const UCS.XT1BYPASS;

// XT1 sourced externally from pin

enum UCS.XT1DRIVE_t

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XT1 oscillator current

XDCscript usage meta-domain

values of type UCS.XT1DRIVE_t

const UCS.XT1DRIVE_0;

// XT1 drive 0

const UCS.XT1DRIVE_1;

// XT1 drive 1

const UCS.XT1DRIVE_2;

// XT1 drive 2

const UCS.XT1DRIVE_3;

// XT1 drive 3

enum UCS.XT1HFOFFG_t

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XT1 high frequency oscillator fault flag

XDCscript usage meta-domain

values of type UCS.XT1HFOFFG_t

const UCS.XT1HFOFFG_OFF;

// No fault condition present

const UCS.XT1HFOFFG;

// XT1 HF fault condition present

enum UCS.XT1LFOFFG_t

index URL

XT1 low frequency oscillator fault flag

XDCscript usage meta-domain

values of type UCS.XT1LFOFFG_t

const UCS.XT1LFOFFG_OFF;

// No fault condition present

const UCS.XT1LFOFFG;

// XT1 LF fault condition present

enum UCS.XT1OFF_t

index URL

Turns off the XT1 oscillator

XDCscript usage meta-domain

values of type UCS.XT1OFF_t

const UCS.XT1OFF_OFF;

// Enable XT1

const UCS.XT1OFF;

// Disable XT1

enum UCS.XT2BYPASSLV_t

index URL

Selects XT2 bypass input swing level

XDCscript usage meta-domain

values of type UCS.XT2BYPASSLV_t

const UCS.XT2BYPASSLV_OFF;

// Input range from 0 to DVCC

const UCS.XT2BYPASSLV;

// Input range from 0 to DVIO

enum UCS.XT2BYPASS_t

index URL

XT2 bypass select

XDCscript usage meta-domain

values of type UCS.XT2BYPASS_t

const UCS.XT2BYPASS_OFF;

// XT2 sourced internally

const UCS.XT2BYPASS;

// XT2 sourced externally from pin

enum UCS.XT2DRIVE_t

index URL

XT2 oscillator current

XDCscript usage meta-domain

values of type UCS.XT2DRIVE_t

const UCS.XT2DRIVE_0;

// 4 MHz to 8 MHz

const UCS.XT2DRIVE_1;

// 8 MHz to 16 MHz

const UCS.XT2DRIVE_2;

// 16 MHz to 24 MHz

const UCS.XT2DRIVE_3;

// 24 MHz to 32 MHz

enum UCS.XT2OFFG_t

index URL

XT2 oscillator fault flag

XDCscript usage meta-domain

values of type UCS.XT2OFFG_t

const UCS.XT2OFFG_OFF;

// No fault condition present

const UCS.XT2OFFG;

// XT2 fault condition present

enum UCS.XT2OFF_t

index URL

Turns off the XT2 oscillator

XDCscript usage meta-domain

values of type UCS.XT2OFF_t

const UCS.XT2OFF_OFF;

// Enable XT2

const UCS.XT2OFF;

// Disable XT2

enum UCS.XTS_t

index URL

XTS mode select

XDCscript usage meta-domain

values of type UCS.XTS_t

const UCS.XTS_OFF;

// Low Frequency

const UCS.XTS;

// High Frequency

struct UCS.AvailableClockVariations_t

index URL

Available variations of clock in a device

XDCscript usage meta-domain

var obj = new UCS.AvailableClockVariations_t;

obj.clockType = String ...

obj.hasClock = Bool ...

DETAILS

Stores true/false if any of the clock variations are available.

SEE

AvailableClockVariations_t

struct UCS.ForceSetDefaultRegister_t

index URL

Force Set Default Register

XDCscript usage meta-domain

var obj = new UCS.ForceSetDefaultRegister_t;

obj.register = String ...

obj.regForceSet = Bool ...

DETAILS

Type to store if each register needs to be forced initialized even if the register is in default state.

SEE

ForceSetDefaultRegister_t

struct UCS.UCSCTL0_t

index URL

Unified Clock System Control 0 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL0_t;

obj.DCO0 = UCS.DCO0_t ...

// DCO tap selection bit 0

obj.DCO1 = UCS.DCO1_t ...

// DCO tap selection bit 1

obj.DCO2 = UCS.DCO2_t ...

// DCO tap selection bit 2

obj.DCO3 = UCS.DCO3_t ...

// DCO tap selection bit 3

obj.DCO4 = UCS.DCO4_t ...

// DCO tap selection bit 4

obj.MOD0 = UCS.MOD0_t ...

// Modulation bit counter bit 0

obj.MOD1 = UCS.MOD1_t ...

// Modulation bit counter bit 1

obj.MOD2 = UCS.MOD2_t ...

// Modulation bit counter bit 2

obj.MOD3 = UCS.MOD3_t ...

// Modulation bit counter bit 3

obj.MOD4 = UCS.MOD4_t ...

// Modulation bit counter bit 4

FIELDS

DCO — DCO tap selection.

MOD — Modulation bit counter.

struct UCS.UCSCTL1_t

index URL

Unified Clock System Control 1 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL1_t;

obj.DCORSEL = UCS.DCORSEL_t ...

// DCO frequency range select. These bits select the DCO frequency range of operation defined in the device-specific datasheet

obj.DISMOD = UCS.DISMOD_t ...

// Modulation. This bit enables/disables the modulation. 0 Modulation enabled 1 Modulation disabled

FIELDS

DCORSEL — DCO frequency range select. These bits select the DCO frequency range of operation defined in the device-specific datasheet.

DISMOD — 0 Modulation enabled, 1 Modulation disabled.

struct UCS.UCSCTL2_t

index URL

Unified Clock System Control 2 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL2_t;

obj.FLLD = UCS.FLLD_t ...

// FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits. 000 fDCOCLK/1 001 fDCOCLK/2 010 fDCOCLK/4 011 fDCOCLK/8 100 fDCOCLK/16 101 fDCOCLK/32 110 Reserved for future use. Defaults to fDCOCLK/32 111 Reserved for future use. Defaults to fDCOCLK/32

obj.FLLN0 = UCS.FLLN0_t ...

// Multiplier bit 0

obj.FLLN1 = UCS.FLLN1_t ...

// Multiplier bit 1

obj.FLLN2 = UCS.FLLN2_t ...

// Multiplier bit 2

obj.FLLN3 = UCS.FLLN3_t ...

// Multiplier bit 3

obj.FLLN4 = UCS.FLLN4_t ...

// Multiplier bit 4

obj.FLLN5 = UCS.FLLN5_t ...

// Multiplier bit 5

obj.FLLN6 = UCS.FLLN6_t ...

// Multiplier bit 6

obj.FLLN7 = UCS.FLLN7_t ...

// Multiplier bit 7

obj.FLLN8 = UCS.FLLN8_t ...

// Multiplier bit 8

obj.FLLN9 = UCS.FLLN9_t ...

// Multiplier bit 9

FIELDS

FLLD — FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier for the multiplier bits.

FLLN — Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1.

struct UCS.UCSCTL3_t

index URL

Unified Clock System Control 3 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL3_t;

obj.SELREF = UCS.SELREF_t ...

// FLL reference select. These bits select the FLL reference clock source. 000 XT1CLK 001 Reserved for future use. Defaults to XT1CLK. 010 REFOCLK 011 Reserved for future use. Defaults to REFOCLK. 100 Reserved for future use. Defaults to REFOCLK. 101 XT2CLK when available, otherwise REFOCLK. 110 Reserved for future use. XT2CLK when available, otherwise REFOCLK. 111 No selection. For the 'F543x and 'F541x non-A versions only, this defaults to XT2CLK. Reserved for future use. XT2CLK when available, otherwise REFOCLK

obj.FLLREFDIV = UCS.FLLREFDIV_t ...

// FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the FLL reference frequency. 000 fFLLREFCLK/1 001 fFLLREFCLK/2 010 fFLLREFCLK/4 011 fFLLREFCLK/8 100 fFLLREFCLK/12 101 fFLLREFCLK/16 110 Reserved for future use. Defaults to fFLLREFCLK/16. 111 Reserved for future use. Defaults to fFLLREFCLK/16

FIELDS

SELREF — FLL reference select. These bits select the FLL reference clock source.

FLLREFDIV — FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the FLL reference frequency.

struct UCS.UCSCTL4_t

index URL

Unified Clock System Control 4 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL4_t;

obj.SELA = UCS.SELA_t ...

// Selects the ACLK source 000 XT1CLK 001 VLOCLK 010 REFOCLK 011 DCOCLK 100 DCOCLKDIV 101 XT2CLK when available, otherwise DCOCLKDIV 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV

obj.SELS = UCS.SELS_t ...

// Selects the SMCLK source 000 XT1CLK 001 VLOCLK 010 REFOCLK 011 DCOCLK 100 DCOCLKDIV 101 XT2CLK when available, otherwise DCOCLKDIV 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV

obj.SELM = UCS.SELM_t ...

// Selects the MCLK source 000 XT1CLK 001 VLOCLK 010 REFOCLK 011 DCOCLK 100 DCOCLKDIV 101 XT2CLK when available, otherwise DCOCLKDIV 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV

FIELDS

SELA — Selects the ACLK source

SELS — Selects the SMCLK source

SELM — Selects the MCLK source

struct UCS.UCSCTL5_t

index URL

Unified Clock System Control 5 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL5_t;

obj.DIVPA = UCS.DIVPA_t ...

// ACLK source divider available at external pin. Divides the frequency of ACLK and presents it to an external pin. 000 fACLK/1 001 fACLK/2 010 fACLK/4 011 fACLK/8 100 fACLK/16 101 fACLK/32 110 Reserved for future use. Defaults to fACLK/32. 111 Reserved for future use. Defaults to fACLK/32

obj.DIVA = UCS.DIVA_t ...

// ACLK source divider. Divides the frequency of the ACLK clock source. 000 fACLK/1 001 fACLK/2 010 fACLK/4 011 fACLK/8 100 fACLK/16 101 fACLK/32 110 Reserved for future use. Defaults to fACLK/32. 111 Reserved for future use. Defaults to fACLK/32

obj.DIVS = UCS.DIVS_t ...

// SMCLK source divider 000 fSMCLK/1 001 fSMCLK/2 010 fSMCLK/4 011 fSMCLK/8 100 fSMCLK/16 101 fSMCLK/32 110 Reserved for future use. Defaults to fSMCLK/32. 111 Reserved for future use. Defaults to fSMCLK/32

obj.DIVM = UCS.DIVM_t ...

// MCLK source divider 000 fMCLK/1 001 fMCLK/2 010 fMCLK/4 011 fMCLK/8 100 fMCLK/16 101 fMCLK/32 110 Reserved for future use. Defaults to fMCLK/32. 111 Reserved for future use. Defaults to fMCLK/32

FIELDS

SELA — Selects the ACLK source

SELS — Selects the SMCLK source

SELM — Selects the MCLK source

struct UCS.UCSCTL6_t

index URL

Unified Clock System Control 6 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL6_t;

obj.XT2DRIVE = UCS.XT2DRIVE_t ...

// The XT2 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. 00 Lowest current consumption. XT2 oscillator operating range is 4 MHz to 8 MHz. 01 Increased drive strength XT2 oscillator. XT2 oscillator operating range is 8 MHz to 16 MHz. 10 Increased drive capability XT2 oscillator. XT2 oscillator operating range is 16 MHz to 24 MHz. 11 Maximum drive capability and maximum current consumption for both XT2 oscillator. XT2 oscillator operating range is 24 MHz to 32 MHz

obj.XT2BYPASS = UCS.XT2BYPASS_t ...

// XT2 bypass select 0 XT2 sourced internally 1 XT2 sourced externally from pin

obj.XT2OFF = UCS.XT2OFF_t ...

// Turns off the XT2 oscillator 0 XT2 is on if XT2 is selected via the port selection and XT2 is not in bypass mode of operation. 1 XT2 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation

obj.XT1DRIVE = UCS.XT1DRIVE_t ...

// The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. 00 Lowest current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 4 MHz to 8 MHz. 01 Increased drive strength for XT1 LF mode. XT1 oscillator operating range in HF mode is 8 MHz to 16 MHz. 10 Increased drive capability for XT1 LF mode. XT1 oscillator operating range in HF mode is 16 MHz to 24 MHz. 11 Maximum drive capability and maximum current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 24 MHz to 32 MHz

obj.XTS = UCS.XTS_t ...

// XT1 mode select 0 Low-frequency mode. XCAP bits define the capacitance at the XIN and XOUT pins. 1 High-frequency mode. XCAP bits are not used

obj.XT1BYPASS = UCS.XT1BYPASS_t ...

// XT1 bypass select 0 XT1 sourced internally 1 XT1 sourced externally from pin

obj.XCAP = UCS.XCAP_t ...

// Oscillator capacitor selection. These bits select the capacitors applied to the LF crystal or resonator in the LF mode (XTS = 0). The effective capacitance (seen by the crystal) is Ceff (CXIN + 2 pF)/2. It is assumed that CXIN = CXOUT and that a parasitic capacitance of 2 pF is added by the package and the printed circuit board. For details about the typical internal and the effective capacitors, refer to the device-specific data sheet

obj.SMCLKOFF = UCS.SMCLKOFF_t ...

// SMCLK off. This bit turns off the SMCLK. 0 SMCLK on 1 SMCLK off

obj.XT1OFF = UCS.XT1OFF_t ...

// XT1 off. This bit turns off the XT1. 0 XT1 is on if XT1 is selected via the port selection and XT1 is not in bypass mode of operation. 1 XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation

FIELDS

SELA — Selects the ACLK source

SELS — Selects the SMCLK source

SELM — Selects the MCLK source

struct UCS.UCSCTL7_t

index URL

Unified Clock System Control 7 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL7_t;

obj.XT2OFFG = UCS.XT2OFFG_t ...

// XT2 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT2OFFG is set if a XT2 fault condition exists. XT2OFFG can be cleared via software. If the XT2 fault condition still remains, XT2OFFG is set. 0 No fault condition occurred after the last reset. 1 XT2 fault. An XT2 fault occurred after the last reset

obj.XT1HFOFFG = UCS.XT1HFOFFG_t ...

// XT1 oscillator fault flag (HF mode). If this bit is set, the OFIFG flag is also set. XT1HFOFFG is set if a XT1 fault condition exists. XT1HFOFFG can be cleared via software. If the XT1 fault condition still remains, XT1HFOFFG is set. 0 No fault condition occurred after the last reset. 1 XT1 fault. An XT1 fault occurred after the last reset

obj.XT1LFOFFG = UCS.XT1LFOFFG_t ...

// XT1 oscillator fault flag (LF mode). If this bit is set, the OFIFG flag is also set. XT1LFOFFG is set if a XT1 fault condition exists. XT1LFOFFG can be cleared via software. If the XT1 fault condition still remains, XT1LFOFFG is set. 0 No fault condition occurred after the last reset. 1 XT1 fault (LF mode). A XT1 fault occurred after the last reset

obj.DCOFFG = UCS.DCOFFG_t ...

// DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or DCO = {31}. DCOFFG can be cleared via software. If the DCO fault condition still remains, DCOFFG is set. 0 No fault condition occurred after the last reset. 1 DCO fault. A DCO fault occurred after the last reset

FIELDS

XT2OFFG — 0 No fault condition, 1 XT2 fault

XT1HFOFFG — 0 No fault condition, 1 XT1 HF fault

XT1LFOFFG — 0 No fault condition, 1 XT1 LF fault

DCOFFG — 0 No fault condition, 1 DCO fault

struct UCS.UCSCTL8_t

index URL

Unified Clock System Control 8 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL8_t;

obj.MODOSCREQEN = UCS.MODOSCREQEN_t ...

// MODOSC clock request enable. Setting this enables conditional module requests for MODOSC. 0 MODOSC conditional requests are disabled. 1 MODOSC conditional requests are enabled

obj.SMCLKREQEN = UCS.SMCLKREQEN_t ...

// SMCLK clock request enable. Setting this enables conditional module requests for SMCLK. 0 SMCLK conditional requests are disabled. 1 SMCLK conditional requests are enabled

obj.MCLKREQEN = UCS.MCLKREQEN_t ...

// MCLK clock request enable. Setting this enables conditional module requests for MCLK 0 MCLK conditional requests are disabled. 1 MCLK conditional requests are enabled

obj.ACLKREQEN = UCS.ACLKREQEN_t ...

// ACLK clock request enable. Setting this enables conditional module requests for ACLK 0 ACLK conditional requests are disabled. 1 ACLK conditional requests are enabled

FIELDS

MODOSCREQEN — 0 MODOSC conditional requests are disabled 1 MODOSC conditional requests are enabled

SMCLKREQEN — 0 SMCLK conditional requests are disabled 1 SMCLK conditional requests are enabled

MCLKREQEN — 0 MCLK conditional requests are disabled 1 MCLK conditional requests are enabled

ACLKREQEN — 0 ACLK conditional requests are disabled 1 ACLK conditional requests are enabled

struct UCS.UCSCTL9_t

index URL

Unified Clock System Control 9 Register

XDCscript usage meta-domain

var obj = new UCS.UCSCTL9_t;

obj.XT2BYPASSLV = UCS.XT2BYPASSLV_t ...

// Selects XT2 bypass input swing level. Must be set for reduced swing operation. 0 Input range from 0 to DVCC 1 Input range from 0 to DVIO

obj.XT1BYPASSLV = UCS.XT1BYPASSLV_t ...

// Selects XT1 bypass input swing level. Must be set for reduced swing operation. 0 Input range from 0 to DVCC 1 Input range from 0 to DVIO

FIELDS

XT2BYPASSLV — 0 Input range from 0 to DVCC 1 Input range from 0 to DVIO

XT1BYPASSLV — 0 Input range from 0 to DVCC 1 Input range from 0 to DVIO

UCS.getAll() // module-wide

index URL

Find all peripherals of a certain type

XDCscript usage meta-domain

UCS.getAll() returns IPeripheral.Instance[]

DETAILS

The type of the peripherals returned is defined by the type of the caller.

RETURNS

Returns an array of IPeripheral instances

UCS.getRegisters() // module-wide

index URL

Find all registers defined by the peripheral

XDCscript usage meta-domain

UCS.getRegisters() returns String[]

RETURNS

Returns an array of register names

Instance Config Parameters

index URL

XDCscript usage meta-domain

var params = new UCS.Params;

// Instance config-params object

params.ACLKHz = Float undefined;

// ACLK frequency in Hertz

params.DCOCLKDIVHz = Float undefined;

// Divided DCO clock frequency in Hertz

params.DCOCLKHz = Float 1000000;

// DCO clock frequency in Hertz

params.MCLKHz = Float undefined;

// MCLK frequency in Hertz

params.REFOCLKHz = Float 32768;

params.SMCLKHz = Float undefined;

// SMCLK frequency in Hertz

params.UCSCTL0 = UCS.UCSCTL0_t {

// Unified Clock System Control 0 Register

DCO0: UCS.DCO0_OFF,

DCO1: UCS.DCO1_OFF,

DCO2: UCS.DCO2_OFF,

DCO3: UCS.DCO3_OFF,

DCO4: UCS.DCO4_OFF,

MOD0: UCS.MOD0_OFF,

MOD1: UCS.MOD1_OFF,

MOD2: UCS.MOD2_OFF,

MOD3: UCS.MOD3_OFF,

MOD4: UCS.MOD4_OFF

};

params.UCSCTL1 = UCS.UCSCTL1_t {

// Unified Clock System Control 1 Register

DCORSEL: UCS.DCORSEL_2,

DISMOD: UCS.DISMOD_OFF

};

params.UCSCTL2 = UCS.UCSCTL2_t {

// Unified Clock System Control 2 Register

FLLD: UCS.FLLD_1,

FLLN0: UCS.FLLN0,

FLLN1: UCS.FLLN1,

FLLN2: UCS.FLLN2,

FLLN3: UCS.FLLN3,

FLLN4: UCS.FLLN4,

FLLN5: UCS.FLLN5_OFF,

FLLN6: UCS.FLLN6_OFF,

FLLN7: UCS.FLLN7_OFF,

FLLN8: UCS.FLLN8_OFF,

FLLN9: UCS.FLLN9_OFF

};

params.UCSCTL3 = UCS.UCSCTL3_t {

// Unified Clock System Control 3 Register

SELREF: UCS.SELREF_0,

FLLREFDIV: UCS.FLLREFDIV_0

};

params.UCSCTL4 = UCS.UCSCTL4_t {

// Unified Clock System Control 4 Register

SELA: UCS.SELA_0,

SELS: UCS.SELS_4,

SELM: UCS.SELM_4

};

params.UCSCTL5 = UCS.UCSCTL5_t {

// Unified Clock System Control 5 Register

DIVPA: UCS.DIVPA_0,

DIVA: UCS.DIVA_0,

DIVS: UCS.DIVS_0,

DIVM: UCS.DIVM_0

};

params.UCSCTL6 = UCS.UCSCTL6_t {

// Unified Clock System Control 6 Register

XT2DRIVE: UCS.XT2DRIVE_3,

XT2BYPASS: UCS.XT2BYPASS_OFF,

XT2OFF: UCS.XT2OFF,

XT1DRIVE: UCS.XT1DRIVE_3,

XTS: UCS.XTS,

XT1BYPASS: UCS.XT1BYPASS,

XCAP: UCS.XCAP_3,

SMCLKOFF: UCS.SMCLKOFF_OFF,

XT1OFF: UCS.XT1OFF

};

params.UCSCTL7 = UCS.UCSCTL7_t {

// Unified Clock System Control 7 Register

XT2OFFG: UCS.XT2OFFG_OFF,

XT1HFOFFG: UCS.XT1HFOFFG_OFF,

XT1LFOFFG: UCS.XT1LFOFFG,

DCOFFG: UCS.DCOFFG

};

params.UCSCTL8 = UCS.UCSCTL8_t {

// Unified Clock System Control 8 Register

MODOSCREQEN: UCS.MODOSCREQEN_OFF,

SMCLKREQEN: UCS.SMCLKREQEN,

MCLKREQEN: UCS.MCLKREQEN,

ACLKREQEN: UCS.ACLKREQEN

};

params.UCSCTL9 = UCS.UCSCTL9_t {

// Unified Clock System Control 9 Register

XT2BYPASSLV: UCS.XT2BYPASSLV_OFF,

XT1BYPASSLV: UCS.XT1BYPASSLV_OFF

};

params.UCS_ACLKREQEN = UCS.ACLKREQEN_t UCS.ACLKREQEN;

// ACLK clock request enable. Setting this enables conditional module requests for ACLK 0 ACLK conditional requests are disabled. 1 ACLK conditional requests are enabled

params.UCS_ACLK_SOURCE = UCS.UCS_CLK_SOURCE_t UCS.UCS_XT1CLK_SELECT;

// ACLK clock source select

params.UCS_ACLK_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

// ACLK clock source divider select

params.UCS_FLL_FREQ = Float 0;

// Set FLL target frequency

params.UCS_FLL_RATIO = UInt 31;

// FLLN value

params.UCS_FLL_REF_CLK_SOURCE = UCS.UCS_CLK_SOURCE_t UCS.UCS_XT1CLK_SELECT;

// FLL reference clock source select

params.UCS_FLL_REF_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

// FLL reference clock source divider select

params.UCS_MCLKREQEN = UCS.MCLKREQEN_t UCS.MCLKREQEN;

// MCLK clock request enable. Setting this enables conditional module requests for MCLK 0 MCLK conditional requests are disabled. 1 MCLK conditional requests are enabled

params.UCS_MCLK_SOURCE = UCS.UCS_CLK_SOURCE_t UCS.UCS_DCOCLKDIV_SELECT;

// MCLK clock source select

params.UCS_MCLK_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

// MCLK clock source divider select

params.UCS_MODOSCREQEN = UCS.MODOSCREQEN_t UCS.MODOSCREQEN_OFF;

// MODOSC clock request enable. Setting this enables conditional module requests for MODOSC. 0 MODOSC conditional requests are disabled. 1 MODOSC conditional requests are enabled

params.UCS_PACLK_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

// External pin ACLK clock source divider select

params.UCS_SMCLKOFF = Bool false;

// Turns OFF SMCLK using the SMCLKOFF bit 0 SMCLK On 1 SMCLK Off

params.UCS_SMCLKREQEN = UCS.SMCLKREQEN_t UCS.SMCLKREQEN;

// SMCLK clock request enable. Setting this enables conditional module requests for SMCLK. 0 SMCLK conditional requests are disabled. 1 SMCLK conditional requests are enabled

params.UCS_SMCLK_SOURCE = UCS.UCS_CLK_SOURCE_t UCS.UCS_DCOCLKDIV_SELECT;

// SMCLK clock source select

params.UCS_SMCLK_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

// SMCLK clock source divider select

params.UCS_XCAP = UCS.UCS_XCAP_t UCS.UCS_XCAP_3;

// Set oscillator capacitor. Available only in LF mode. See device-specific datasheet for actual values

params.UCS_XT1BYPASS = Bool false;

// Set XT1 in bypass mode. The frequency input at XIN1 pin requires 0 to VCC

params.UCS_XT1_DRIVE = UCS.XT1DRIVE_t UCS.XT1DRIVE_3;

// Set XT1 drive strength

params.UCS_XT2BYPASS = Bool false;

// Set XT2 in bypass mode. The frequency input at XIN2 pin requires 0 to VCC

params.UCS_XT2_DRIVE = UCS.XT2DRIVE_t UCS.XT2DRIVE_3;

// Set XT2 drive strength

params.VLOCLKHz = Float 12000;

params.WATCHCRYSTALCLKHz = Float 32768;

params.XT1CLKHz = Float 0;

params.XT2CLKHz = Float 0;

params.baseAddr = UInt undefined;

// Address of the peripheral's control register

params.baseAddress = String "__MSP430_BASEADDRESS_UCS__";

// UCS base address

params.forceSetDefaultRegister = UCS.ForceSetDefaultRegister_t[] [

// Determine if each Register needs to be forced set or not

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.hasAllCal = Bool false;

// Specify if device has all calibration constants

params.hasHFXT1 = Bool false;

// Specify if HFXT1 is available on the device

params.hasRosc = Bool false;

// Specify if Rosc is available on the device

params.hasVLO = Bool false;

// Specify if VLO is available on the device

params.hasXT2 = Bool false;

// Specify if XT2 is available on the device

params.maxCpuFrequency = Float 0;

// Maximum CPU frequency in Hertz

params.name = String undefined;

// Specific peripheral name given by the device

params.owner = String undefined;

// String specifying the entity that manages the peripheral

config UCS.ACLKHz // instance

index URL

ACLK frequency in Hertz

XDCscript usage meta-domain

var params = new UCS.Params;

...

const params.ACLKHz = Float computed value;

config UCS.DCOCLKDIVHz // instance

index URL

Divided DCO clock frequency in Hertz

XDCscript usage meta-domain

var params = new UCS.Params;

...

const params.DCOCLKDIVHz = Float computed value;

config UCS.DCOCLKHz // instance

index URL

DCO clock frequency in Hertz

XDCscript usage meta-domain

var params = new UCS.Params;

...

const params.DCOCLKHz = Float 1000000;

config UCS.MCLKHz // instance

index URL

MCLK frequency in Hertz

XDCscript usage meta-domain

var params = new UCS.Params;

...

const params.MCLKHz = Float computed value;

config UCS.REFOCLKHz // instance

index URL

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.REFOCLKHz = Float 32768;

config UCS.SMCLKHz // instance

index URL

SMCLK frequency in Hertz

XDCscript usage meta-domain

var params = new UCS.Params;

...

const params.SMCLKHz = Float computed value;

config UCS.UCSCTL0 // instance

index URL

Unified Clock System Control 0 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL0 = UCS.UCSCTL0_t {

DCO0: UCS.DCO0_OFF,

DCO1: UCS.DCO1_OFF,

DCO2: UCS.DCO2_OFF,

DCO3: UCS.DCO3_OFF,

DCO4: UCS.DCO4_OFF,

MOD0: UCS.MOD0_OFF,

MOD1: UCS.MOD1_OFF,

MOD2: UCS.MOD2_OFF,

MOD3: UCS.MOD3_OFF,

MOD4: UCS.MOD4_OFF

};

config UCS.UCSCTL1 // instance

index URL

Unified Clock System Control 1 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL1 = UCS.UCSCTL1_t {

DCORSEL: UCS.DCORSEL_2,

DISMOD: UCS.DISMOD_OFF

};

config UCS.UCSCTL2 // instance

index URL

Unified Clock System Control 2 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL2 = UCS.UCSCTL2_t {

FLLD: UCS.FLLD_1,

FLLN0: UCS.FLLN0,

FLLN1: UCS.FLLN1,

FLLN2: UCS.FLLN2,

FLLN3: UCS.FLLN3,

FLLN4: UCS.FLLN4,

FLLN5: UCS.FLLN5_OFF,

FLLN6: UCS.FLLN6_OFF,

FLLN7: UCS.FLLN7_OFF,

FLLN8: UCS.FLLN8_OFF,

FLLN9: UCS.FLLN9_OFF

};

config UCS.UCSCTL3 // instance

index URL

Unified Clock System Control 3 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL3 = UCS.UCSCTL3_t {

SELREF: UCS.SELREF_0,

FLLREFDIV: UCS.FLLREFDIV_0

};

config UCS.UCSCTL4 // instance

index URL

Unified Clock System Control 4 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL4 = UCS.UCSCTL4_t {

SELA: UCS.SELA_0,

SELS: UCS.SELS_4,

SELM: UCS.SELM_4

};

config UCS.UCSCTL5 // instance

index URL

Unified Clock System Control 5 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL5 = UCS.UCSCTL5_t {

DIVPA: UCS.DIVPA_0,

DIVA: UCS.DIVA_0,

DIVS: UCS.DIVS_0,

DIVM: UCS.DIVM_0

};

config UCS.UCSCTL6 // instance

index URL

Unified Clock System Control 6 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL6 = UCS.UCSCTL6_t {

XT2DRIVE: UCS.XT2DRIVE_3,

XT2BYPASS: UCS.XT2BYPASS_OFF,

XT2OFF: UCS.XT2OFF,

XT1DRIVE: UCS.XT1DRIVE_3,

XTS: UCS.XTS,

XT1BYPASS: UCS.XT1BYPASS,

XCAP: UCS.XCAP_3,

SMCLKOFF: UCS.SMCLKOFF_OFF,

XT1OFF: UCS.XT1OFF

};

config UCS.UCSCTL7 // instance

index URL

Unified Clock System Control 7 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL7 = UCS.UCSCTL7_t {

XT2OFFG: UCS.XT2OFFG_OFF,

XT1HFOFFG: UCS.XT1HFOFFG_OFF,

XT1LFOFFG: UCS.XT1LFOFFG,

DCOFFG: UCS.DCOFFG

};

config UCS.UCSCTL8 // instance

index URL

Unified Clock System Control 8 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL8 = UCS.UCSCTL8_t {

MODOSCREQEN: UCS.MODOSCREQEN_OFF,

SMCLKREQEN: UCS.SMCLKREQEN,

MCLKREQEN: UCS.MCLKREQEN,

ACLKREQEN: UCS.ACLKREQEN

};

config UCS.UCSCTL9 // instance

index URL

Unified Clock System Control 9 Register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCSCTL9 = UCS.UCSCTL9_t {

XT2BYPASSLV: UCS.XT2BYPASSLV_OFF,

XT1BYPASSLV: UCS.XT1BYPASSLV_OFF

};

config UCS.UCS_ACLKREQEN // instance

index URL

ACLK clock request enable. Setting this enables conditional module requests for ACLK 0 ACLK conditional requests are disabled. 1 ACLK conditional requests are enabled

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_ACLKREQEN = UCS.ACLKREQEN_t UCS.ACLKREQEN;

config UCS.UCS_ACLK_SOURCE // instance

index URL

ACLK clock source select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_ACLK_SOURCE = UCS.UCS_CLK_SOURCE_t UCS.UCS_XT1CLK_SELECT;

config UCS.UCS_ACLK_SRC_DIVIDER // instance

index URL

ACLK clock source divider select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_ACLK_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

config UCS.UCS_FLL_FREQ // instance

index URL

Set FLL target frequency

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_FLL_FREQ = Float 0;

config UCS.UCS_FLL_RATIO // instance

index URL

FLLN value

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_FLL_RATIO = UInt 31;

config UCS.UCS_FLL_REF_CLK_SOURCE // instance

index URL

FLL reference clock source select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_FLL_REF_CLK_SOURCE = UCS.UCS_CLK_SOURCE_t UCS.UCS_XT1CLK_SELECT;

config UCS.UCS_FLL_REF_SRC_DIVIDER // instance

index URL

FLL reference clock source divider select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_FLL_REF_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

config UCS.UCS_MCLKREQEN // instance

index URL

MCLK clock request enable. Setting this enables conditional module requests for MCLK 0 MCLK conditional requests are disabled. 1 MCLK conditional requests are enabled

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_MCLKREQEN = UCS.MCLKREQEN_t UCS.MCLKREQEN;

config UCS.UCS_MCLK_SOURCE // instance

index URL

MCLK clock source select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_MCLK_SOURCE = UCS.UCS_CLK_SOURCE_t UCS.UCS_DCOCLKDIV_SELECT;

config UCS.UCS_MCLK_SRC_DIVIDER // instance

index URL

MCLK clock source divider select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_MCLK_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

config UCS.UCS_MODOSCREQEN // instance

index URL

MODOSC clock request enable. Setting this enables conditional module requests for MODOSC. 0 MODOSC conditional requests are disabled. 1 MODOSC conditional requests are enabled

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_MODOSCREQEN = UCS.MODOSCREQEN_t UCS.MODOSCREQEN_OFF;

config UCS.UCS_PACLK_SRC_DIVIDER // instance

index URL

External pin ACLK clock source divider select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_PACLK_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

config UCS.UCS_SMCLKOFF // instance

index URL

Turns OFF SMCLK using the SMCLKOFF bit 0 SMCLK On 1 SMCLK Off

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_SMCLKOFF = Bool false;

config UCS.UCS_SMCLKREQEN // instance

index URL

SMCLK clock request enable. Setting this enables conditional module requests for SMCLK. 0 SMCLK conditional requests are disabled. 1 SMCLK conditional requests are enabled

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_SMCLKREQEN = UCS.SMCLKREQEN_t UCS.SMCLKREQEN;

config UCS.UCS_SMCLK_SOURCE // instance

index URL

SMCLK clock source select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_SMCLK_SOURCE = UCS.UCS_CLK_SOURCE_t UCS.UCS_DCOCLKDIV_SELECT;

config UCS.UCS_SMCLK_SRC_DIVIDER // instance

index URL

SMCLK clock source divider select

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_SMCLK_SRC_DIVIDER = UCS.UCS_CLK_SRC_DIVIDER_t UCS.UCS_CLOCK_DIVIDER_1;

config UCS.UCS_XCAP // instance

index URL

Set oscillator capacitor. Available only in LF mode. See device-specific datasheet for actual values

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_XCAP = UCS.UCS_XCAP_t UCS.UCS_XCAP_3;

config UCS.UCS_XT1BYPASS // instance

index URL

Set XT1 in bypass mode. The frequency input at XIN1 pin requires 0 to VCC

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_XT1BYPASS = Bool false;

config UCS.UCS_XT1_DRIVE // instance

index URL

Set XT1 drive strength

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_XT1_DRIVE = UCS.XT1DRIVE_t UCS.XT1DRIVE_3;

config UCS.UCS_XT2BYPASS // instance

index URL

Set XT2 in bypass mode. The frequency input at XIN2 pin requires 0 to VCC

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_XT2BYPASS = Bool false;

config UCS.UCS_XT2_DRIVE // instance

index URL

Set XT2 drive strength

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.UCS_XT2_DRIVE = UCS.XT2DRIVE_t UCS.XT2DRIVE_3;

config UCS.VLOCLKHz // instance

index URL

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.VLOCLKHz = Float 12000;

config UCS.WATCHCRYSTALCLKHz // instance

index URL

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.WATCHCRYSTALCLKHz = Float 32768;

config UCS.XT1CLKHz // instance

index URL

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.XT1CLKHz = Float 0;

config UCS.XT2CLKHz // instance

index URL

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.XT2CLKHz = Float 0;

config UCS.baseAddr // instance

index URL

Address of the peripheral's control register

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.baseAddr = UInt undefined;

DETAILS

A peripheral's registers are commonly accessed through a structure that defines the offsets of a particular register from the lowest address mapped to a peripheral. That lowest address is specified by this parameter.

config UCS.baseAddress // instance

index URL

UCS base address

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.baseAddress = String "__MSP430_BASEADDRESS_UCS__";

config UCS.forceSetDefaultRegister // instance

index URL

Determine if each Register needs to be forced set or not

XDCscript usage meta-domain

var params = new UCS.Params;

...

const params.forceSetDefaultRegister = UCS.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

config UCS.hasAllCal // instance

index URL

Specify if device has all calibration constants

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.hasAllCal = Bool false;

DETAILS

G1 devices do not.

config UCS.hasHFXT1 // instance

index URL

Specify if HFXT1 is available on the device

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.hasHFXT1 = Bool false;

DETAILS

Not all devices have high frequency clock. This specifies if it is available for a particular device.

config UCS.hasRosc // instance

index URL

Specify if Rosc is available on the device

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.hasRosc = Bool false;

DETAILS

Not all devices have Rosc circuitry. This specifies if it is available for a particular device.

config UCS.hasVLO // instance

index URL

Specify if VLO is available on the device

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.hasVLO = Bool false;

DETAILS

Not all devices have very low frequency clock VLO. This specifies if it is available for a particular device.

config UCS.hasXT2 // instance

index URL

Specify if XT2 is available on the device

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.hasXT2 = Bool false;

DETAILS

Not all devices have XT2 clock available. This specifies if it is available for a particular device.

config UCS.maxCpuFrequency // instance

index URL

Maximum CPU frequency in Hertz

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.maxCpuFrequency = Float 0;

config UCS.name // instance

index URL

Specific peripheral name given by the device

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.name = String undefined;

DETAILS

Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.

config UCS.owner // instance

index URL

String specifying the entity that manages the peripheral

XDCscript usage meta-domain

var params = new UCS.Params;

...

params.owner = String undefined;

UCS.computeDCOCLKHz() // instance

index URL

Initialize to the nearest available DCO clock frequency

XDCscript usage meta-domain

inst.computeDCOCLKHz(Float DCOCLKHz) returns Void

generated on Fri, 14 Sep 2012 21:30:02 GMT