module ti.catalog.msp430.peripherals.adc.ADC12

metaonly module ti.catalog.msp430.peripherals.adc.ADC12

index URL

MSP430 12-bit Analog to Digital Converter

XDCscript usage
Individual elements

XDCscript usage meta-domain sourced in ti/catalog/msp430/peripherals/adc/ADC12.xdc

var ADC12 = xdc.useModule('ti.catalog.msp430.peripherals.adc.ADC12');

module-wide constants & types

values of type ADC12.ADC12BUSY_t// ADC12 Busy Bit

const ADC12.ADC12BUSY_OFF;

const ADC12.ADC12BUSY;

values of type ADC12.ADC12DIV_t// ADC12DIV Bits

const ADC12.ADC12DIV_0// Divide by 1;

const ADC12.ADC12DIV_1// Divide by 2;

const ADC12.ADC12DIV_2// Divide by 3;

const ADC12.ADC12DIV_3// Divide by 4;

const ADC12.ADC12DIV_4// Divide by 5;

const ADC12.ADC12DIV_5// Divide by 6;

const ADC12.ADC12DIV_6// Divide by 7;

const ADC12.ADC12DIV_7// Divide by 8;

values of type ADC12.ADC12IE0_t// ADC12 Interrupt Enable Bit 0

const ADC12.ADC12IE0_OFF// Disable the interrupt request for the ADC12IFG0 bit;

const ADC12.ADC12IE0// Enable the interrupt request for the ADC12IFG0 bit;

values of type ADC12.ADC12IE10_t// ADC12 Interrupt Enable Bit 10

const ADC12.ADC12IE10_OFF// Disable the interrupt request for the ADC12IFG10 bit;

const ADC12.ADC12IE10// Enable the interrupt request for the ADC12IFG10 bit;

values of type ADC12.ADC12IE11_t// ADC12 Interrupt Enable Bit 11

const ADC12.ADC12IE11_OFF// Disable the interrupt request for the ADC12IFG11 bit;

const ADC12.ADC12IE11// Enable the interrupt request for the ADC12IFG11 bit;

values of type ADC12.ADC12IE12_t// ADC12 Interrupt Enable Bit 12

const ADC12.ADC12IE12_OFF// Disable the interrupt request for the ADC12IFG12 bit;

const ADC12.ADC12IE12// Enable the interrupt request for the ADC12IFG12 bit;

values of type ADC12.ADC12IE13_t// ADC12 Interrupt Enable Bit 13

const ADC12.ADC12IE13_OFF// Disable the interrupt request for the ADC12IFG13 bit;

const ADC12.ADC12IE13// Enable the interrupt request for the ADC12IFG13 bit;

values of type ADC12.ADC12IE14_t// ADC12 Interrupt Enable Bit 14

const ADC12.ADC12IE14_OFF// Disable the interrupt request for the ADC12IFG14 bit;

const ADC12.ADC12IE14// Enable the interrupt request for the ADC12IFG14 bit;

values of type ADC12.ADC12IE15_t// ADC12 Interrupt Enable Bit 15

const ADC12.ADC12IE15_OFF// Disable the interrupt request for the ADC12IFG15 bit;

const ADC12.ADC12IE15// Enable the interrupt request for the ADC12IFG15 bit;

values of type ADC12.ADC12IE1_t// ADC12 Interrupt Enable Bit 1

const ADC12.ADC12IE1_OFF// Disable the interrupt request for the ADC12IFG1 bit;

const ADC12.ADC12IE1// Enable the interrupt request for the ADC12IFG1 bit;

values of type ADC12.ADC12IE2_t// ADC12 Interrupt Enable Bit 2

const ADC12.ADC12IE2_OFF// Disable the interrupt request for the ADC12IFG2 bit;

const ADC12.ADC12IE2// Enable the interrupt request for the ADC12IFG2 bit;

values of type ADC12.ADC12IE3_t// ADC12 Interrupt Enable Bit 3

const ADC12.ADC12IE3_OFF// Disable the interrupt request for the ADC12IFG3 bit;

const ADC12.ADC12IE3// Enable the interrupt request for the ADC12IFG3 bit;

values of type ADC12.ADC12IE4_t// ADC12 Interrupt Enable Bit 4

const ADC12.ADC12IE4_OFF// Disable the interrupt request for the ADC12IFG4 bit;

const ADC12.ADC12IE4// Enable the interrupt request for the ADC12IFG4 bit;

values of type ADC12.ADC12IE5_t// ADC12 Interrupt Enable Bit 5

const ADC12.ADC12IE5_OFF// Disable the interrupt request for the ADC12IFG5 bit;

const ADC12.ADC12IE5// Enable the interrupt request for the ADC12IFG5 bit;

values of type ADC12.ADC12IE6_t// ADC12 Interrupt Enable Bit 6

const ADC12.ADC12IE6_OFF// Disable the interrupt request for the ADC12IFG6 bit;

const ADC12.ADC12IE6// Enable the interrupt request for the ADC12IFG6 bit;

values of type ADC12.ADC12IE7_t// ADC12 Interrupt Enable Bit 7

const ADC12.ADC12IE7_OFF// Disable the interrupt request for the ADC12IFG7 bit;

const ADC12.ADC12IE7// Enable the interrupt request for the ADC12IFG7 bit;

values of type ADC12.ADC12IE8_t// ADC12 Interrupt Enable Bit 8

const ADC12.ADC12IE8_OFF// Disable the interrupt request for the ADC12IFG8 bit;

const ADC12.ADC12IE8// Enable the interrupt request for the ADC12IFG8 bit;

values of type ADC12.ADC12IE9_t// ADC12 Interrupt Enable Bit 9

const ADC12.ADC12IE9_OFF// Disable the interrupt request for the ADC12IFG9 bit;

const ADC12.ADC12IE9// Enable the interrupt request for the ADC12IFG9 bit;

values of type ADC12.ADC12IV_t// ADC12IV Definitions

const ADC12.ADC12IV_NONE// No Interrupt pending;

const ADC12.ADC12IV_ADC12OVIFG// ADC12OVIFG;

const ADC12.ADC12IV_ADC12TOVIFG// ADC12TOVIFG;

const ADC12.ADC12IV_ADC12IFG0// ADC12IFG0;

const ADC12.ADC12IV_ADC12IFG1// ADC12IFG1;

const ADC12.ADC12IV_ADC12IFG2// ADC12IFG2;

const ADC12.ADC12IV_ADC12IFG3// ADC12IFG3;

const ADC12.ADC12IV_ADC12IFG4// ADC12IFG4;

const ADC12.ADC12IV_ADC12IFG5// ADC12IFG5;

const ADC12.ADC12IV_ADC12IFG6// ADC12IFG6;

const ADC12.ADC12IV_ADC12IFG7// ADC12IFG7;

const ADC12.ADC12IV_ADC12IFG8// ADC12IFG8;

const ADC12.ADC12IV_ADC12IFG9// ADC12IFG9;

const ADC12.ADC12IV_ADC12IFG10// ADC12IFG10;

const ADC12.ADC12IV_ADC12IFG11// ADC12IFG11;

const ADC12.ADC12IV_ADC12IFG12// ADC12IFG12;

const ADC12.ADC12IV_ADC12IFG13// ADC12IFG13;

const ADC12.ADC12IV_ADC12IFG14// ADC12IFG14;

const ADC12.ADC12IV_ADC12IFG15// ADC12IFG15;

values of type ADC12.ADC12ON_t// ADC12ON Bit

const ADC12.ADC12ON_OFF// ADC12 off;

const ADC12.ADC12ON// ADC12 on;

values of type ADC12.ADC12OVIE_t// ADC12OVIE Bit

const ADC12.ADC12OVIE_OFF// Overflow interrupt disabled;

const ADC12.ADC12OVIE// Overflow interrupt enabled;

values of type ADC12.ADC12SC_t// ADC12SC Bit

const ADC12.ADC12SC_OFF// No sample-and-conversion-start;

const ADC12.ADC12SC// Start sample-and-conversion;

values of type ADC12.ADC12SHT0_t// SHT0 Bits

const ADC12.SHT0_0// 4 ADC12CLK cycles;

const ADC12.SHT0_1// 8 ADC12CLK cycles;

const ADC12.SHT0_2// 16 ADC12CLK cycles;

const ADC12.SHT0_3// 32 ADC12CLK cycles;

const ADC12.SHT0_4// 64 ADC12CLK cycles;

const ADC12.SHT0_5// 96 ADC12CLK cycles;

const ADC12.SHT0_6// 128 ADC12CLK cycles;

const ADC12.SHT0_7// 192 ADC12CLK cycles;

const ADC12.SHT0_8// 256 ADC12CLK cycles;

const ADC12.SHT0_9// 384 ADC12CLK cycles;

const ADC12.SHT0_10// 512 ADC12CLK cycles;

const ADC12.SHT0_11// 768 ADC12CLK cycles;

const ADC12.SHT0_12// 1024 ADC12CLK cycles;

const ADC12.SHT0_13// 1024 ADC12CLK cycles;

const ADC12.SHT0_14// 1024 ADC12CLK cycles;

const ADC12.SHT0_15// 1024 ADC12CLK cycles;

values of type ADC12.ADC12SHT1_t// SHT1 Bits

const ADC12.SHT1_0// 4 ADC12CLK cycles;

const ADC12.SHT1_1// 8 ADC12CLK cycles;

const ADC12.SHT1_2// 16 ADC12CLK cycles;

const ADC12.SHT1_3// 32 ADC12CLK cycles;

const ADC12.SHT1_4// 64 ADC12CLK cycles;

const ADC12.SHT1_5// 96 ADC12CLK cycles;

const ADC12.SHT1_6// 128 ADC12CLK cycles;

const ADC12.SHT1_7// 192 ADC12CLK cycles;

const ADC12.SHT1_8// 256 ADC12CLK cycles;

const ADC12.SHT1_9// 384 ADC12CLK cycles;

const ADC12.SHT1_10// 512 ADC12CLK cycles;

const ADC12.SHT1_11// 768 ADC12CLK cycles;

const ADC12.SHT1_12// 1024 ADC12CLK cycles;

const ADC12.SHT1_13// 1024 ADC12CLK cycles;

const ADC12.SHT1_14// 1024 ADC12CLK cycles;

const ADC12.SHT1_15// 1024 ADC12CLK cycles;

values of type ADC12.ADC12SSEL_t// ADC12SSEL Bits

const ADC12.ADC12SSEL_0// ADC12OSC;

const ADC12.ADC12SSEL_1// ACLK;

const ADC12.ADC12SSEL_2// MCLK;

const ADC12.ADC12SSEL_3// SMCLK;

values of type ADC12.ADC12TOVIE_t// ADC12TOVIE Bit

const ADC12.ADC12TOVIE_OFF// Conversion time overflow interrupt disabled;

const ADC12.ADC12TOVIE// Conversion time overflow interrupt disabled;

values of type ADC12.CONSEQ_t// CONSEQ Bits

const ADC12.CONSEQ_0// Single channel single conversion;

const ADC12.CONSEQ_1// Sequence of channels;

const ADC12.CONSEQ_2// Repeat single channel;

const ADC12.CONSEQ_3// Repeat sequence of channels;

values of type ADC12.CSTARTADD_t// CSTARTADD Bits

const ADC12.CSTARTADD_0// ADC12MEM0;

const ADC12.CSTARTADD_1// ADC12MEM1;

const ADC12.CSTARTADD_2// ADC12MEM2;

const ADC12.CSTARTADD_3// ADC12MEM3;

const ADC12.CSTARTADD_4// ADC12MEM4;

const ADC12.CSTARTADD_5// ADC12MEM5;

const ADC12.CSTARTADD_6// ADC12MEM6;

const ADC12.CSTARTADD_7// ADC12MEM7;

const ADC12.CSTARTADD_8// ADC12MEM8;

const ADC12.CSTARTADD_9// ADC12MEM9;

const ADC12.CSTARTADD_10// ADC12MEM10;

const ADC12.CSTARTADD_11// ADC12MEM11;

const ADC12.CSTARTADD_12// ADC12MEM12;

const ADC12.CSTARTADD_13// ADC12MEM13;

const ADC12.CSTARTADD_14// ADC12MEM14;

const ADC12.CSTARTADD_15// ADC12MEM15;

values of type ADC12.ENC_t// ENC Bit

const ADC12.ENC_OFF// ADC12 disabled;

const ADC12.ENC// ADC12 enabled;

values of type ADC12.EOS_t// EOS Bit

const ADC12.EOS_OFF// Not end of sequence;

const ADC12.EOS// End of sequence;

values of type ADC12.INCH_t// INCH Bits

const ADC12.INCH_0// A0;

const ADC12.INCH_1// A1;

const ADC12.INCH_2// A2;

const ADC12.INCH_3// A3;

const ADC12.INCH_4// A4;

const ADC12.INCH_5// A5;

const ADC12.INCH_6// A6;

const ADC12.INCH_7// A7;

const ADC12.INCH_8// VeREF+;

const ADC12.INCH_9// VREF--/VeREF-;

const ADC12.INCH_10// Temperature diode;

const ADC12.INCH_11// (AVcc - AVss) / 2;

const ADC12.INCH_12// GND;

const ADC12.INCH_13// GND;

const ADC12.INCH_14// GND;

const ADC12.INCH_15// GND;

values of type ADC12.ISSH_t// ISSH Bits

const ADC12.ISSH_OFF// The sample-input signal is not inverted;

const ADC12.ISSH// The sample-input signal is inverted;

values of type ADC12.MSC_t// MSC Bit

const ADC12.MSC_OFF// The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion;

const ADC12.MSC// The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed;

values of type ADC12.REF2_5V_t// REF2_5V Bit

const ADC12.REF2_5V_OFF// 1.5V;

const ADC12.REF2_5V// 2.5V;

values of type ADC12.REFON_t// REFON Bit

const ADC12.REFON_OFF// Reference off;

const ADC12.REFON// Reference on;

values of type ADC12.SHP_t// SHP Bits

const ADC12.SHP_OFF// SAMPCON signal is sourced from the sample-input signal;

const ADC12.SHP// SAMPCON signal is sourced from the sampling timer;

values of type ADC12.SHS_t// SHS Bits

const ADC12.SHS_0// ADC12SC bit;

const ADC12.SHS_1// Timer_A.OUT1;

const ADC12.SHS_2// Timer_B.OUT0;

const ADC12.SHS_3// Timer_B.OUT1;

values of type ADC12.SREF_t// SREF Bits

const ADC12.SREF_0// VR+ = AVcc and VR-- = AVss;

const ADC12.SREF_1// VR+ = VREF+ and VR-- = AVss;

const ADC12.SREF_2// VR+ = VeREF+ and VR-- = AVss;

const ADC12.SREF_3// VR+ = VeREF+ and VR-- = AVss;

const ADC12.SREF_4// VR+ = AVcc and VR-- = VREF--/ VeREF--;

const ADC12.SREF_5// VR+ = VREF+ and VR-- = VREF--/ VeREF--;

const ADC12.SREF_6// VR+ = VeREF+ and VR-- = VREF--/ VeREF--;

const ADC12.SREF_7// VR+ = VeREF+ and VR-- = VREF--/ VeREF--;

var obj = new ADC12.ADC12CTL0_t// ADC12 Control Register 0;

obj.ADC12SHT1// Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15 = ADC12.ADC12SHT1_t ...

obj.ADC12SHT0// Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7 = ADC12.ADC12SHT0_t ...

obj.MSC// Multiple sample and conversion. Valid only for sequence or repeated modes. 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed = ADC12.MSC_t ...

obj.REF2_5V// Reference generator voltage. REFON must also be set. 0 1.5V 1 2.5V = ADC12.REF2_5V_t ...

obj.REFON// Reference generator on 0 Reference off 1 Reference on = ADC12.REFON_t ...

obj.ADC12ON// ADC12 on 0 ADC12 off 1 ADC12 on = ADC12.ADC12ON_t ...

obj.ADC12OVIE// ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Overflow interrupt disabled 1 Overflow interrupt enabled = ADC12.ADC12OVIE_t ...

obj.ADC12TOVIE// ADC12 conversion-time-overflow interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled = ADC12.ADC12TOVIE_t ...

obj.ENC// Enable conversion 0 ADC12 disabled 1 ADC12 enabled = ADC12.ENC_t ...

obj.ADC12SC// Start conversion. Software-controlled sample-and-conversion start. ADC12SC and ENC may be set together with one instruction. ADC12SC is reset automatically. 0 No sample-and-conversion-start 1 Start sample-and-conversion = ADC12.ADC12SC_t ...

var obj = new ADC12.ADC12CTL1_t// ADC12 Control Register 1;

obj.CSTARTADD// Conversion start address. These bits select which ADC12 conversion-memory register is used for a single conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15 = ADC12.CSTARTADD_t ...

obj.SHS// Sample-and-hold source select 00 ADC12SC bit 01 Timer_A.OUT1 10 Timer_B.OUT0 11 Timer_B.OUT1 = ADC12.SHS_t ...

obj.SHP// Sample-and-hold pulse-mode select. This bit selects the source of the sampling signal (SAMPCON) to be either the output of the sampling timer or the sample-input signal directly. 0 SAMPCON signal is sourced from the sample-input signal. 1 SAMPCON signal is sourced from the sampling timer = ADC12.SHP_t ...

obj.ISSH// Invert signal sample-and-hold 0 The sample-input signal is not inverted. 1 The sample-input signal is inverted = ADC12.ISSH_t ...

obj.ADC12DIV// ADC12 clock divider 000 /1 001 /2 010 /3 011 /4 100 /5 101 /6 110 /7 111 /8 = ADC12.ADC12DIV_t ...

obj.ADC12SSEL// ADC12 clock source select 00 ADC12OSC 01 ACLK 10 MCLK 11 SMCLK = ADC12.ADC12SSEL_t ...

obj.CONSEQ// Conversion sequence mode select 00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels = ADC12.CONSEQ_t ...

obj.ADC12BUSY// ADC12 busy. This bit indicates an active sample or conversion operation. 0 No operation is active. 1 A sequence, sample, or conversion is active = ADC12.ADC12BUSY_t ...

var obj = new ADC12.ADC12IE_t// ADC12 Interrupt Enable Register;

obj.ADC12IE15// Enable or disable the interrupt request for the ADC12IFG15 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE15_t ...

obj.ADC12IE14// Enable or disable the interrupt request for the ADC12IFG14 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE14_t ...

obj.ADC12IE13// Enable or disable the interrupt request for the ADC12IFG13 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE13_t ...

obj.ADC12IE12// Enable or disable the interrupt request for the ADC12IFG12 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE12_t ...

obj.ADC12IE11// Enable or disable the interrupt request for the ADC12IFG11 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE11_t ...

obj.ADC12IE10// Enable or disable the interrupt request for the ADC12IFG10 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE10_t ...

obj.ADC12IE9// Enable or disable the interrupt request for the ADC12IFG9 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE9_t ...

obj.ADC12IE8// Enable or disable the interrupt request for the ADC12IFG8 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE8_t ...

obj.ADC12IE7// Enable or disable the interrupt request for the ADC12IFG7 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE7_t ...

obj.ADC12IE6// Enable or disable the interrupt request for the ADC12IFG6 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE6_t ...

obj.ADC12IE5// Enable or disable the interrupt request for the ADC12IFG5 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE5_t ...

obj.ADC12IE4// Enable or disable the interrupt request for the ADC12IFG4 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE4_t ...

obj.ADC12IE3// Enable or disable the interrupt request for the ADC12IFG3 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE3_t ...

obj.ADC12IE2// Enable or disable the interrupt request for the ADC12IFG2 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE2_t ...

obj.ADC12IE1// Enable or disable the interrupt request for the ADC12IFG1 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE1_t ...

obj.ADC12IE0// Enable or disable the interrupt request for the ADC12IFG0 bit. 0 Interrupt disabled 1 Interrupt enabled = ADC12.ADC12IE0_t ...

var obj = new ADC12.ADC12MCTL_t// ADC12 Conversion Memory Control Registers;

obj.EOS// End of sequence. Indicates the last conversion in a sequence. 0 Not end of sequence 1 End of sequence = ADC12.EOS_t ...

obj.SREF// Select reference 000 VR+ = AVCC and VR-- = AVSS 001 VR+ = VREF+ and VR-- = AVSS 010 VR+ = VeREF+ and VR-- = AVSS 011 VR+ = VeREF+ and VR-- = AVSS 100 VR+ = AVCC and VR-- = VREF--/ VeREF-- 101 VR+ = VREF+ and VR-- = VREF--/ VeREF-- 110 VR+ = VeREF+ and VR-- = VREF--/ VeREF-- 111 VR+ = VeREF+ and VR-- = VREF--/ VeREF-- = ADC12.SREF_t ...

obj.INCH// Input channel select 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 VeREF+ 1001 VREF--/VeREF-- 1010 Temperature diode 1011 (AVCC � AVSS) / 2 1100 GND 1101 GND 1110 GND 1111 GND = ADC12.INCH_t ...

var obj = new ADC12.ForceSetDefaultRegister_t// Force Set Default Register;

obj.register = String ...

obj.regForceSet = Bool ...

var obj = new ADC12.regIntVect_t// Interrupt vector description;

obj.registerName = String ...

obj.registerDescription = String ...

obj.isrToggleString = String ...

obj.priorityName = String ...

obj.interruptEnable = Bool ...

obj.interruptHandler = Bool ...

obj.priority = Int ...

module-wide functions

ADC12.getAll// Find all peripherals of a certain type() returns IPeripheral.Instance[]

ADC12.getRegisters// Find all registers defined by the peripheral() returns String[]

per-instance config parameters

var params = new ADC12.Params// Instance config-params object;

params.ADC12CTL0// ADC12CTL0 Register = ADC12.ADC12CTL0_t {

ADC12SHT1: ADC12.SHT1_0,

ADC12SHT0: ADC12.SHT0_0,

MSC: ADC12.MSC_OFF,

REF2_5V: ADC12.REF2_5V_OFF,

REFON: ADC12.REFON_OFF,

ADC12ON: ADC12.ADC12ON_OFF,

ADC12OVIE: ADC12.ADC12OVIE_OFF,

ADC12TOVIE: ADC12.ADC12TOVIE_OFF,

ENC: ADC12.ENC_OFF,

ADC12SC: ADC12.ADC12SC_OFF

};

params.ADC12CTL1// ADC12CTL1 Register = ADC12.ADC12CTL1_t {

CSTARTADD: ADC12.CSTARTADD_0,

SHS: ADC12.SHS_0,

SHP: ADC12.SHP_OFF,

ISSH: ADC12.ISSH_OFF,

ADC12DIV: ADC12.ADC12DIV_0,

ADC12SSEL: ADC12.ADC12SSEL_0,

CONSEQ: ADC12.CONSEQ_0,

ADC12BUSY: ADC12.ADC12BUSY_OFF

};

params.ADC12IE// ADC12 Interrupt Enable Register = ADC12.ADC12IE_t {

ADC12IE15: ADC12.ADC12IE15_OFF,

ADC12IE14: ADC12.ADC12IE14_OFF,

ADC12IE13: ADC12.ADC12IE13_OFF,

ADC12IE12: ADC12.ADC12IE12_OFF,

ADC12IE11: ADC12.ADC12IE11_OFF,

ADC12IE10: ADC12.ADC12IE10_OFF,

ADC12IE9: ADC12.ADC12IE9_OFF,

ADC12IE8: ADC12.ADC12IE8_OFF,

ADC12IE7: ADC12.ADC12IE7_OFF,

ADC12IE6: ADC12.ADC12IE6_OFF,

ADC12IE5: ADC12.ADC12IE5_OFF,

ADC12IE4: ADC12.ADC12IE4_OFF,

ADC12IE3: ADC12.ADC12IE3_OFF,

ADC12IE2: ADC12.ADC12IE2_OFF,

ADC12IE1: ADC12.ADC12IE1_OFF,

ADC12IE0: ADC12.ADC12IE0_OFF

};

params.ADC12IFG// ADC12IFG Register = Bits16 0;

params.ADC12IV// ADC12IV Register = Bits16 ADC12.ADC12IV_NONE;

params.ADC12MCTL0// ADC12MCTL0 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL1// ADC12MCTL1 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL10// ADC12MCTL10 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL11// ADC12MCTL11 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL12// ADC12MCTL12 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL13// ADC12MCTL13 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL14// ADC12MCTL14 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL15// ADC12MCTL15 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL2// ADC12MCTL2 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL3// ADC12MCTL3 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL4// ADC12MCTL4 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL5// ADC12MCTL5 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL6// ADC12MCTL6 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL7// ADC12MCTL7 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL8// ADC12MCTL8 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL9// ADC12MCTL9 Register = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MEM0// ADC12MEM0 Register = Bits16 0;

params.ADC12MEM1// ADC12MEM1 Register = Bits16 0;

params.ADC12MEM10// ADC12MEM10 Register = Bits16 0;

params.ADC12MEM11// ADC12MEM11 Register = Bits16 0;

params.ADC12MEM12// ADC12MEM12 Register = Bits16 0;

params.ADC12MEM13// ADC12MEM13 Register = Bits16 0;

params.ADC12MEM14// ADC12MEM14 Register = Bits16 0;

params.ADC12MEM15// ADC12MEM15 Register = Bits16 0;

params.ADC12MEM2// ADC12MEM2 Register = Bits16 0;

params.ADC12MEM3// ADC12MEM3 Register = Bits16 0;

params.ADC12MEM4// ADC12MEM4 Register = Bits16 0;

params.ADC12MEM5// ADC12MEM5 Register = Bits16 0;

params.ADC12MEM6// ADC12MEM6 Register = Bits16 0;

params.ADC12MEM7// ADC12MEM7 Register = Bits16 0;

params.ADC12MEM8// ADC12MEM8 Register = Bits16 0;

params.ADC12MEM9// ADC12MEM9 Register = Bits16 0;

params.forceSetDefaultRegister// Determine if each Register needs to be forced set or not = ADC12.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.interruptSource// ADC12 has 16 interrupt enable = ADC12.regIntVect_t[16] undefined;

params.name// Specific peripheral name given by the device = String undefined;

params.owner// String specifying the entity that manages the peripheral = String undefined;

per-instance creation

var inst = ADC12.create// Create an instance-object(IClock.Instance clock, params);

enum ADC12.ADC12BUSY_t

index URL

ADC12 Busy Bit

XDCscript usage meta-domain

values of type ADC12.ADC12BUSY_t

const ADC12.ADC12BUSY_OFF;

const ADC12.ADC12BUSY;

enum ADC12.ADC12DIV_t

index URL

ADC12DIV Bits

XDCscript usage meta-domain

values of type ADC12.ADC12DIV_t

const ADC12.ADC12DIV_0;

// Divide by 1

const ADC12.ADC12DIV_1;

// Divide by 2

const ADC12.ADC12DIV_2;

// Divide by 3

const ADC12.ADC12DIV_3;

// Divide by 4

const ADC12.ADC12DIV_4;

// Divide by 5

const ADC12.ADC12DIV_5;

// Divide by 6

const ADC12.ADC12DIV_6;

// Divide by 7

const ADC12.ADC12DIV_7;

// Divide by 8

enum ADC12.ADC12IE0_t

index URL

ADC12 Interrupt Enable Bit 0

XDCscript usage meta-domain

values of type ADC12.ADC12IE0_t

const ADC12.ADC12IE0_OFF;

// Disable the interrupt request for the ADC12IFG0 bit

const ADC12.ADC12IE0;

// Enable the interrupt request for the ADC12IFG0 bit

enum ADC12.ADC12IE10_t

index URL

ADC12 Interrupt Enable Bit 10

XDCscript usage meta-domain

values of type ADC12.ADC12IE10_t

const ADC12.ADC12IE10_OFF;

// Disable the interrupt request for the ADC12IFG10 bit

const ADC12.ADC12IE10;

// Enable the interrupt request for the ADC12IFG10 bit

enum ADC12.ADC12IE11_t

index URL

ADC12 Interrupt Enable Bit 11

XDCscript usage meta-domain

values of type ADC12.ADC12IE11_t

const ADC12.ADC12IE11_OFF;

// Disable the interrupt request for the ADC12IFG11 bit

const ADC12.ADC12IE11;

// Enable the interrupt request for the ADC12IFG11 bit

enum ADC12.ADC12IE12_t

index URL

ADC12 Interrupt Enable Bit 12

XDCscript usage meta-domain

values of type ADC12.ADC12IE12_t

const ADC12.ADC12IE12_OFF;

// Disable the interrupt request for the ADC12IFG12 bit

const ADC12.ADC12IE12;

// Enable the interrupt request for the ADC12IFG12 bit

enum ADC12.ADC12IE13_t

index URL

ADC12 Interrupt Enable Bit 13

XDCscript usage meta-domain

values of type ADC12.ADC12IE13_t

const ADC12.ADC12IE13_OFF;

// Disable the interrupt request for the ADC12IFG13 bit

const ADC12.ADC12IE13;

// Enable the interrupt request for the ADC12IFG13 bit

enum ADC12.ADC12IE14_t

index URL

ADC12 Interrupt Enable Bit 14

XDCscript usage meta-domain

values of type ADC12.ADC12IE14_t

const ADC12.ADC12IE14_OFF;

// Disable the interrupt request for the ADC12IFG14 bit

const ADC12.ADC12IE14;

// Enable the interrupt request for the ADC12IFG14 bit

enum ADC12.ADC12IE15_t

index URL

ADC12 Interrupt Enable Bit 15

XDCscript usage meta-domain

values of type ADC12.ADC12IE15_t

const ADC12.ADC12IE15_OFF;

// Disable the interrupt request for the ADC12IFG15 bit

const ADC12.ADC12IE15;

// Enable the interrupt request for the ADC12IFG15 bit

enum ADC12.ADC12IE1_t

index URL

ADC12 Interrupt Enable Bit 1

XDCscript usage meta-domain

values of type ADC12.ADC12IE1_t

const ADC12.ADC12IE1_OFF;

// Disable the interrupt request for the ADC12IFG1 bit

const ADC12.ADC12IE1;

// Enable the interrupt request for the ADC12IFG1 bit

enum ADC12.ADC12IE2_t

index URL

ADC12 Interrupt Enable Bit 2

XDCscript usage meta-domain

values of type ADC12.ADC12IE2_t

const ADC12.ADC12IE2_OFF;

// Disable the interrupt request for the ADC12IFG2 bit

const ADC12.ADC12IE2;

// Enable the interrupt request for the ADC12IFG2 bit

enum ADC12.ADC12IE3_t

index URL

ADC12 Interrupt Enable Bit 3

XDCscript usage meta-domain

values of type ADC12.ADC12IE3_t

const ADC12.ADC12IE3_OFF;

// Disable the interrupt request for the ADC12IFG3 bit

const ADC12.ADC12IE3;

// Enable the interrupt request for the ADC12IFG3 bit

enum ADC12.ADC12IE4_t

index URL

ADC12 Interrupt Enable Bit 4

XDCscript usage meta-domain

values of type ADC12.ADC12IE4_t

const ADC12.ADC12IE4_OFF;

// Disable the interrupt request for the ADC12IFG4 bit

const ADC12.ADC12IE4;

// Enable the interrupt request for the ADC12IFG4 bit

enum ADC12.ADC12IE5_t

index URL

ADC12 Interrupt Enable Bit 5

XDCscript usage meta-domain

values of type ADC12.ADC12IE5_t

const ADC12.ADC12IE5_OFF;

// Disable the interrupt request for the ADC12IFG5 bit

const ADC12.ADC12IE5;

// Enable the interrupt request for the ADC12IFG5 bit

enum ADC12.ADC12IE6_t

index URL

ADC12 Interrupt Enable Bit 6

XDCscript usage meta-domain

values of type ADC12.ADC12IE6_t

const ADC12.ADC12IE6_OFF;

// Disable the interrupt request for the ADC12IFG6 bit

const ADC12.ADC12IE6;

// Enable the interrupt request for the ADC12IFG6 bit

enum ADC12.ADC12IE7_t

index URL

ADC12 Interrupt Enable Bit 7

XDCscript usage meta-domain

values of type ADC12.ADC12IE7_t

const ADC12.ADC12IE7_OFF;

// Disable the interrupt request for the ADC12IFG7 bit

const ADC12.ADC12IE7;

// Enable the interrupt request for the ADC12IFG7 bit

enum ADC12.ADC12IE8_t

index URL

ADC12 Interrupt Enable Bit 8

XDCscript usage meta-domain

values of type ADC12.ADC12IE8_t

const ADC12.ADC12IE8_OFF;

// Disable the interrupt request for the ADC12IFG8 bit

const ADC12.ADC12IE8;

// Enable the interrupt request for the ADC12IFG8 bit

enum ADC12.ADC12IE9_t

index URL

ADC12 Interrupt Enable Bit 9

XDCscript usage meta-domain

values of type ADC12.ADC12IE9_t

const ADC12.ADC12IE9_OFF;

// Disable the interrupt request for the ADC12IFG9 bit

const ADC12.ADC12IE9;

// Enable the interrupt request for the ADC12IFG9 bit

enum ADC12.ADC12IV_t

index URL

ADC12IV Definitions

XDCscript usage meta-domain

values of type ADC12.ADC12IV_t

const ADC12.ADC12IV_NONE;

// No Interrupt pending

const ADC12.ADC12IV_ADC12OVIFG;

// ADC12OVIFG

const ADC12.ADC12IV_ADC12TOVIFG;

// ADC12TOVIFG

const ADC12.ADC12IV_ADC12IFG0;

// ADC12IFG0

const ADC12.ADC12IV_ADC12IFG1;

// ADC12IFG1

const ADC12.ADC12IV_ADC12IFG2;

// ADC12IFG2

const ADC12.ADC12IV_ADC12IFG3;

// ADC12IFG3

const ADC12.ADC12IV_ADC12IFG4;

// ADC12IFG4

const ADC12.ADC12IV_ADC12IFG5;

// ADC12IFG5

const ADC12.ADC12IV_ADC12IFG6;

// ADC12IFG6

const ADC12.ADC12IV_ADC12IFG7;

// ADC12IFG7

const ADC12.ADC12IV_ADC12IFG8;

// ADC12IFG8

const ADC12.ADC12IV_ADC12IFG9;

// ADC12IFG9

const ADC12.ADC12IV_ADC12IFG10;

// ADC12IFG10

const ADC12.ADC12IV_ADC12IFG11;

// ADC12IFG11

const ADC12.ADC12IV_ADC12IFG12;

// ADC12IFG12

const ADC12.ADC12IV_ADC12IFG13;

// ADC12IFG13

const ADC12.ADC12IV_ADC12IFG14;

// ADC12IFG14

const ADC12.ADC12IV_ADC12IFG15;

// ADC12IFG15

enum ADC12.ADC12ON_t

index URL

ADC12ON Bit

XDCscript usage meta-domain

values of type ADC12.ADC12ON_t

const ADC12.ADC12ON_OFF;

// ADC12 off

const ADC12.ADC12ON;

// ADC12 on

enum ADC12.ADC12OVIE_t

index URL

ADC12OVIE Bit

XDCscript usage meta-domain

values of type ADC12.ADC12OVIE_t

const ADC12.ADC12OVIE_OFF;

// Overflow interrupt disabled

const ADC12.ADC12OVIE;

// Overflow interrupt enabled

enum ADC12.ADC12SC_t

index URL

ADC12SC Bit

XDCscript usage meta-domain

values of type ADC12.ADC12SC_t

const ADC12.ADC12SC_OFF;

// No sample-and-conversion-start

const ADC12.ADC12SC;

// Start sample-and-conversion

enum ADC12.ADC12SHT0_t

index URL

SHT0 Bits

XDCscript usage meta-domain

values of type ADC12.ADC12SHT0_t

const ADC12.SHT0_0;

// 4 ADC12CLK cycles

const ADC12.SHT0_1;

// 8 ADC12CLK cycles

const ADC12.SHT0_2;

// 16 ADC12CLK cycles

const ADC12.SHT0_3;

// 32 ADC12CLK cycles

const ADC12.SHT0_4;

// 64 ADC12CLK cycles

const ADC12.SHT0_5;

// 96 ADC12CLK cycles

const ADC12.SHT0_6;

// 128 ADC12CLK cycles

const ADC12.SHT0_7;

// 192 ADC12CLK cycles

const ADC12.SHT0_8;

// 256 ADC12CLK cycles

const ADC12.SHT0_9;

// 384 ADC12CLK cycles

const ADC12.SHT0_10;

// 512 ADC12CLK cycles

const ADC12.SHT0_11;

// 768 ADC12CLK cycles

const ADC12.SHT0_12;

// 1024 ADC12CLK cycles

const ADC12.SHT0_13;

// 1024 ADC12CLK cycles

const ADC12.SHT0_14;

// 1024 ADC12CLK cycles

const ADC12.SHT0_15;

// 1024 ADC12CLK cycles

enum ADC12.ADC12SHT1_t

index URL

SHT1 Bits

XDCscript usage meta-domain

values of type ADC12.ADC12SHT1_t

const ADC12.SHT1_0;

// 4 ADC12CLK cycles

const ADC12.SHT1_1;

// 8 ADC12CLK cycles

const ADC12.SHT1_2;

// 16 ADC12CLK cycles

const ADC12.SHT1_3;

// 32 ADC12CLK cycles

const ADC12.SHT1_4;

// 64 ADC12CLK cycles

const ADC12.SHT1_5;

// 96 ADC12CLK cycles

const ADC12.SHT1_6;

// 128 ADC12CLK cycles

const ADC12.SHT1_7;

// 192 ADC12CLK cycles

const ADC12.SHT1_8;

// 256 ADC12CLK cycles

const ADC12.SHT1_9;

// 384 ADC12CLK cycles

const ADC12.SHT1_10;

// 512 ADC12CLK cycles

const ADC12.SHT1_11;

// 768 ADC12CLK cycles

const ADC12.SHT1_12;

// 1024 ADC12CLK cycles

const ADC12.SHT1_13;

// 1024 ADC12CLK cycles

const ADC12.SHT1_14;

// 1024 ADC12CLK cycles

const ADC12.SHT1_15;

// 1024 ADC12CLK cycles

enum ADC12.ADC12SSEL_t

index URL

ADC12SSEL Bits

XDCscript usage meta-domain

values of type ADC12.ADC12SSEL_t

const ADC12.ADC12SSEL_0;

// ADC12OSC

const ADC12.ADC12SSEL_1;

// ACLK

const ADC12.ADC12SSEL_2;

// MCLK

const ADC12.ADC12SSEL_3;

// SMCLK

enum ADC12.ADC12TOVIE_t

index URL

ADC12TOVIE Bit

XDCscript usage meta-domain

values of type ADC12.ADC12TOVIE_t

const ADC12.ADC12TOVIE_OFF;

// Conversion time overflow interrupt disabled

const ADC12.ADC12TOVIE;

// Conversion time overflow interrupt disabled

enum ADC12.CONSEQ_t

index URL

CONSEQ Bits

XDCscript usage meta-domain

values of type ADC12.CONSEQ_t

const ADC12.CONSEQ_0;

// Single channel single conversion

const ADC12.CONSEQ_1;

// Sequence of channels

const ADC12.CONSEQ_2;

// Repeat single channel

const ADC12.CONSEQ_3;

// Repeat sequence of channels

enum ADC12.CSTARTADD_t

index URL

CSTARTADD Bits

XDCscript usage meta-domain

values of type ADC12.CSTARTADD_t

const ADC12.CSTARTADD_0;

// ADC12MEM0

const ADC12.CSTARTADD_1;

// ADC12MEM1

const ADC12.CSTARTADD_2;

// ADC12MEM2

const ADC12.CSTARTADD_3;

// ADC12MEM3

const ADC12.CSTARTADD_4;

// ADC12MEM4

const ADC12.CSTARTADD_5;

// ADC12MEM5

const ADC12.CSTARTADD_6;

// ADC12MEM6

const ADC12.CSTARTADD_7;

// ADC12MEM7

const ADC12.CSTARTADD_8;

// ADC12MEM8

const ADC12.CSTARTADD_9;

// ADC12MEM9

const ADC12.CSTARTADD_10;

// ADC12MEM10

const ADC12.CSTARTADD_11;

// ADC12MEM11

const ADC12.CSTARTADD_12;

// ADC12MEM12

const ADC12.CSTARTADD_13;

// ADC12MEM13

const ADC12.CSTARTADD_14;

// ADC12MEM14

const ADC12.CSTARTADD_15;

// ADC12MEM15

enum ADC12.ENC_t

index URL

ENC Bit

XDCscript usage meta-domain

values of type ADC12.ENC_t

const ADC12.ENC_OFF;

// ADC12 disabled

const ADC12.ENC;

// ADC12 enabled

enum ADC12.EOS_t

index URL

EOS Bit

XDCscript usage meta-domain

values of type ADC12.EOS_t

const ADC12.EOS_OFF;

// Not end of sequence

const ADC12.EOS;

// End of sequence

enum ADC12.INCH_t

index URL

INCH Bits

XDCscript usage meta-domain

values of type ADC12.INCH_t

const ADC12.INCH_0;

// A0

const ADC12.INCH_1;

// A1

const ADC12.INCH_2;

// A2

const ADC12.INCH_3;

// A3

const ADC12.INCH_4;

// A4

const ADC12.INCH_5;

// A5

const ADC12.INCH_6;

// A6

const ADC12.INCH_7;

// A7

const ADC12.INCH_8;

// VeREF+

const ADC12.INCH_9;

// VREF--/VeREF-

const ADC12.INCH_10;

// Temperature diode

const ADC12.INCH_11;

// (AVcc - AVss) / 2

const ADC12.INCH_12;

// GND

const ADC12.INCH_13;

// GND

const ADC12.INCH_14;

// GND

const ADC12.INCH_15;

// GND

enum ADC12.ISSH_t

index URL

ISSH Bits

XDCscript usage meta-domain

values of type ADC12.ISSH_t

const ADC12.ISSH_OFF;

// The sample-input signal is not inverted

const ADC12.ISSH;

// The sample-input signal is inverted

enum ADC12.MSC_t

index URL

MSC Bit

XDCscript usage meta-domain

values of type ADC12.MSC_t

const ADC12.MSC_OFF;

// The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion

const ADC12.MSC;

// The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed

enum ADC12.REF2_5V_t

index URL

REF2_5V Bit

XDCscript usage meta-domain

values of type ADC12.REF2_5V_t

const ADC12.REF2_5V_OFF;

// 1.5V

const ADC12.REF2_5V;

// 2.5V

enum ADC12.REFON_t

index URL

REFON Bit

XDCscript usage meta-domain

values of type ADC12.REFON_t

const ADC12.REFON_OFF;

// Reference off

const ADC12.REFON;

// Reference on

enum ADC12.SHP_t

index URL

SHP Bits

XDCscript usage meta-domain

values of type ADC12.SHP_t

const ADC12.SHP_OFF;

// SAMPCON signal is sourced from the sample-input signal

const ADC12.SHP;

// SAMPCON signal is sourced from the sampling timer

enum ADC12.SHS_t

index URL

SHS Bits

XDCscript usage meta-domain

values of type ADC12.SHS_t

const ADC12.SHS_0;

// ADC12SC bit

const ADC12.SHS_1;

// Timer_A.OUT1

const ADC12.SHS_2;

// Timer_B.OUT0

const ADC12.SHS_3;

// Timer_B.OUT1

enum ADC12.SREF_t

index URL

SREF Bits

XDCscript usage meta-domain

values of type ADC12.SREF_t

const ADC12.SREF_0;

// VR+ = AVcc and VR-- = AVss

const ADC12.SREF_1;

// VR+ = VREF+ and VR-- = AVss

const ADC12.SREF_2;

// VR+ = VeREF+ and VR-- = AVss

const ADC12.SREF_3;

// VR+ = VeREF+ and VR-- = AVss

const ADC12.SREF_4;

// VR+ = AVcc and VR-- = VREF--/ VeREF--

const ADC12.SREF_5;

// VR+ = VREF+ and VR-- = VREF--/ VeREF--

const ADC12.SREF_6;

// VR+ = VeREF+ and VR-- = VREF--/ VeREF--

const ADC12.SREF_7;

// VR+ = VeREF+ and VR-- = VREF--/ VeREF--

struct ADC12.ADC12CTL0_t

index URL

ADC12 Control Register 0

XDCscript usage meta-domain

var obj = new ADC12.ADC12CTL0_t;

obj.ADC12SHT1 = ADC12.ADC12SHT1_t ...

// Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15

obj.ADC12SHT0 = ADC12.ADC12SHT0_t ...

// Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7

obj.MSC = ADC12.MSC_t ...

// Multiple sample and conversion. Valid only for sequence or repeated modes. 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed

obj.REF2_5V = ADC12.REF2_5V_t ...

// Reference generator voltage. REFON must also be set. 0 1.5V 1 2.5V

obj.REFON = ADC12.REFON_t ...

// Reference generator on 0 Reference off 1 Reference on

obj.ADC12ON = ADC12.ADC12ON_t ...

// ADC12 on 0 ADC12 off 1 ADC12 on

obj.ADC12OVIE = ADC12.ADC12OVIE_t ...

// ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Overflow interrupt disabled 1 Overflow interrupt enabled

obj.ADC12TOVIE = ADC12.ADC12TOVIE_t ...

// ADC12 conversion-time-overflow interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled

obj.ENC = ADC12.ENC_t ...

// Enable conversion 0 ADC12 disabled 1 ADC12 enabled

obj.ADC12SC = ADC12.ADC12SC_t ...

// Start conversion. Software-controlled sample-and-conversion start. ADC12SC and ENC may be set together with one instruction. ADC12SC is reset automatically. 0 No sample-and-conversion-start 1 Start sample-and-conversion

struct ADC12.ADC12CTL1_t

index URL

ADC12 Control Register 1

XDCscript usage meta-domain

var obj = new ADC12.ADC12CTL1_t;

obj.CSTARTADD = ADC12.CSTARTADD_t ...

// Conversion start address. These bits select which ADC12 conversion-memory register is used for a single conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15

obj.SHS = ADC12.SHS_t ...

// Sample-and-hold source select 00 ADC12SC bit 01 Timer_A.OUT1 10 Timer_B.OUT0 11 Timer_B.OUT1

obj.SHP = ADC12.SHP_t ...

// Sample-and-hold pulse-mode select. This bit selects the source of the sampling signal (SAMPCON) to be either the output of the sampling timer or the sample-input signal directly. 0 SAMPCON signal is sourced from the sample-input signal. 1 SAMPCON signal is sourced from the sampling timer

obj.ISSH = ADC12.ISSH_t ...

// Invert signal sample-and-hold 0 The sample-input signal is not inverted. 1 The sample-input signal is inverted

obj.ADC12DIV = ADC12.ADC12DIV_t ...

// ADC12 clock divider 000 /1 001 /2 010 /3 011 /4 100 /5 101 /6 110 /7 111 /8

obj.ADC12SSEL = ADC12.ADC12SSEL_t ...

// ADC12 clock source select 00 ADC12OSC 01 ACLK 10 MCLK 11 SMCLK

obj.CONSEQ = ADC12.CONSEQ_t ...

// Conversion sequence mode select 00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels

obj.ADC12BUSY = ADC12.ADC12BUSY_t ...

// ADC12 busy. This bit indicates an active sample or conversion operation. 0 No operation is active. 1 A sequence, sample, or conversion is active

struct ADC12.ADC12IE_t

index URL

ADC12 Interrupt Enable Register

XDCscript usage meta-domain

var obj = new ADC12.ADC12IE_t;

obj.ADC12IE15 = ADC12.ADC12IE15_t ...

// Enable or disable the interrupt request for the ADC12IFG15 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE14 = ADC12.ADC12IE14_t ...

// Enable or disable the interrupt request for the ADC12IFG14 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE13 = ADC12.ADC12IE13_t ...

// Enable or disable the interrupt request for the ADC12IFG13 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE12 = ADC12.ADC12IE12_t ...

// Enable or disable the interrupt request for the ADC12IFG12 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE11 = ADC12.ADC12IE11_t ...

// Enable or disable the interrupt request for the ADC12IFG11 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE10 = ADC12.ADC12IE10_t ...

// Enable or disable the interrupt request for the ADC12IFG10 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE9 = ADC12.ADC12IE9_t ...

// Enable or disable the interrupt request for the ADC12IFG9 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE8 = ADC12.ADC12IE8_t ...

// Enable or disable the interrupt request for the ADC12IFG8 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE7 = ADC12.ADC12IE7_t ...

// Enable or disable the interrupt request for the ADC12IFG7 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE6 = ADC12.ADC12IE6_t ...

// Enable or disable the interrupt request for the ADC12IFG6 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE5 = ADC12.ADC12IE5_t ...

// Enable or disable the interrupt request for the ADC12IFG5 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE4 = ADC12.ADC12IE4_t ...

// Enable or disable the interrupt request for the ADC12IFG4 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE3 = ADC12.ADC12IE3_t ...

// Enable or disable the interrupt request for the ADC12IFG3 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE2 = ADC12.ADC12IE2_t ...

// Enable or disable the interrupt request for the ADC12IFG2 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE1 = ADC12.ADC12IE1_t ...

// Enable or disable the interrupt request for the ADC12IFG1 bit. 0 Interrupt disabled 1 Interrupt enabled

obj.ADC12IE0 = ADC12.ADC12IE0_t ...

// Enable or disable the interrupt request for the ADC12IFG0 bit. 0 Interrupt disabled 1 Interrupt enabled

struct ADC12.ADC12MCTL_t

index URL

ADC12 Conversion Memory Control Registers

XDCscript usage meta-domain

var obj = new ADC12.ADC12MCTL_t;

obj.EOS = ADC12.EOS_t ...

// End of sequence. Indicates the last conversion in a sequence. 0 Not end of sequence 1 End of sequence

obj.SREF = ADC12.SREF_t ...

// Select reference 000 VR+ = AVCC and VR-- = AVSS 001 VR+ = VREF+ and VR-- = AVSS 010 VR+ = VeREF+ and VR-- = AVSS 011 VR+ = VeREF+ and VR-- = AVSS 100 VR+ = AVCC and VR-- = VREF--/ VeREF-- 101 VR+ = VREF+ and VR-- = VREF--/ VeREF-- 110 VR+ = VeREF+ and VR-- = VREF--/ VeREF-- 111 VR+ = VeREF+ and VR-- = VREF--/ VeREF--

obj.INCH = ADC12.INCH_t ...

// Input channel select 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 VeREF+ 1001 VREF--/VeREF-- 1010 Temperature diode 1011 (AVCC � AVSS) / 2 1100 GND 1101 GND 1110 GND 1111 GND

struct ADC12.ForceSetDefaultRegister_t

index URL

Force Set Default Register

XDCscript usage meta-domain

var obj = new ADC12.ForceSetDefaultRegister_t;

obj.register = String ...

obj.regForceSet = Bool ...

DETAILS

Type to store if each register needs to be forced initialized even if the register is in default state.

SEE

ForceSetDefaultRegister_t

struct ADC12.regIntVect_t

index URL

Interrupt vector description

XDCscript usage meta-domain

var obj = new ADC12.regIntVect_t;

obj.registerName = String ...

obj.registerDescription = String ...

obj.isrToggleString = String ...

obj.priorityName = String ...

obj.interruptEnable = Bool ...

obj.interruptHandler = Bool ...

obj.priority = Int ...

DETAILS

Type to describe a single interrupt vector pin and all its possible configurations.

SEE

regIntVect_t

ADC12.getAll() // module-wide

index URL

Find all peripherals of a certain type

XDCscript usage meta-domain

ADC12.getAll() returns IPeripheral.Instance[]

DETAILS

The type of the peripherals returned is defined by the type of the caller.

RETURNS

Returns an array of IPeripheral instances

ADC12.getRegisters() // module-wide

index URL

Find all registers defined by the peripheral

XDCscript usage meta-domain

ADC12.getRegisters() returns String[]

RETURNS

Returns an array of register names

Instance Config Parameters

index URL

XDCscript usage meta-domain

var params = new ADC12.Params;

// Instance config-params object

params.ADC12CTL0 = ADC12.ADC12CTL0_t {

// ADC12CTL0 Register

ADC12SHT1: ADC12.SHT1_0,

ADC12SHT0: ADC12.SHT0_0,

MSC: ADC12.MSC_OFF,

REF2_5V: ADC12.REF2_5V_OFF,

REFON: ADC12.REFON_OFF,

ADC12ON: ADC12.ADC12ON_OFF,

ADC12OVIE: ADC12.ADC12OVIE_OFF,

ADC12TOVIE: ADC12.ADC12TOVIE_OFF,

ENC: ADC12.ENC_OFF,

ADC12SC: ADC12.ADC12SC_OFF

};

params.ADC12CTL1 = ADC12.ADC12CTL1_t {

// ADC12CTL1 Register

CSTARTADD: ADC12.CSTARTADD_0,

SHS: ADC12.SHS_0,

SHP: ADC12.SHP_OFF,

ISSH: ADC12.ISSH_OFF,

ADC12DIV: ADC12.ADC12DIV_0,

ADC12SSEL: ADC12.ADC12SSEL_0,

CONSEQ: ADC12.CONSEQ_0,

ADC12BUSY: ADC12.ADC12BUSY_OFF

};

params.ADC12IE = ADC12.ADC12IE_t {

// ADC12 Interrupt Enable Register

ADC12IE15: ADC12.ADC12IE15_OFF,

ADC12IE14: ADC12.ADC12IE14_OFF,

ADC12IE13: ADC12.ADC12IE13_OFF,

ADC12IE12: ADC12.ADC12IE12_OFF,

ADC12IE11: ADC12.ADC12IE11_OFF,

ADC12IE10: ADC12.ADC12IE10_OFF,

ADC12IE9: ADC12.ADC12IE9_OFF,

ADC12IE8: ADC12.ADC12IE8_OFF,

ADC12IE7: ADC12.ADC12IE7_OFF,

ADC12IE6: ADC12.ADC12IE6_OFF,

ADC12IE5: ADC12.ADC12IE5_OFF,

ADC12IE4: ADC12.ADC12IE4_OFF,

ADC12IE3: ADC12.ADC12IE3_OFF,

ADC12IE2: ADC12.ADC12IE2_OFF,

ADC12IE1: ADC12.ADC12IE1_OFF,

ADC12IE0: ADC12.ADC12IE0_OFF

};

params.ADC12IFG = Bits16 0;

// ADC12IFG Register

params.ADC12IV = Bits16 ADC12.ADC12IV_NONE;

// ADC12IV Register

params.ADC12MCTL0 = ADC12.ADC12MCTL_t {

// ADC12MCTL0 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL1 = ADC12.ADC12MCTL_t {

// ADC12MCTL1 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL10 = ADC12.ADC12MCTL_t {

// ADC12MCTL10 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL11 = ADC12.ADC12MCTL_t {

// ADC12MCTL11 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL12 = ADC12.ADC12MCTL_t {

// ADC12MCTL12 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL13 = ADC12.ADC12MCTL_t {

// ADC12MCTL13 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL14 = ADC12.ADC12MCTL_t {

// ADC12MCTL14 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL15 = ADC12.ADC12MCTL_t {

// ADC12MCTL15 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL2 = ADC12.ADC12MCTL_t {

// ADC12MCTL2 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL3 = ADC12.ADC12MCTL_t {

// ADC12MCTL3 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL4 = ADC12.ADC12MCTL_t {

// ADC12MCTL4 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL5 = ADC12.ADC12MCTL_t {

// ADC12MCTL5 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL6 = ADC12.ADC12MCTL_t {

// ADC12MCTL6 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL7 = ADC12.ADC12MCTL_t {

// ADC12MCTL7 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL8 = ADC12.ADC12MCTL_t {

// ADC12MCTL8 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MCTL9 = ADC12.ADC12MCTL_t {

// ADC12MCTL9 Register

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

params.ADC12MEM0 = Bits16 0;

// ADC12MEM0 Register

params.ADC12MEM1 = Bits16 0;

// ADC12MEM1 Register

params.ADC12MEM10 = Bits16 0;

// ADC12MEM10 Register

params.ADC12MEM11 = Bits16 0;

// ADC12MEM11 Register

params.ADC12MEM12 = Bits16 0;

// ADC12MEM12 Register

params.ADC12MEM13 = Bits16 0;

// ADC12MEM13 Register

params.ADC12MEM14 = Bits16 0;

// ADC12MEM14 Register

params.ADC12MEM15 = Bits16 0;

// ADC12MEM15 Register

params.ADC12MEM2 = Bits16 0;

// ADC12MEM2 Register

params.ADC12MEM3 = Bits16 0;

// ADC12MEM3 Register

params.ADC12MEM4 = Bits16 0;

// ADC12MEM4 Register

params.ADC12MEM5 = Bits16 0;

// ADC12MEM5 Register

params.ADC12MEM6 = Bits16 0;

// ADC12MEM6 Register

params.ADC12MEM7 = Bits16 0;

// ADC12MEM7 Register

params.ADC12MEM8 = Bits16 0;

// ADC12MEM8 Register

params.ADC12MEM9 = Bits16 0;

// ADC12MEM9 Register

params.forceSetDefaultRegister = ADC12.ForceSetDefaultRegister_t[] [

// Determine if each Register needs to be forced set or not

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

params.interruptSource = ADC12.regIntVect_t[16] undefined;

// ADC12 has 16 interrupt enable

params.name = String undefined;

// Specific peripheral name given by the device

params.owner = String undefined;

// String specifying the entity that manages the peripheral

config ADC12.ADC12CTL0 // instance

index URL

ADC12CTL0 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12CTL0 = ADC12.ADC12CTL0_t {

ADC12SHT1: ADC12.SHT1_0,

ADC12SHT0: ADC12.SHT0_0,

MSC: ADC12.MSC_OFF,

REF2_5V: ADC12.REF2_5V_OFF,

REFON: ADC12.REFON_OFF,

ADC12ON: ADC12.ADC12ON_OFF,

ADC12OVIE: ADC12.ADC12OVIE_OFF,

ADC12TOVIE: ADC12.ADC12TOVIE_OFF,

ENC: ADC12.ENC_OFF,

ADC12SC: ADC12.ADC12SC_OFF

};

config ADC12.ADC12CTL1 // instance

index URL

ADC12CTL1 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12CTL1 = ADC12.ADC12CTL1_t {

CSTARTADD: ADC12.CSTARTADD_0,

SHS: ADC12.SHS_0,

SHP: ADC12.SHP_OFF,

ISSH: ADC12.ISSH_OFF,

ADC12DIV: ADC12.ADC12DIV_0,

ADC12SSEL: ADC12.ADC12SSEL_0,

CONSEQ: ADC12.CONSEQ_0,

ADC12BUSY: ADC12.ADC12BUSY_OFF

};

config ADC12.ADC12IE // instance

index URL

ADC12 Interrupt Enable Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12IE = ADC12.ADC12IE_t {

ADC12IE15: ADC12.ADC12IE15_OFF,

ADC12IE14: ADC12.ADC12IE14_OFF,

ADC12IE13: ADC12.ADC12IE13_OFF,

ADC12IE12: ADC12.ADC12IE12_OFF,

ADC12IE11: ADC12.ADC12IE11_OFF,

ADC12IE10: ADC12.ADC12IE10_OFF,

ADC12IE9: ADC12.ADC12IE9_OFF,

ADC12IE8: ADC12.ADC12IE8_OFF,

ADC12IE7: ADC12.ADC12IE7_OFF,

ADC12IE6: ADC12.ADC12IE6_OFF,

ADC12IE5: ADC12.ADC12IE5_OFF,

ADC12IE4: ADC12.ADC12IE4_OFF,

ADC12IE3: ADC12.ADC12IE3_OFF,

ADC12IE2: ADC12.ADC12IE2_OFF,

ADC12IE1: ADC12.ADC12IE1_OFF,

ADC12IE0: ADC12.ADC12IE0_OFF

};

config ADC12.ADC12IFG // instance

index URL

ADC12IFG Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12IFG = Bits16 0;

config ADC12.ADC12IV // instance

index URL

ADC12IV Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12IV = Bits16 ADC12.ADC12IV_NONE;

config ADC12.ADC12MCTL0 // instance

index URL

ADC12MCTL0 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL0 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL1 // instance

index URL

ADC12MCTL1 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL1 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL10 // instance

index URL

ADC12MCTL10 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL10 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL11 // instance

index URL

ADC12MCTL11 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL11 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL12 // instance

index URL

ADC12MCTL12 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL12 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL13 // instance

index URL

ADC12MCTL13 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL13 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL14 // instance

index URL

ADC12MCTL14 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL14 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL15 // instance

index URL

ADC12MCTL15 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL15 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL2 // instance

index URL

ADC12MCTL2 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL2 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL3 // instance

index URL

ADC12MCTL3 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL3 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL4 // instance

index URL

ADC12MCTL4 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL4 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL5 // instance

index URL

ADC12MCTL5 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL5 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL6 // instance

index URL

ADC12MCTL6 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL6 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL7 // instance

index URL

ADC12MCTL7 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL7 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL8 // instance

index URL

ADC12MCTL8 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL8 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MCTL9 // instance

index URL

ADC12MCTL9 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MCTL9 = ADC12.ADC12MCTL_t {

EOS: ADC12.EOS_OFF,

SREF: ADC12.SREF_0,

INCH: ADC12.INCH_0

};

config ADC12.ADC12MEM0 // instance

index URL

ADC12MEM0 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM0 = Bits16 0;

config ADC12.ADC12MEM1 // instance

index URL

ADC12MEM1 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM1 = Bits16 0;

config ADC12.ADC12MEM10 // instance

index URL

ADC12MEM10 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM10 = Bits16 0;

config ADC12.ADC12MEM11 // instance

index URL

ADC12MEM11 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM11 = Bits16 0;

config ADC12.ADC12MEM12 // instance

index URL

ADC12MEM12 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM12 = Bits16 0;

config ADC12.ADC12MEM13 // instance

index URL

ADC12MEM13 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM13 = Bits16 0;

config ADC12.ADC12MEM14 // instance

index URL

ADC12MEM14 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM14 = Bits16 0;

config ADC12.ADC12MEM15 // instance

index URL

ADC12MEM15 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM15 = Bits16 0;

config ADC12.ADC12MEM2 // instance

index URL

ADC12MEM2 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM2 = Bits16 0;

config ADC12.ADC12MEM3 // instance

index URL

ADC12MEM3 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM3 = Bits16 0;

config ADC12.ADC12MEM4 // instance

index URL

ADC12MEM4 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM4 = Bits16 0;

config ADC12.ADC12MEM5 // instance

index URL

ADC12MEM5 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM5 = Bits16 0;

config ADC12.ADC12MEM6 // instance

index URL

ADC12MEM6 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM6 = Bits16 0;

config ADC12.ADC12MEM7 // instance

index URL

ADC12MEM7 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM7 = Bits16 0;

config ADC12.ADC12MEM8 // instance

index URL

ADC12MEM8 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM8 = Bits16 0;

config ADC12.ADC12MEM9 // instance

index URL

ADC12MEM9 Register

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.ADC12MEM9 = Bits16 0;

config ADC12.forceSetDefaultRegister // instance

index URL

Determine if each Register needs to be forced set or not

XDCscript usage meta-domain

var params = new ADC12.Params;

...

const params.forceSetDefaultRegister = ADC12.ForceSetDefaultRegister_t[] [

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

{

regForceSet: false

}

];

config ADC12.interruptSource // instance

index URL

ADC12 has 16 interrupt enable

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.interruptSource = ADC12.regIntVect_t[16] undefined;

config ADC12.name // instance

index URL

Specific peripheral name given by the device

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.name = String undefined;

DETAILS

Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.

config ADC12.owner // instance

index URL

String specifying the entity that manages the peripheral

XDCscript usage meta-domain

var params = new ADC12.Params;

...

params.owner = String undefined;

Instance Creation

index URL

XDCscript usage meta-domain

var params = new ADC12.Params;

// Allocate instance config-params

params.config = ...

// Assign individual configs

var inst = ADC12.create(IClock.Instance clock, params);

// Create an instance-object

generated on Fri, 14 Sep 2012 21:30:00 GMT