enum USCI_B0_I2C_2xx.UC7BIT_t |
![](../../../../../Arrow_up.png) |
Character length. Selects 7-bit or 8-bit character length
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UC7BIT_t
const USCI_B0_I2C_2xx.UC7BIT_OFF;
// 8-bit
const USCI_B0_I2C_2xx.UC7BIT;
// 7-bit
enum USCI_B0_I2C_2xx.UCA10_t |
![](../../../../../Arrow_up.png) |
Own addressing mode select
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCA10_t
const USCI_B0_I2C_2xx.UCA10_OFF;
// Own address is a 7-bit address
const USCI_B0_I2C_2xx.UCA10;
// Own address is a 10-bit address
enum USCI_B0_I2C_2xx.UCADDR_t |
![](../../../../../Arrow_up.png) |
Address received in address-bit multiprocessor mode
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCADDR_t
const USCI_B0_I2C_2xx.UCADDR_OFF;
// Received character is data
const USCI_B0_I2C_2xx.UCADDR;
// Received character is an address
enum USCI_B0_I2C_2xx.UCALIE_t |
![](../../../../../Arrow_up.png) |
Arbitration lost interrupt enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCALIE_t
const USCI_B0_I2C_2xx.UCALIE_OFF;
// Interrupt disabled
const USCI_B0_I2C_2xx.UCALIE;
// Interrupt enabled
enum USCI_B0_I2C_2xx.UCALIFG_t |
![](../../../../../Arrow_up.png) |
Arbitration lost interrupt flag
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCALIFG_t
const USCI_B0_I2C_2xx.UCALIFG_OFF;
// No interrupt pending
const USCI_B0_I2C_2xx.UCALIFG;
// Interrupt pending
enum USCI_B0_I2C_2xx.UCBBUSY_t |
![](../../../../../Arrow_up.png) |
Bus busy
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCBBUSY_t
const USCI_B0_I2C_2xx.UCBBUSY_OFF;
// Bus inactive
const USCI_B0_I2C_2xx.UCBBUSY;
// Bus busy
enum USCI_B0_I2C_2xx.UCBRKIE_t |
![](../../../../../Arrow_up.png) |
Receive break character interrupt-enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCBRKIE_t
const USCI_B0_I2C_2xx.UCBRKIE_OFF;
// Received break characters do not set UCAxRXIFG
const USCI_B0_I2C_2xx.UCBRKIE;
// Received break characters set UCAxRXIFG
enum USCI_B0_I2C_2xx.UCBRK_t |
![](../../../../../Arrow_up.png) |
Break detect flag
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCBRK_t
const USCI_B0_I2C_2xx.UCBRK_OFF;
// No break condition
const USCI_B0_I2C_2xx.UCBRK;
// Break condition occurred
enum USCI_B0_I2C_2xx.UCBUSY_t |
![](../../../../../Arrow_up.png) |
USCI busy. This bit indicates if a transmit or receive operation is in progress
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCBUSY_t
const USCI_B0_I2C_2xx.UCBUSY_OFF;
// USCI inactive
const USCI_B0_I2C_2xx.UCBUSY;
// USCI transmitting or receiving
enum USCI_B0_I2C_2xx.UCDORM_t |
![](../../../../../Arrow_up.png) |
Dormant. Puts USCI into sleep mode
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCDORM_t
const USCI_B0_I2C_2xx.UCDORM_OFF;
// Not dormant. All received characters will set UCAxRXIFG
const USCI_B0_I2C_2xx.UCDORM;
// Dormant. Only characters that are preceded by an idle-line or with
address bit set will set UCAxRXIFG. In UART mode with automatic baud
rate detection only the combination of a break and synch field will set
UCAxRXIFG
enum USCI_B0_I2C_2xx.UCFE_t |
![](../../../../../Arrow_up.png) |
Framing error flag
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCFE_t
const USCI_B0_I2C_2xx.UCFE_OFF;
// 0 No error
const USCI_B0_I2C_2xx.UCFE;
// Character received with low stop bit
enum USCI_B0_I2C_2xx.UCGCEN_t |
![](../../../../../Arrow_up.png) |
General call response enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCGCEN_t
const USCI_B0_I2C_2xx.UCGCEN_OFF;
// Do not respond to a general call
const USCI_B0_I2C_2xx.UCGCEN;
// Respond to a general call
enum USCI_B0_I2C_2xx.UCGC_t |
![](../../../../../Arrow_up.png) |
General call address received
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCGC_t
const USCI_B0_I2C_2xx.UCGC_OFF;
// No general call address received
const USCI_B0_I2C_2xx.UCGC;
// General call address received
enum USCI_B0_I2C_2xx.UCIDLE_t |
![](../../../../../Arrow_up.png) |
Idle line detected in idle-line multiprocessor mode
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCIDLE_t
const USCI_B0_I2C_2xx.UCIDLE_OFF;
// No idle line detected
const USCI_B0_I2C_2xx.UCIDLE;
// Idle line detected
enum USCI_B0_I2C_2xx.UCLISTEN_t |
![](../../../../../Arrow_up.png) |
Listen enable. The UCLISTEN bit selects loopback mode
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCLISTEN_t
const USCI_B0_I2C_2xx.UCLISTEN_OFF;
// Disabled
const USCI_B0_I2C_2xx.UCLISTEN;
// Enabled. UCAxTXD is internally fed back to the receiver
enum USCI_B0_I2C_2xx.UCMM_t |
![](../../../../../Arrow_up.png) |
Multi-master environment select
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCMM_t
const USCI_B0_I2C_2xx.UCMM_OFF;
// Single master environment. There is no other master in the system. The address compare unit is disabled
const USCI_B0_I2C_2xx.UCMM;
// Multi master environment
enum USCI_B0_I2C_2xx.UCMODE_SYNC_t |
![](../../../../../Arrow_up.png) |
USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCMODE_SYNC_t
const USCI_B0_I2C_2xx.UCMODE_0;
// 3-Pin SPI
const USCI_B0_I2C_2xx.UCMODE_1;
// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
const USCI_B0_I2C_2xx.UCMODE_2;
// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
const USCI_B0_I2C_2xx.UCMODE_3;
// I2C Mode
enum USCI_B0_I2C_2xx.UCMSB_t |
![](../../../../../Arrow_up.png) |
MSB first select. Controls the direction of the receive and transmit shift register
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCMSB_t
const USCI_B0_I2C_2xx.UCMSB_OFF;
// LSB first
const USCI_B0_I2C_2xx.UCMSB;
// MSB first
enum USCI_B0_I2C_2xx.UCMST_t |
![](../../../../../Arrow_up.png) |
Master mode select
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCMST_t
const USCI_B0_I2C_2xx.UCMST_OFF;
// Slave mode
const USCI_B0_I2C_2xx.UCMST;
// Master mode
enum USCI_B0_I2C_2xx.UCNACKIE_t |
![](../../../../../Arrow_up.png) |
Not-acknowledge interrupt enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCNACKIE_t
const USCI_B0_I2C_2xx.UCNACKIE_OFF;
// Interrupt disabled
const USCI_B0_I2C_2xx.UCNACKIE;
// Interrupt enabled
enum USCI_B0_I2C_2xx.UCNACKIFG_t |
![](../../../../../Arrow_up.png) |
Not-acknowledge received interrupt flag
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCNACKIFG_t
const USCI_B0_I2C_2xx.UCNACKIFG_OFF;
// No interrupt pending
const USCI_B0_I2C_2xx.UCNACKIFG;
// Interrupt pending
enum USCI_B0_I2C_2xx.UCOE_t |
![](../../../../../Arrow_up.png) |
Overrun error flag
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCOE_t
const USCI_B0_I2C_2xx.UCOE_OFF;
// No error
const USCI_B0_I2C_2xx.UCOE;
// Overrun error occurred
enum USCI_B0_I2C_2xx.UCPE_t |
![](../../../../../Arrow_up.png) |
Parity error flag. When UCPEN = 0, UCPE is read as 0
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCPE_t
const USCI_B0_I2C_2xx.UCPE_OFF;
// No error
const USCI_B0_I2C_2xx.UCPE;
// Character received with parity error
enum USCI_B0_I2C_2xx.UCRXEIE_t |
![](../../../../../Arrow_up.png) |
Receive erroneous-character interrupt-enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCRXEIE_t
const USCI_B0_I2C_2xx.UCRXEIE_OFF;
// Erroneous characters rejected and UCAxRXIFG is not set
const USCI_B0_I2C_2xx.UCRXEIE;
// Erroneous characters received will set UCAxRXIFG
enum USCI_B0_I2C_2xx.UCRXERR_t |
![](../../../../../Arrow_up.png) |
Bit 2 Receive error flag. This bit indicates a character was received with error(s).
When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also
set. UCRXERR is cleared when UCAxRXBUF is read
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCRXERR_t
const USCI_B0_I2C_2xx.UCRXERR_OFF;
// No receive errors detected
const USCI_B0_I2C_2xx.UCRXERR;
// Receive error detected
enum USCI_B0_I2C_2xx.UCSCLLOW_t |
![](../../../../../Arrow_up.png) |
SCL low
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSCLLOW_t
const USCI_B0_I2C_2xx.UCSCLLOW_OFF;
// SCL is not held low
const USCI_B0_I2C_2xx.UCSCLLOW;
// SCL is held low
enum USCI_B0_I2C_2xx.UCSLA10_t |
![](../../../../../Arrow_up.png) |
Slave addressing mode select
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSLA10_t
const USCI_B0_I2C_2xx.UCSLA10_OFF;
// Address slave with 7-bit address
const USCI_B0_I2C_2xx.UCSLA10;
// Address slave with 10-bit address
enum USCI_B0_I2C_2xx.UCSSEL_I2C_t |
![](../../../../../Arrow_up.png) |
USCI clock source select. These bits select the BRCLK source clock
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSSEL_I2C_t
const USCI_B0_I2C_2xx.UCSSEL_0;
// UCLK
const USCI_B0_I2C_2xx.UCSSEL_1;
// ACLK
const USCI_B0_I2C_2xx.UCSSEL_2;
// SMCLK
enum USCI_B0_I2C_2xx.UCSTPIE_t |
![](../../../../../Arrow_up.png) |
Stop condition interrupt enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSTPIE_t
const USCI_B0_I2C_2xx.UCSTPIE_OFF;
// Interrupt disabled
const USCI_B0_I2C_2xx.UCSTPIE;
// Interrupt enabled
enum USCI_B0_I2C_2xx.UCSTPIFG_t |
![](../../../../../Arrow_up.png) |
Stop condition interrupt flag
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSTPIFG_t
const USCI_B0_I2C_2xx.UCSTPIFG_OFF;
// No interrupt pending
const USCI_B0_I2C_2xx.UCSTPIFG;
// Interrupt pending
enum USCI_B0_I2C_2xx.UCSTTIE_t |
![](../../../../../Arrow_up.png) |
Start condition interrupt enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSTTIE_t
const USCI_B0_I2C_2xx.UCSTTIE_OFF;
// Interrupt disabled
const USCI_B0_I2C_2xx.UCSTTIE;
// Interrupt enabled
enum USCI_B0_I2C_2xx.UCSTTIFG_t |
![](../../../../../Arrow_up.png) |
Start condition interrupt flag
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSTTIFG_t
const USCI_B0_I2C_2xx.UCSTTIFG_OFF;
// No interrupt pending
const USCI_B0_I2C_2xx.UCSTTIFG;
// Interrupt pending
enum USCI_B0_I2C_2xx.UCSWRST_t |
![](../../../../../Arrow_up.png) |
Software reset enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSWRST_t
const USCI_B0_I2C_2xx.UCSWRST_OFF;
// Disabled. USCI reset released for operation
const USCI_B0_I2C_2xx.UCSWRST;
// Enabled. USCI logic held in reset state
enum USCI_B0_I2C_2xx.UCSYNC_t |
![](../../../../../Arrow_up.png) |
Synchronous mode enable
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCSYNC_t
const USCI_B0_I2C_2xx.UCSYNC_OFF;
// Asynchronous mode
const USCI_B0_I2C_2xx.UCSYNC;
// Synchronous Mode
enum USCI_B0_I2C_2xx.UCTR_t |
![](../../../../../Arrow_up.png) |
Transmitter/Receiver
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCTR_t
const USCI_B0_I2C_2xx.UCTR_OFF;
// Receiver
const USCI_B0_I2C_2xx.UCTR;
// Transmitter
enum USCI_B0_I2C_2xx.UCTXADDR_t |
![](../../../../../Arrow_up.png) |
Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCTXADDR_t
const USCI_B0_I2C_2xx.UCTXADDR_OFF;
// Next frame transmitted is data
const USCI_B0_I2C_2xx.UCTXADDR;
// Next frame transmitted is an address
enum USCI_B0_I2C_2xx.UCTXBRK_t |
![](../../../../../Arrow_up.png) |
Transmit break. Transmits a break with the next write to the transmit buffer.
In UART mode with automatic baud rate detection 055h must be written
into UCAxTXBUF to generate the required break/synch fields. Otherwise
0h must be written into the transmit buffer
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCTXBRK_t
const USCI_B0_I2C_2xx.UCTXBRK_OFF;
// Next frame transmitted is not a break
const USCI_B0_I2C_2xx.UCTXBRK;
// Next frame transmitted is a break or a break/synch
enum USCI_B0_I2C_2xx.UCTXNACK_t |
![](../../../../../Arrow_up.png) |
Transmit a NACK
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCTXNACK_t
const USCI_B0_I2C_2xx.UCTXNACK_OFF;
// Acknowledge normally
const USCI_B0_I2C_2xx.UCTXNACK;
// Generate NACK
enum USCI_B0_I2C_2xx.UCTXSTP_t |
![](../../../../../Arrow_up.png) |
Transmit STOP condition in master mode
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCTXSTP_t
const USCI_B0_I2C_2xx.UCTXSTP_OFF;
// No STOP generated
const USCI_B0_I2C_2xx.UCTXSTP;
// Generate STOP
enum USCI_B0_I2C_2xx.UCTXSTT_t |
![](../../../../../Arrow_up.png) |
Transmit START condition in master mode
XDCscript usage |
meta-domain |
values of type USCI_B0_I2C_2xx.UCTXSTT_t
const USCI_B0_I2C_2xx.UCTXSTT_OFF;
// Do not generate START condition
const USCI_B0_I2C_2xx.UCTXSTT;
// Generate START condition
struct USCI_B0_I2C_2xx.ForceSetDefaultRegister_t |
![](../../../../../Arrow_up.png) |
Force Set Default Register
XDCscript usage |
meta-domain |
var obj = new USCI_B0_I2C_2xx.ForceSetDefaultRegister_t;
obj.register = String ...
obj.regForceSet = Bool ...
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct USCI_B0_I2C_2xx.UCBxI2CIE_t |
![](../../../../../Arrow_up.png) |
USCI_Bx I2C Interrupt Enable Register
XDCscript usage |
meta-domain |
var obj = new USCI_B0_I2C_2xx.UCBxI2CIE_t;
// Not-acknowledge interrupt enable
0 Interrupt disabled
1 Interrupt enabled
// Stop condition interrupt enable
0 Interrupt disabled
1 Interrupt enabled
// Start condition interrupt enable
0 Interrupt disabled
1 Interrupt enabled
// Arbitration lost interrupt enable
0 Interrupt disabled
1 Interrupt enabled
struct USCI_B0_I2C_2xx.UCBxI2COA_t |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var obj = new USCI_B0_I2C_2xx.UCBxI2COA_t;
// General call response enable
0 Do not respond to a general call
1 Respond to a general call
obj.I2COA = UChar ...
// I2C own address. The I2COAx bits contain the local address of the USCI_Bx
I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is
the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB
struct USCI_B0_I2C_2xx.UCxCTL0_t |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var obj = new USCI_B0_I2C_2xx.UCxCTL0_t;
// Own addressing mode select
0 Own address is a 7-bit address
1 Own address is a 10-bit address
// Slave addressing mode select
0 Address slave with 7-bit address
1 Address slave with 10-bit address
// Multi-master environment select
0 Single master environment. There is no other master in the system.
The address compare unit is disabled.
1 Multi master environment
// Master mode select. When a master looses arbitration in a multi-master
environment (UCMM = 1) the UCMST bit is automatically cleared and the
module acts as slave.
0 Slave mode
1 Master mode
// USCI Mode. The UCMODEx bits select the synchronous mode when
UCSYNC = 1.
00 3-pin SPI
01 4-pin SPI (master/slave enabled if STE = 1)
10 4-pin SPI (master/slave enabled if STE = 0)
11 I2C mode
// Synchronous mode enable
0 Asynchronous mode
1 Synchronous mode
struct USCI_B0_I2C_2xx.UCxCTL1_t |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var obj = new USCI_B0_I2C_2xx.UCxCTL1_t;
// USCI clock source select. These bits select the BRCLK source clock.
00 UCLKI
01 ACLK
10 SMCLK
11 SMCLK
// Transmitter/Receiver
0 Receiver
1 Transmitter
// Transmit a NACK. UCTXNACK is automatically cleared after a NACK is
transmitted.
0 Acknowledge normally
1 Generate NACK
// Transmit STOP condition in master mode. Ignored in slave mode. In
master receiver mode the STOP condition is preceded by a NACK.
UCTXSTP is automatically cleared after STOP is generated.
0 No STOP generated
1 Generate STOP
// Transmit START condition in master mode. Ignored in slave mode. In
master receiver mode a repeated START condition is preceded by a
NACK. UCTXSTT is automatically cleared after START condition and
address information is transmitted.
Ignored in slave mode.
0 Do not generate START condition
1 Generate START condition
// Software reset enable
0 Disabled. USCI reset released for operation.
1 Enabled. USCI logic held in reset state
struct USCI_B0_I2C_2xx.UCxSTAT_t |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var obj = new USCI_B0_I2C_2xx.UCxSTAT_t;
// SCL low
0 SCL is not held low
1 SCL is held low
// General call address received. UCGC is automatically cleared when a
START condition is received.
0 No general call address received
1 General call address received
// Bus busy
0 Bus inactive
1 Bus busy
// Not-acknowledge received interrupt flag. UCNACKIFG is automatically
cleared when a START condition is received.
0 No interrupt pending
1 Interrupt pending
// Stop condition interrupt flag. UCSTPIFG is automatically cleared when a
START condition is received.
0 No interrupt pending
1 Interrupt pending
// Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP
condition is received.
0 No interrupt pending
1 Interrupt pending
// Arbitration lost interrupt flag
0 No interrupt pending
1 Interrupt pending
USCI_B0_I2C_2xx.getAll() // module-wide |
![](../../../../../Arrow_up.png) |
Find all peripherals of a certain type
XDCscript usage |
meta-domain |
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
USCI_B0_I2C_2xx.getRegisters() // module-wide |
![](../../../../../Arrow_up.png) |
Find all registers defined by the peripheral
XDCscript usage |
meta-domain |
USCI_B0_I2C_2xx.getRegisters() returns String[]
RETURNS
Returns an array of register names
Instance Config Parameters |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
// Instance config-params object
params.UCB0BR0 = Bits8 0;
// Bit Rate Control Register 0
params.UCB0BR1 = Bits8 0;
// Bit Rate Control Register 1
// Control Register 0
};
// Control Register 1
};
// USCI_Bx I2C Interrupt Enable Register
};
// I2C Own Address Register
I2COA: 0
};
params.UCB0I2CSA = Bits8 0;
// I2C Slave Address Register
params.UCB0RXBUF = Bits8 0;
// Receive Buffer Register
// Status Register
};
params.UCB0TXBUF = Bits8 0;
// Transmit Buffer Register
params.UCLKHz = Float 1000000;
// Stores the UCLK external clock frequency in float
// Determine if each Register needs to be forced set or not
{
register: "UCB0CTL0",
regForceSet: false
},
{
register: "UCB0CTL1",
regForceSet: false
},
{
register: "UCB0BR0",
regForceSet: false
},
{
register: "UCB0BR1",
regForceSet: false
},
{
register: "UCB0STAT",
regForceSet: false
},
{
register: "UCB0RXBUF",
regForceSet: false
},
{
register: "UCB0TXBUF",
regForceSet: false
},
{
register: "UCB0I2COA",
regForceSet: false
},
{
register: "UCB0I2CSA",
regForceSet: false
},
{
register: "UCB0I2CIE",
regForceSet: false
}
];
params.name = String undefined;
// Specific peripheral name given by the device
params.owner = String undefined;
// String specifying the entity that manages the peripheral
config USCI_B0_I2C_2xx.UCB0BR0 // instance |
![](../../../../../Arrow_up.png) |
Bit Rate Control Register 0
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
params.UCB0BR0 = Bits8 0;
config USCI_B0_I2C_2xx.UCB0BR1 // instance |
![](../../../../../Arrow_up.png) |
Bit Rate Control Register 1
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
params.UCB0BR1 = Bits8 0;
config USCI_B0_I2C_2xx.UCB0CTL0 // instance |
![](../../../../../Arrow_up.png) |
Control Register 0
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
};
config USCI_B0_I2C_2xx.UCB0CTL1 // instance |
![](../../../../../Arrow_up.png) |
Control Register 1
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
};
config USCI_B0_I2C_2xx.UCB0I2CIE // instance |
![](../../../../../Arrow_up.png) |
USCI_Bx I2C Interrupt Enable Register
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
};
config USCI_B0_I2C_2xx.UCB0I2COA // instance |
![](../../../../../Arrow_up.png) |
I2C Own Address Register
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
I2COA: 0
};
config USCI_B0_I2C_2xx.UCB0I2CSA // instance |
![](../../../../../Arrow_up.png) |
I2C Slave Address Register
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
params.UCB0I2CSA = Bits8 0;
config USCI_B0_I2C_2xx.UCB0RXBUF // instance |
![](../../../../../Arrow_up.png) |
Receive Buffer Register
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
params.UCB0RXBUF = Bits8 0;
config USCI_B0_I2C_2xx.UCB0STAT // instance |
![](../../../../../Arrow_up.png) |
Status Register
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
};
config USCI_B0_I2C_2xx.UCB0TXBUF // instance |
![](../../../../../Arrow_up.png) |
Transmit Buffer Register
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
params.UCB0TXBUF = Bits8 0;
config USCI_B0_I2C_2xx.UCLKHz // instance |
![](../../../../../Arrow_up.png) |
Stores the UCLK external clock frequency in float
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
params.UCLKHz = Float 1000000;
config USCI_B0_I2C_2xx.forceSetDefaultRegister // instance |
![](../../../../../Arrow_up.png) |
Determine if each Register needs to be forced set or not
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
{
register: "UCB0CTL0",
regForceSet: false
},
{
register: "UCB0CTL1",
regForceSet: false
},
{
register: "UCB0BR0",
regForceSet: false
},
{
register: "UCB0BR1",
regForceSet: false
},
{
register: "UCB0STAT",
regForceSet: false
},
{
register: "UCB0RXBUF",
regForceSet: false
},
{
register: "UCB0TXBUF",
regForceSet: false
},
{
register: "UCB0I2COA",
regForceSet: false
},
{
register: "UCB0I2CSA",
regForceSet: false
},
{
register: "UCB0I2CIE",
regForceSet: false
}
];
config USCI_B0_I2C_2xx.name // instance |
![](../../../../../Arrow_up.png) |
Specific peripheral name given by the device
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
params.name = String undefined;
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config USCI_B0_I2C_2xx.owner // instance |
![](../../../../../Arrow_up.png) |
String specifying the entity that manages the peripheral
XDCscript usage |
meta-domain |
var params = new USCI_B0_I2C_2xx.Params;
...
params.owner = String undefined;
Instance Creation |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params =
new USCI_B0_I2C_2xx.
Params;
// Allocate instance config-params
params.config = ...
// Assign individual configs
// Create an instance-object
USCI_B0_I2C_2xx.getUCALIE() // instance |
![](../../../../../Arrow_up.png) |
Gets UCALIE bit
XDCscript usage |
meta-domain |
inst.getUCALIE() returns Bool
SEE
USCI_B0_I2C_2xx.getUCBxI2CSA() // instance |
![](../../../../../Arrow_up.png) |
Returns UCBxI2CSA register value based on which module
XDCscript usage |
meta-domain |
inst.getUCBxI2CSA() returns Bits8
SEE
USCI_B0_I2C_2xx.getUCNACKIE() // instance |
![](../../../../../Arrow_up.png) |
Gets UCNACKIE bit
XDCscript usage |
meta-domain |
inst.getUCNACKIE() returns Bool
SEE
USCI_B0_I2C_2xx.getUCSTPIE() // instance |
![](../../../../../Arrow_up.png) |
Gets UCSTPIE bit
XDCscript usage |
meta-domain |
inst.getUCSTPIE() returns Bool
SEE
USCI_B0_I2C_2xx.getUCSTTIE() // instance |
![](../../../../../Arrow_up.png) |
Gets UCSTTIE bit
XDCscript usage |
meta-domain |
inst.getUCSTTIE() returns Bool
SEE
USCI_B0_I2C_2xx.getUCxxBR0() // instance |
![](../../../../../Arrow_up.png) |
Returns UCxxBR0 register value based on which module
XDCscript usage |
meta-domain |
inst.getUCxxBR0() returns Bits8
SEE
USCI_B0_I2C_2xx.getUCxxBR1() // instance |
![](../../../../../Arrow_up.png) |
Returns UCxxBR1 register value based on which module
XDCscript usage |
meta-domain |
inst.getUCxxBR1() returns Bits8
SEE
USCI_B0_I2C_2xx.getUCxxRXIE() // instance |
![](../../../../../Arrow_up.png) |
Gets UCxxRXIE bit
XDCscript usage |
meta-domain |
inst.getUCxxRXIE() returns Bool
SEE
USCI_B0_I2C_2xx.getUCxxTXIE() // instance |
![](../../../../../Arrow_up.png) |
Gets UCxxTXIE bit
XDCscript usage |
meta-domain |
inst.getUCxxTXIE() returns Bool
SEE
USCI_B0_I2C_2xx.setUCALIE() // instance |
![](../../../../../Arrow_up.png) |
Sets UCALIE bit
XDCscript usage |
meta-domain |
inst.setUCALIE(Bool set) returns Bool
SEE
USCI_B0_I2C_2xx.setUCBxI2CSA() // instance |
![](../../../../../Arrow_up.png) |
Sets UCxxI2CSA register value based on which module
XDCscript usage |
meta-domain |
inst.setUCBxI2CSA(Bits8 value) returns Void
SEE
USCI_B0_I2C_2xx.setUCNACKIE() // instance |
![](../../../../../Arrow_up.png) |
Sets UCNACKIE bit
XDCscript usage |
meta-domain |
inst.setUCNACKIE(Bool set) returns Bool
SEE
USCI_B0_I2C_2xx.setUCSTPIE() // instance |
![](../../../../../Arrow_up.png) |
Sets UCSTPIE bit
XDCscript usage |
meta-domain |
inst.setUCSTPIE(Bool set) returns Bool
SEE
USCI_B0_I2C_2xx.setUCSTTIE() // instance |
![](../../../../../Arrow_up.png) |
Sets UCSTTIE bit
XDCscript usage |
meta-domain |
inst.setUCSTTIE(Bool set) returns Bool
SEE
USCI_B0_I2C_2xx.setUCxxBR0() // instance |
![](../../../../../Arrow_up.png) |
Sets UCxxBR0 register value based on which module
XDCscript usage |
meta-domain |
inst.setUCxxBR0(Bits8 value) returns Void
SEE
USCI_B0_I2C_2xx.setUCxxBR1() // instance |
![](../../../../../Arrow_up.png) |
Sets UCxxBR1 register value based on which module
XDCscript usage |
meta-domain |
inst.setUCxxBR1(Bits8 value) returns Void
SEE
USCI_B0_I2C_2xx.setUCxxRXIE() // instance |
![](../../../../../Arrow_up.png) |
Sets UCxxRXIE bit
XDCscript usage |
meta-domain |
inst.setUCxxRXIE(Bool set) returns Bool
SEE
USCI_B0_I2C_2xx.setUCxxTXIE() // instance |
![](../../../../../Arrow_up.png) |
Sets UCxxTXIE bit
XDCscript usage |
meta-domain |
inst.setUCxxTXIE(Bool set) returns Bool
SEE