metaonly module ti.catalog.msp430.peripherals.communication.USCI_B1_I2C_2xx
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Universal Serial Communication Interface B1 I2C 2xx

XDCscript usage meta-domain sourced in ti/catalog/msp430/peripherals/communication/USCI_B1_I2C_2xx.xdc
var USCI_B1_I2C_2xx = xdc.useModule('ti.catalog.msp430.peripherals.communication.USCI_B1_I2C_2xx');
module-wide constants & types
    values of type USCI_B1_I2C_2xx.UC7BIT_t// Character length. Selects 7-bit or 8-bit character length
        const USCI_B1_I2C_2xx.UC7BIT_OFF// 8-bit;
        const USCI_B1_I2C_2xx.UC7BIT// 7-bit;
 
    values of type USCI_B1_I2C_2xx.UCA10_t// Own addressing mode select
        const USCI_B1_I2C_2xx.UCA10_OFF// Own address is a 7-bit address;
        const USCI_B1_I2C_2xx.UCA10// Own address is a 10-bit address;
 
    values of type USCI_B1_I2C_2xx.UCADDR_t// Address received in address-bit multiprocessor mode
        const USCI_B1_I2C_2xx.UCADDR_OFF// Received character is data;
        const USCI_B1_I2C_2xx.UCADDR// Received character is an address;
 
    values of type USCI_B1_I2C_2xx.UCALIE_t// Arbitration lost interrupt enable
        const USCI_B1_I2C_2xx.UCALIE_OFF// Interrupt disabled;
        const USCI_B1_I2C_2xx.UCALIE// Interrupt enabled;
 
    values of type USCI_B1_I2C_2xx.UCALIFG_t// Arbitration lost interrupt flag
        const USCI_B1_I2C_2xx.UCALIFG_OFF// No interrupt pending;
        const USCI_B1_I2C_2xx.UCALIFG// Interrupt pending;
 
    values of type USCI_B1_I2C_2xx.UCB1RXIE_t// USCI_B1 receive interrupt enable
        const USCI_B1_I2C_2xx.UCB1RXIE_OFF// Interrupt disabled;
        const USCI_B1_I2C_2xx.UCB1RXIE// Interrupt enabled;
 
    values of type USCI_B1_I2C_2xx.UCB1TXIE_t// USCI_B1 transmit interrupt enable
        const USCI_B1_I2C_2xx.UCB1TXIE_OFF// Interrupt disabled;
        const USCI_B1_I2C_2xx.UCB1TXIE// Interrupt enabled;
 
    values of type USCI_B1_I2C_2xx.UCBBUSY_t// Bus busy
        const USCI_B1_I2C_2xx.UCBBUSY_OFF// Bus inactive;
        const USCI_B1_I2C_2xx.UCBBUSY// Bus busy;
 
    values of type USCI_B1_I2C_2xx.UCBRKIE_t// Receive break character interrupt-enable
        const USCI_B1_I2C_2xx.UCBRKIE_OFF// Received break characters do not set UCAxRXIFG;
        const USCI_B1_I2C_2xx.UCBRKIE// Received break characters set UCAxRXIFG;
 
    values of type USCI_B1_I2C_2xx.UCBRK_t// Break detect flag
        const USCI_B1_I2C_2xx.UCBRK_OFF// No break condition;
        const USCI_B1_I2C_2xx.UCBRK// Break condition occurred;
 
    values of type USCI_B1_I2C_2xx.UCBUSY_t// USCI busy. This bit indicates if a transmit or receive operation is in progress
        const USCI_B1_I2C_2xx.UCBUSY_OFF// USCI inactive;
        const USCI_B1_I2C_2xx.UCBUSY// USCI transmitting or receiving;
 
    values of type USCI_B1_I2C_2xx.UCDORM_t// Dormant. Puts USCI into sleep mode
        const USCI_B1_I2C_2xx.UCDORM_OFF// Not dormant. All received characters will set UCAxRXIFG;
        const USCI_B1_I2C_2xx.UCDORM// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG;
 
    values of type USCI_B1_I2C_2xx.UCFE_t// Framing error flag
        const USCI_B1_I2C_2xx.UCFE_OFF// 0 No error;
        const USCI_B1_I2C_2xx.UCFE// Character received with low stop bit;
 
    values of type USCI_B1_I2C_2xx.UCGCEN_t// General call response enable
        const USCI_B1_I2C_2xx.UCGCEN_OFF// Do not respond to a general call;
        const USCI_B1_I2C_2xx.UCGCEN// Respond to a general call;
 
    values of type USCI_B1_I2C_2xx.UCGC_t// General call address received
        const USCI_B1_I2C_2xx.UCGC_OFF// No general call address received;
        const USCI_B1_I2C_2xx.UCGC// General call address received;
 
    values of type USCI_B1_I2C_2xx.UCIDLE_t// Idle line detected in idle-line multiprocessor mode
        const USCI_B1_I2C_2xx.UCIDLE_OFF// No idle line detected;
        const USCI_B1_I2C_2xx.UCIDLE// Idle line detected;
 
    values of type USCI_B1_I2C_2xx.UCLISTEN_t// Listen enable. The UCLISTEN bit selects loopback mode
        const USCI_B1_I2C_2xx.UCLISTEN_OFF// Disabled;
        const USCI_B1_I2C_2xx.UCLISTEN// Enabled. UCAxTXD is internally fed back to the receiver;
 
    values of type USCI_B1_I2C_2xx.UCMM_t// Multi-master environment select
        const USCI_B1_I2C_2xx.UCMM_OFF// Single master environment. There is no other master in the system. The address compare unit is disabled;
        const USCI_B1_I2C_2xx.UCMM// Multi master environment;
 
    values of type USCI_B1_I2C_2xx.UCMODE_SYNC_t// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1
        const USCI_B1_I2C_2xx.UCMODE_0// 3-Pin SPI;
        const USCI_B1_I2C_2xx.UCMODE_1// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1;
        const USCI_B1_I2C_2xx.UCMODE_2// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0;
        const USCI_B1_I2C_2xx.UCMODE_3// I2C Mode;
 
    values of type USCI_B1_I2C_2xx.UCMSB_t// MSB first select. Controls the direction of the receive and transmit shift register
        const USCI_B1_I2C_2xx.UCMSB_OFF// LSB first;
        const USCI_B1_I2C_2xx.UCMSB// MSB first;
 
    values of type USCI_B1_I2C_2xx.UCMST_t// Master mode select
        const USCI_B1_I2C_2xx.UCMST_OFF// Slave mode;
        const USCI_B1_I2C_2xx.UCMST// Master mode;
 
    values of type USCI_B1_I2C_2xx.UCNACKIE_t// Not-acknowledge interrupt enable
        const USCI_B1_I2C_2xx.UCNACKIE_OFF// Interrupt disabled;
        const USCI_B1_I2C_2xx.UCNACKIE// Interrupt enabled;
 
    values of type USCI_B1_I2C_2xx.UCNACKIFG_t// Not-acknowledge received interrupt flag
        const USCI_B1_I2C_2xx.UCNACKIFG_OFF// No interrupt pending;
        const USCI_B1_I2C_2xx.UCNACKIFG// Interrupt pending;
 
    values of type USCI_B1_I2C_2xx.UCOE_t// Overrun error flag
        const USCI_B1_I2C_2xx.UCOE_OFF// No error;
        const USCI_B1_I2C_2xx.UCOE// Overrun error occurred;
 
    values of type USCI_B1_I2C_2xx.UCPE_t// Parity error flag. When UCPEN = 0, UCPE is read as 0
        const USCI_B1_I2C_2xx.UCPE_OFF// No error;
        const USCI_B1_I2C_2xx.UCPE// Character received with parity error;
 
    values of type USCI_B1_I2C_2xx.UCRXEIE_t// Receive erroneous-character interrupt-enable
        const USCI_B1_I2C_2xx.UCRXEIE_OFF// Erroneous characters rejected and UCAxRXIFG is not set;
        const USCI_B1_I2C_2xx.UCRXEIE// Erroneous characters received will set UCAxRXIFG;
 
    values of type USCI_B1_I2C_2xx.UCRXERR_t// Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read
        const USCI_B1_I2C_2xx.UCRXERR_OFF// No receive errors detected;
        const USCI_B1_I2C_2xx.UCRXERR// Receive error detected;
 
    values of type USCI_B1_I2C_2xx.UCSCLLOW_t// SCL low
        const USCI_B1_I2C_2xx.UCSCLLOW_OFF// SCL is not held low;
        const USCI_B1_I2C_2xx.UCSCLLOW// SCL is held low;
 
    values of type USCI_B1_I2C_2xx.UCSLA10_t// Slave addressing mode select
        const USCI_B1_I2C_2xx.UCSLA10_OFF// Address slave with 7-bit address;
        const USCI_B1_I2C_2xx.UCSLA10// Address slave with 10-bit address;
 
    values of type USCI_B1_I2C_2xx.UCSSEL_I2C_t// USCI clock source select. These bits select the BRCLK source clock
        const USCI_B1_I2C_2xx.UCSSEL_0// UCLK;
        const USCI_B1_I2C_2xx.UCSSEL_1// ACLK;
        const USCI_B1_I2C_2xx.UCSSEL_2// SMCLK;
 
    values of type USCI_B1_I2C_2xx.UCSTPIE_t// Stop condition interrupt enable
        const USCI_B1_I2C_2xx.UCSTPIE_OFF// Interrupt disabled;
        const USCI_B1_I2C_2xx.UCSTPIE// Interrupt enabled;
 
    values of type USCI_B1_I2C_2xx.UCSTPIFG_t// Stop condition interrupt flag
        const USCI_B1_I2C_2xx.UCSTPIFG_OFF// No interrupt pending;
        const USCI_B1_I2C_2xx.UCSTPIFG// Interrupt pending;
 
    values of type USCI_B1_I2C_2xx.UCSTTIE_t// Start condition interrupt enable
        const USCI_B1_I2C_2xx.UCSTTIE_OFF// Interrupt disabled;
        const USCI_B1_I2C_2xx.UCSTTIE// Interrupt enabled;
 
    values of type USCI_B1_I2C_2xx.UCSTTIFG_t// Start condition interrupt flag
        const USCI_B1_I2C_2xx.UCSTTIFG_OFF// No interrupt pending;
        const USCI_B1_I2C_2xx.UCSTTIFG// Interrupt pending;
 
    values of type USCI_B1_I2C_2xx.UCSWRST_t// Software reset enable
        const USCI_B1_I2C_2xx.UCSWRST_OFF// Disabled. USCI reset released for operation;
        const USCI_B1_I2C_2xx.UCSWRST// Enabled. USCI logic held in reset state;
 
    values of type USCI_B1_I2C_2xx.UCSYNC_t// Synchronous mode enable
        const USCI_B1_I2C_2xx.UCSYNC_OFF// Asynchronous mode;
        const USCI_B1_I2C_2xx.UCSYNC// Synchronous Mode;
 
    values of type USCI_B1_I2C_2xx.UCTR_t// Transmitter/Receiver
        const USCI_B1_I2C_2xx.UCTR_OFF// Receiver;
        const USCI_B1_I2C_2xx.UCTR// Transmitter;
 
    values of type USCI_B1_I2C_2xx.UCTXADDR_t// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode
        const USCI_B1_I2C_2xx.UCTXADDR_OFF// Next frame transmitted is data;
        const USCI_B1_I2C_2xx.UCTXADDR// Next frame transmitted is an address;
 
    values of type USCI_B1_I2C_2xx.UCTXBRK_t// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer
        const USCI_B1_I2C_2xx.UCTXBRK_OFF// Next frame transmitted is not a break;
        const USCI_B1_I2C_2xx.UCTXBRK// Next frame transmitted is a break or a break/synch;
 
    values of type USCI_B1_I2C_2xx.UCTXNACK_t// Transmit a NACK
        const USCI_B1_I2C_2xx.UCTXNACK_OFF// Acknowledge normally;
        const USCI_B1_I2C_2xx.UCTXNACK// Generate NACK;
 
    values of type USCI_B1_I2C_2xx.UCTXSTP_t// Transmit STOP condition in master mode
        const USCI_B1_I2C_2xx.UCTXSTP_OFF// No STOP generated;
        const USCI_B1_I2C_2xx.UCTXSTP// Generate STOP;
 
    values of type USCI_B1_I2C_2xx.UCTXSTT_t// Transmit START condition in master mode
        const USCI_B1_I2C_2xx.UCTXSTT_OFF// Do not generate START condition;
        const USCI_B1_I2C_2xx.UCTXSTT// Generate START condition;
 
    var obj = new USCI_B1_I2C_2xx.ForceSetDefaultRegister_t// Force Set Default Register;
        obj.register = String  ...
        obj.regForceSet = Bool  ...
 
    var obj = new USCI_B1_I2C_2xx.UC1IE_t// USCI_xx SPI Interrupt Enable Register;
        obj.UCB1TXIE// USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled = USCI_B1_I2C_2xx.UCB1TXIE_t  ...
        obj.UCB1RXIE// USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled = USCI_B1_I2C_2xx.UCB1RXIE_t  ...
 
    var obj = new USCI_B1_I2C_2xx.UCBxI2CIE_t// USCI_Bx I2C Interrupt Enable Register;
        obj.UCNACKIE// Not-acknowledge interrupt enable 0 Interrupt disabled 1 Interrupt enabled = USCI_B1_I2C_2xx.UCNACKIE_t  ...
        obj.UCSTPIE// Stop condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled = USCI_B1_I2C_2xx.UCSTPIE_t  ...
        obj.UCSTTIE// Start condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled = USCI_B1_I2C_2xx.UCSTTIE_t  ...
        obj.UCALIE// Arbitration lost interrupt enable 0 Interrupt disabled 1 Interrupt enabled = USCI_B1_I2C_2xx.UCALIE_t  ...
 
    var obj = new USCI_B1_I2C_2xx.UCBxI2COA_t// ;
        obj.UCGCEN// General call response enable 0 Do not respond to a general call 1 Respond to a general call = IUSCI_I2C.UCGCEN_t  ...
        obj.I2COA// I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB = UChar  ...
 
    var obj = new USCI_B1_I2C_2xx.UCxCTL0_t// ;
        obj.UCA10// Own addressing mode select 0 Own address is a 7-bit address 1 Own address is a 10-bit address = IUSCI_I2C.UCA10_t  ...
        obj.UCSLA10// Slave addressing mode select 0 Address slave with 7-bit address 1 Address slave with 10-bit address = IUSCI_I2C.UCSLA10_t  ...
        obj.UCMM// Multi-master environment select 0 Single master environment. There is no other master in the system. The address compare unit is disabled. 1 Multi master environment = IUSCI_I2C.UCMM_t  ...
        obj.UCMST// Master mode select. When a master looses arbitration in a multi-master environment (UCMM = 1) the UCMST bit is automatically cleared and the module acts as slave. 0 Slave mode 1 Master mode = IUSCI_I2C.UCMST_t  ...
        obj.UCMODE// USCI Mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-pin SPI 01 4-pin SPI (master/slave enabled if STE = 1) 10 4-pin SPI (master/slave enabled if STE = 0) 11 I2C mode = IUSCI_I2C.UCMODE_SYNC_t  ...
        obj.UCSYNC// Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode = IUSCI_I2C.UCSYNC_t  ...
 
    var obj = new USCI_B1_I2C_2xx.UCxCTL1_t// ;
        obj.UCSSEL// USCI clock source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK = IUSCI_I2C.UCSSEL_I2C_t  ...
        obj.UCTR// Transmitter/Receiver 0 Receiver 1 Transmitter = IUSCI_I2C.UCTR_t  ...
        obj.UCTXNACK// Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted. 0 Acknowledge normally 1 Generate NACK = IUSCI_I2C.UCTXNACK_t  ...
        obj.UCTXSTP// Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode the STOP condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated. 0 No STOP generated 1 Generate STOP = IUSCI_I2C.UCTXSTP_t  ...
        obj.UCTXSTT// Transmit START condition in master mode. Ignored in slave mode. In master receiver mode a repeated START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and address information is transmitted. Ignored in slave mode. 0 Do not generate START condition 1 Generate START condition = IUSCI_I2C.UCTXSTT_t  ...
        obj.UCSWRST// Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state = IUSCI_I2C.UCSWRST_t  ...
 
    var obj = new USCI_B1_I2C_2xx.UCxSTAT_t// ;
        obj.UCSCLLOW// SCL low 0 SCL is not held low 1 SCL is held low = IUSCI_I2C.UCSCLLOW_t  ...
        obj.UCGC// General call address received. UCGC is automatically cleared when a START condition is received. 0 No general call address received 1 General call address received = IUSCI_I2C.UCGC_t  ...
        obj.UCBBUSY// Bus busy 0 Bus inactive 1 Bus busy = IUSCI_I2C.UCBBUSY_t  ...
        obj.UCNACKIFG// Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending = IUSCI_I2C.UCNACKIFG_t  ...
        obj.UCSTPIFG// Stop condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending = IUSCI_I2C.UCSTPIFG_t  ...
        obj.UCSTTIFG// Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received. 0 No interrupt pending 1 Interrupt pending = IUSCI_I2C.UCSTTIFG_t  ...
        obj.UCALIFG// Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending = IUSCI_I2C.UCALIFG_t  ...
module-wide functions
    USCI_B1_I2C_2xx.getAll// Find all peripherals of a certain type() returns IPeripheral.Instance[]
    USCI_B1_I2C_2xx.getRegisters// Find all registers defined by the peripheral() returns String[]
per-instance config parameters
    var params = new USCI_B1_I2C_2xx.Params// Instance config-params object;
        params.UC1IE// USCI_B1 Interrupt Enable Register = USCI_B1_I2C_2xx.UC1IE_t {
            UCB1TXIE: USCI_B1_I2C_2xx.UCB1TXIE_OFF,
            UCB1RXIE: USCI_B1_I2C_2xx.UCB1RXIE_OFF
        };
        params.UCB1BR0// Bit Rate Control Register 0 = Bits8 0;
        params.UCB1BR1// Bit Rate Control Register 1 = Bits8 0;
        params.UCB1CTL0// Control Register 0 = IUSCI_B1_I2C.UCxCTL0_t {
            UCA10: IUSCI_I2C.UCA10_OFF,
            UCSLA10: IUSCI_I2C.UCSLA10_OFF,
            UCMM: IUSCI_I2C.UCMM_OFF,
            UCMST: IUSCI_I2C.UCMST_OFF,
            UCMODE: IUSCI.UCMODE_0,
            UCSYNC: IUSCI.UCSYNC
        };
        params.UCB1CTL1// Control Register 1 = IUSCI_B1_I2C.UCxCTL1_t {
            UCSSEL: IUSCI_I2C.UCSSEL_0,
            UCTR: IUSCI_I2C.UCTR_OFF,
            UCTXNACK: IUSCI_I2C.UCTXNACK_OFF,
            UCTXSTP: IUSCI_I2C.UCTXSTP_OFF,
            UCTXSTT: IUSCI_I2C.UCTXSTT_OFF,
            UCSWRST: IUSCI.UCSWRST
        };
        params.UCB1I2CIE// USCI_Bx I2C Interrupt Enable Register = USCI_B1_I2C_2xx.UCBxI2CIE_t {
            UCNACKIE: USCI_B1_I2C_2xx.UCNACKIE_OFF,
            UCSTPIE: USCI_B1_I2C_2xx.UCSTPIE_OFF,
            UCSTTIE: USCI_B1_I2C_2xx.UCSTTIE_OFF,
            UCALIE: USCI_B1_I2C_2xx.UCALIE_OFF
        };
        params.UCB1I2COA// I2C Own Address Register = IUSCI_B1_I2C.UCBxI2COA_t {
            UCGCEN: IUSCI_I2C.UCGCEN_OFF,
            I2COA: 0
        };
        params.UCB1I2CSA// I2C Slave Address Register = Bits8 0;
        params.UCB1RXBUF// Receive Buffer Register = Bits8 0;
        params.UCB1STAT// Status Register = IUSCI_B1_I2C.UCxSTAT_t {
            UCSCLLOW: IUSCI_I2C.UCSCLLOW,
            UCGC: IUSCI_I2C.UCGC,
            UCBBUSY: IUSCI_I2C.UCBBUSY,
            UCNACKIFG: IUSCI_I2C.UCNACKIFG,
            UCSTPIFG: IUSCI_I2C.UCSTPIFG,
            UCSTTIFG: IUSCI_I2C.UCSTTIFG,
            UCALIFG: IUSCI_I2C.UCALIFG
        };
        params.UCB1TXBUF// Transmit Buffer Register = Bits8 0;
        params.UCLKHz// Stores the UCLK external clock frequency in float = Float 1000000;
        params.forceSetDefaultRegister// Determine if each Register needs to be forced set or not = USCI_B1_I2C_2xx.ForceSetDefaultRegister_t[] [
            {
                register: "UCB1CTL0",
                regForceSet: false
            },
            {
                register: "UCB1CTL1",
                regForceSet: false
            },
            {
                register: "UCB1BR0",
                regForceSet: false
            },
            {
                register: "UCB1BR1",
                regForceSet: false
            },
            {
                register: "UCB1STAT",
                regForceSet: false
            },
            {
                register: "UCB1RXBUF",
                regForceSet: false
            },
            {
                register: "UCB1TXBUF",
                regForceSet: false
            },
            {
                register: "UCB1I2COA",
                regForceSet: false
            },
            {
                register: "UCB1I2CSA",
                regForceSet: false
            },
            {
                register: "UCB1I2CIE",
                regForceSet: false
            },
            {
                register: "UC1IE",
                regForceSet: false
            }
        ];
        params.name// Specific peripheral name given by the device = String undefined;
        params.owner// String specifying the entity that manages the peripheral = String undefined;
per-instance creation
    var inst = USCI_B1_I2C_2xx.create// Create an instance-object(IClock.Instance clock, params);
per-instance functions
    inst.getUCALIE// Gets UCALIE bit() returns Bool
    inst.getUCBxI2CSA// Returns UCBxI2CSA register value based on which module() returns Bits8
    inst.getUCNACKIE// Gets UCNACKIE bit() returns Bool
    inst.getUCSTPIE// Gets UCSTPIE bit() returns Bool
    inst.getUCSTTIE// Gets UCSTTIE bit() returns Bool
    inst.getUCxxBR0// Returns UCxxBR0 register value based on which module() returns Bits8
    inst.getUCxxBR1// Returns UCxxBR1 register value based on which module() returns Bits8
    inst.getUCxxRXIE// Gets UCxxRXIE bit() returns Bool
    inst.getUCxxTXIE// Gets UCxxTXIE bit() returns Bool
    inst.setUCALIE// Sets UCALIE bit(Bool set) returns Bool
    inst.setUCBxI2CSA// Sets UCxxI2CSA register value based on which module(Bits8 value) returns Void
    inst.setUCNACKIE// Sets UCNACKIE bit(Bool set) returns Bool
    inst.setUCSTPIE// Sets UCSTPIE bit(Bool set) returns Bool
    inst.setUCSTTIE// Sets UCSTTIE bit(Bool set) returns Bool
    inst.setUCxxBR0// Sets UCxxBR0 register value based on which module(Bits8 value) returns Void
    inst.setUCxxBR1// Sets UCxxBR1 register value based on which module(Bits8 value) returns Void
    inst.setUCxxRXIE// Sets UCxxRXIE bit(Bool set) returns Bool
    inst.setUCxxTXIE// Sets UCxxTXIE bit(Bool set) returns Bool
 
 
enum USCI_B1_I2C_2xx.UC7BIT_t
index URL

Character length. Selects 7-bit or 8-bit character length

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UC7BIT_t
    const USCI_B1_I2C_2xx.UC7BIT_OFF;
    // 8-bit
    const USCI_B1_I2C_2xx.UC7BIT;
    // 7-bit
 
 
enum USCI_B1_I2C_2xx.UCA10_t
index URL

Own addressing mode select

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCA10_t
    const USCI_B1_I2C_2xx.UCA10_OFF;
    // Own address is a 7-bit address
    const USCI_B1_I2C_2xx.UCA10;
    // Own address is a 10-bit address
 
 
enum USCI_B1_I2C_2xx.UCADDR_t
index URL

Address received in address-bit multiprocessor mode

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCADDR_t
    const USCI_B1_I2C_2xx.UCADDR_OFF;
    // Received character is data
    const USCI_B1_I2C_2xx.UCADDR;
    // Received character is an address
 
 
enum USCI_B1_I2C_2xx.UCALIE_t
index URL

Arbitration lost interrupt enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCALIE_t
    const USCI_B1_I2C_2xx.UCALIE_OFF;
    // Interrupt disabled
    const USCI_B1_I2C_2xx.UCALIE;
    // Interrupt enabled
 
 
enum USCI_B1_I2C_2xx.UCALIFG_t
index URL

Arbitration lost interrupt flag

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCALIFG_t
    const USCI_B1_I2C_2xx.UCALIFG_OFF;
    // No interrupt pending
    const USCI_B1_I2C_2xx.UCALIFG;
    // Interrupt pending
 
 
enum USCI_B1_I2C_2xx.UCB1RXIE_t
index URL

USCI_B1 receive interrupt enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCB1RXIE_t
    const USCI_B1_I2C_2xx.UCB1RXIE_OFF;
    // Interrupt disabled
    const USCI_B1_I2C_2xx.UCB1RXIE;
    // Interrupt enabled
 
 
enum USCI_B1_I2C_2xx.UCB1TXIE_t
index URL

USCI_B1 transmit interrupt enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCB1TXIE_t
    const USCI_B1_I2C_2xx.UCB1TXIE_OFF;
    // Interrupt disabled
    const USCI_B1_I2C_2xx.UCB1TXIE;
    // Interrupt enabled
 
 
enum USCI_B1_I2C_2xx.UCBBUSY_t
index URL

Bus busy

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCBBUSY_t
    const USCI_B1_I2C_2xx.UCBBUSY_OFF;
    // Bus inactive
    const USCI_B1_I2C_2xx.UCBBUSY;
    // Bus busy
 
 
enum USCI_B1_I2C_2xx.UCBRKIE_t
index URL

Receive break character interrupt-enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCBRKIE_t
    const USCI_B1_I2C_2xx.UCBRKIE_OFF;
    // Received break characters do not set UCAxRXIFG
    const USCI_B1_I2C_2xx.UCBRKIE;
    // Received break characters set UCAxRXIFG
 
 
enum USCI_B1_I2C_2xx.UCBRK_t
index URL

Break detect flag

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCBRK_t
    const USCI_B1_I2C_2xx.UCBRK_OFF;
    // No break condition
    const USCI_B1_I2C_2xx.UCBRK;
    // Break condition occurred
 
 
enum USCI_B1_I2C_2xx.UCBUSY_t
index URL

USCI busy. This bit indicates if a transmit or receive operation is in progress

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCBUSY_t
    const USCI_B1_I2C_2xx.UCBUSY_OFF;
    // USCI inactive
    const USCI_B1_I2C_2xx.UCBUSY;
    // USCI transmitting or receiving
 
 
enum USCI_B1_I2C_2xx.UCDORM_t
index URL

Dormant. Puts USCI into sleep mode

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCDORM_t
    const USCI_B1_I2C_2xx.UCDORM_OFF;
    // Not dormant. All received characters will set UCAxRXIFG
    const USCI_B1_I2C_2xx.UCDORM;
    // Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
 
 
enum USCI_B1_I2C_2xx.UCFE_t
index URL

Framing error flag

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCFE_t
    const USCI_B1_I2C_2xx.UCFE_OFF;
    // 0 No error
    const USCI_B1_I2C_2xx.UCFE;
    // Character received with low stop bit
 
 
enum USCI_B1_I2C_2xx.UCGCEN_t
index URL

General call response enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCGCEN_t
    const USCI_B1_I2C_2xx.UCGCEN_OFF;
    // Do not respond to a general call
    const USCI_B1_I2C_2xx.UCGCEN;
    // Respond to a general call
 
 
enum USCI_B1_I2C_2xx.UCGC_t
index URL

General call address received

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCGC_t
    const USCI_B1_I2C_2xx.UCGC_OFF;
    // No general call address received
    const USCI_B1_I2C_2xx.UCGC;
    // General call address received
 
 
enum USCI_B1_I2C_2xx.UCIDLE_t
index URL

Idle line detected in idle-line multiprocessor mode

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCIDLE_t
    const USCI_B1_I2C_2xx.UCIDLE_OFF;
    // No idle line detected
    const USCI_B1_I2C_2xx.UCIDLE;
    // Idle line detected
 
 
enum USCI_B1_I2C_2xx.UCLISTEN_t
index URL

Listen enable. The UCLISTEN bit selects loopback mode

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCLISTEN_t
    const USCI_B1_I2C_2xx.UCLISTEN_OFF;
    // Disabled
    const USCI_B1_I2C_2xx.UCLISTEN;
    // Enabled. UCAxTXD is internally fed back to the receiver
 
 
enum USCI_B1_I2C_2xx.UCMM_t
index URL

Multi-master environment select

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCMM_t
    const USCI_B1_I2C_2xx.UCMM_OFF;
    // Single master environment. There is no other master in the system. The address compare unit is disabled
    const USCI_B1_I2C_2xx.UCMM;
    // Multi master environment
 
 
enum USCI_B1_I2C_2xx.UCMODE_SYNC_t
index URL

USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCMODE_SYNC_t
    const USCI_B1_I2C_2xx.UCMODE_0;
    // 3-Pin SPI
    const USCI_B1_I2C_2xx.UCMODE_1;
    // 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
    const USCI_B1_I2C_2xx.UCMODE_2;
    // 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
    const USCI_B1_I2C_2xx.UCMODE_3;
    // I2C Mode
 
 
enum USCI_B1_I2C_2xx.UCMSB_t
index URL

MSB first select. Controls the direction of the receive and transmit shift register

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCMSB_t
    const USCI_B1_I2C_2xx.UCMSB_OFF;
    // LSB first
    const USCI_B1_I2C_2xx.UCMSB;
    // MSB first
 
 
enum USCI_B1_I2C_2xx.UCMST_t
index URL

Master mode select

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCMST_t
    const USCI_B1_I2C_2xx.UCMST_OFF;
    // Slave mode
    const USCI_B1_I2C_2xx.UCMST;
    // Master mode
 
 
enum USCI_B1_I2C_2xx.UCNACKIE_t
index URL

Not-acknowledge interrupt enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCNACKIE_t
    const USCI_B1_I2C_2xx.UCNACKIE_OFF;
    // Interrupt disabled
    const USCI_B1_I2C_2xx.UCNACKIE;
    // Interrupt enabled
 
 
enum USCI_B1_I2C_2xx.UCNACKIFG_t
index URL

Not-acknowledge received interrupt flag

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCNACKIFG_t
    const USCI_B1_I2C_2xx.UCNACKIFG_OFF;
    // No interrupt pending
    const USCI_B1_I2C_2xx.UCNACKIFG;
    // Interrupt pending
 
 
enum USCI_B1_I2C_2xx.UCOE_t
index URL

Overrun error flag

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCOE_t
    const USCI_B1_I2C_2xx.UCOE_OFF;
    // No error
    const USCI_B1_I2C_2xx.UCOE;
    // Overrun error occurred
 
 
enum USCI_B1_I2C_2xx.UCPE_t
index URL

Parity error flag. When UCPEN = 0, UCPE is read as 0

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCPE_t
    const USCI_B1_I2C_2xx.UCPE_OFF;
    // No error
    const USCI_B1_I2C_2xx.UCPE;
    // Character received with parity error
 
 
enum USCI_B1_I2C_2xx.UCRXEIE_t
index URL

Receive erroneous-character interrupt-enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCRXEIE_t
    const USCI_B1_I2C_2xx.UCRXEIE_OFF;
    // Erroneous characters rejected and UCAxRXIFG is not set
    const USCI_B1_I2C_2xx.UCRXEIE;
    // Erroneous characters received will set UCAxRXIFG
 
 
enum USCI_B1_I2C_2xx.UCRXERR_t
index URL

Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCRXERR_t
    const USCI_B1_I2C_2xx.UCRXERR_OFF;
    // No receive errors detected
    const USCI_B1_I2C_2xx.UCRXERR;
    // Receive error detected
 
 
enum USCI_B1_I2C_2xx.UCSCLLOW_t
index URL

SCL low

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSCLLOW_t
    const USCI_B1_I2C_2xx.UCSCLLOW_OFF;
    // SCL is not held low
    const USCI_B1_I2C_2xx.UCSCLLOW;
    // SCL is held low
 
 
enum USCI_B1_I2C_2xx.UCSLA10_t
index URL

Slave addressing mode select

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSLA10_t
    const USCI_B1_I2C_2xx.UCSLA10_OFF;
    // Address slave with 7-bit address
    const USCI_B1_I2C_2xx.UCSLA10;
    // Address slave with 10-bit address
 
 
enum USCI_B1_I2C_2xx.UCSSEL_I2C_t
index URL

USCI clock source select. These bits select the BRCLK source clock

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSSEL_I2C_t
    const USCI_B1_I2C_2xx.UCSSEL_0;
    // UCLK
    const USCI_B1_I2C_2xx.UCSSEL_1;
    // ACLK
    const USCI_B1_I2C_2xx.UCSSEL_2;
    // SMCLK
 
 
enum USCI_B1_I2C_2xx.UCSTPIE_t
index URL

Stop condition interrupt enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSTPIE_t
    const USCI_B1_I2C_2xx.UCSTPIE_OFF;
    // Interrupt disabled
    const USCI_B1_I2C_2xx.UCSTPIE;
    // Interrupt enabled
 
 
enum USCI_B1_I2C_2xx.UCSTPIFG_t
index URL

Stop condition interrupt flag

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSTPIFG_t
    const USCI_B1_I2C_2xx.UCSTPIFG_OFF;
    // No interrupt pending
    const USCI_B1_I2C_2xx.UCSTPIFG;
    // Interrupt pending
 
 
enum USCI_B1_I2C_2xx.UCSTTIE_t
index URL

Start condition interrupt enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSTTIE_t
    const USCI_B1_I2C_2xx.UCSTTIE_OFF;
    // Interrupt disabled
    const USCI_B1_I2C_2xx.UCSTTIE;
    // Interrupt enabled
 
 
enum USCI_B1_I2C_2xx.UCSTTIFG_t
index URL

Start condition interrupt flag

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSTTIFG_t
    const USCI_B1_I2C_2xx.UCSTTIFG_OFF;
    // No interrupt pending
    const USCI_B1_I2C_2xx.UCSTTIFG;
    // Interrupt pending
 
 
enum USCI_B1_I2C_2xx.UCSWRST_t
index URL

Software reset enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSWRST_t
    const USCI_B1_I2C_2xx.UCSWRST_OFF;
    // Disabled. USCI reset released for operation
    const USCI_B1_I2C_2xx.UCSWRST;
    // Enabled. USCI logic held in reset state
 
 
enum USCI_B1_I2C_2xx.UCSYNC_t
index URL

Synchronous mode enable

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCSYNC_t
    const USCI_B1_I2C_2xx.UCSYNC_OFF;
    // Asynchronous mode
    const USCI_B1_I2C_2xx.UCSYNC;
    // Synchronous Mode
 
 
enum USCI_B1_I2C_2xx.UCTR_t
index URL

Transmitter/Receiver

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCTR_t
    const USCI_B1_I2C_2xx.UCTR_OFF;
    // Receiver
    const USCI_B1_I2C_2xx.UCTR;
    // Transmitter
 
 
enum USCI_B1_I2C_2xx.UCTXADDR_t
index URL

Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCTXADDR_t
    const USCI_B1_I2C_2xx.UCTXADDR_OFF;
    // Next frame transmitted is data
    const USCI_B1_I2C_2xx.UCTXADDR;
    // Next frame transmitted is an address
 
 
enum USCI_B1_I2C_2xx.UCTXBRK_t
index URL

Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCTXBRK_t
    const USCI_B1_I2C_2xx.UCTXBRK_OFF;
    // Next frame transmitted is not a break
    const USCI_B1_I2C_2xx.UCTXBRK;
    // Next frame transmitted is a break or a break/synch
 
 
enum USCI_B1_I2C_2xx.UCTXNACK_t
index URL

Transmit a NACK

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCTXNACK_t
    const USCI_B1_I2C_2xx.UCTXNACK_OFF;
    // Acknowledge normally
    const USCI_B1_I2C_2xx.UCTXNACK;
    // Generate NACK
 
 
enum USCI_B1_I2C_2xx.UCTXSTP_t
index URL

Transmit STOP condition in master mode

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCTXSTP_t
    const USCI_B1_I2C_2xx.UCTXSTP_OFF;
    // No STOP generated
    const USCI_B1_I2C_2xx.UCTXSTP;
    // Generate STOP
 
 
enum USCI_B1_I2C_2xx.UCTXSTT_t
index URL

Transmit START condition in master mode

XDCscript usage meta-domain
values of type USCI_B1_I2C_2xx.UCTXSTT_t
    const USCI_B1_I2C_2xx.UCTXSTT_OFF;
    // Do not generate START condition
    const USCI_B1_I2C_2xx.UCTXSTT;
    // Generate START condition
 
 
struct USCI_B1_I2C_2xx.ForceSetDefaultRegister_t
index URL

Force Set Default Register

XDCscript usage meta-domain
var obj = new USCI_B1_I2C_2xx.ForceSetDefaultRegister_t;
 
    obj.register = String  ...
    obj.regForceSet = Bool  ...
 
DETAILS
Type to store if each register needs to be forced initialized even if the register is in default state.
SEE
ForceSetDefaultRegister_t
 
struct USCI_B1_I2C_2xx.UC1IE_t
index URL

USCI_xx SPI Interrupt Enable Register

XDCscript usage meta-domain
var obj = new USCI_B1_I2C_2xx.UC1IE_t;
 
    obj.UCB1TXIE = USCI_B1_I2C_2xx.UCB1TXIE_t  ...
    // USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled
    obj.UCB1RXIE = USCI_B1_I2C_2xx.UCB1RXIE_t  ...
    // USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled
 
 
struct USCI_B1_I2C_2xx.UCBxI2CIE_t
index URL

USCI_Bx I2C Interrupt Enable Register

XDCscript usage meta-domain
var obj = new USCI_B1_I2C_2xx.UCBxI2CIE_t;
 
    obj.UCNACKIE = USCI_B1_I2C_2xx.UCNACKIE_t  ...
    // Not-acknowledge interrupt enable 0 Interrupt disabled 1 Interrupt enabled
    obj.UCSTPIE = USCI_B1_I2C_2xx.UCSTPIE_t  ...
    // Stop condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled
    obj.UCSTTIE = USCI_B1_I2C_2xx.UCSTTIE_t  ...
    // Start condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled
    obj.UCALIE = USCI_B1_I2C_2xx.UCALIE_t  ...
    // Arbitration lost interrupt enable 0 Interrupt disabled 1 Interrupt enabled
 
 
struct USCI_B1_I2C_2xx.UCBxI2COA_t
index URL
XDCscript usage meta-domain
var obj = new USCI_B1_I2C_2xx.UCBxI2COA_t;
 
    obj.UCGCEN = IUSCI_I2C.UCGCEN_t  ...
    // General call response enable 0 Do not respond to a general call 1 Respond to a general call
    obj.I2COA = UChar  ...
    // I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB
 
 
struct USCI_B1_I2C_2xx.UCxCTL0_t
index URL
XDCscript usage meta-domain
var obj = new USCI_B1_I2C_2xx.UCxCTL0_t;
 
    obj.UCA10 = IUSCI_I2C.UCA10_t  ...
    // Own addressing mode select 0 Own address is a 7-bit address 1 Own address is a 10-bit address
    obj.UCSLA10 = IUSCI_I2C.UCSLA10_t  ...
    // Slave addressing mode select 0 Address slave with 7-bit address 1 Address slave with 10-bit address
    obj.UCMM = IUSCI_I2C.UCMM_t  ...
    // Multi-master environment select 0 Single master environment. There is no other master in the system. The address compare unit is disabled. 1 Multi master environment
    obj.UCMST = IUSCI_I2C.UCMST_t  ...
    // Master mode select. When a master looses arbitration in a multi-master environment (UCMM = 1) the UCMST bit is automatically cleared and the module acts as slave. 0 Slave mode 1 Master mode
    obj.UCMODE = IUSCI_I2C.UCMODE_SYNC_t  ...
    // USCI Mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-pin SPI 01 4-pin SPI (master/slave enabled if STE = 1) 10 4-pin SPI (master/slave enabled if STE = 0) 11 I2C mode
    obj.UCSYNC = IUSCI_I2C.UCSYNC_t  ...
    // Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode
 
 
struct USCI_B1_I2C_2xx.UCxCTL1_t
index URL
XDCscript usage meta-domain
var obj = new USCI_B1_I2C_2xx.UCxCTL1_t;
 
    obj.UCSSEL = IUSCI_I2C.UCSSEL_I2C_t  ...
    // USCI clock source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK
    obj.UCTR = IUSCI_I2C.UCTR_t  ...
    // Transmitter/Receiver 0 Receiver 1 Transmitter
    obj.UCTXNACK = IUSCI_I2C.UCTXNACK_t  ...
    // Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted. 0 Acknowledge normally 1 Generate NACK
    obj.UCTXSTP = IUSCI_I2C.UCTXSTP_t  ...
    // Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode the STOP condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated. 0 No STOP generated 1 Generate STOP
    obj.UCTXSTT = IUSCI_I2C.UCTXSTT_t  ...
    // Transmit START condition in master mode. Ignored in slave mode. In master receiver mode a repeated START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and address information is transmitted. Ignored in slave mode. 0 Do not generate START condition 1 Generate START condition
    obj.UCSWRST = IUSCI_I2C.UCSWRST_t  ...
    // Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state
 
 
struct USCI_B1_I2C_2xx.UCxSTAT_t
index URL
XDCscript usage meta-domain
var obj = new USCI_B1_I2C_2xx.UCxSTAT_t;
 
    obj.UCSCLLOW = IUSCI_I2C.UCSCLLOW_t  ...
    // SCL low 0 SCL is not held low 1 SCL is held low
    obj.UCGC = IUSCI_I2C.UCGC_t  ...
    // General call address received. UCGC is automatically cleared when a START condition is received. 0 No general call address received 1 General call address received
    obj.UCBBUSY = IUSCI_I2C.UCBBUSY_t  ...
    // Bus busy 0 Bus inactive 1 Bus busy
    obj.UCNACKIFG = IUSCI_I2C.UCNACKIFG_t  ...
    // Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending
    obj.UCSTPIFG = IUSCI_I2C.UCSTPIFG_t  ...
    // Stop condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending
    obj.UCSTTIFG = IUSCI_I2C.UCSTTIFG_t  ...
    // Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received. 0 No interrupt pending 1 Interrupt pending
    obj.UCALIFG = IUSCI_I2C.UCALIFG_t  ...
    // Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending
 
 
USCI_B1_I2C_2xx.getAll()  // module-wide
index URL

Find all peripherals of a certain type

XDCscript usage meta-domain
USCI_B1_I2C_2xx.getAll() returns IPeripheral.Instance[]
 
DETAILS
The type of the peripherals returned is defined by the type of the caller.
RETURNS
Returns an array of IPeripheral instances
 
USCI_B1_I2C_2xx.getRegisters()  // module-wide
index URL

Find all registers defined by the peripheral

XDCscript usage meta-domain
USCI_B1_I2C_2xx.getRegisters() returns String[]
 
RETURNS
Returns an array of register names
Instance Config Parameters
index URL

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
// Instance config-params object
    params.UC1IE = USCI_B1_I2C_2xx.UC1IE_t {
    // USCI_B1 Interrupt Enable Register
        UCB1TXIE: USCI_B1_I2C_2xx.UCB1TXIE_OFF,
        UCB1RXIE: USCI_B1_I2C_2xx.UCB1RXIE_OFF
    };
    params.UCB1BR0 = Bits8 0;
    // Bit Rate Control Register 0
    params.UCB1BR1 = Bits8 0;
    // Bit Rate Control Register 1
    params.UCB1CTL0 = IUSCI_B1_I2C.UCxCTL0_t {
    // Control Register 0
        UCA10: IUSCI_I2C.UCA10_OFF,
        UCSLA10: IUSCI_I2C.UCSLA10_OFF,
        UCMM: IUSCI_I2C.UCMM_OFF,
        UCMST: IUSCI_I2C.UCMST_OFF,
        UCMODE: IUSCI.UCMODE_0,
        UCSYNC: IUSCI.UCSYNC
    };
    params.UCB1CTL1 = IUSCI_B1_I2C.UCxCTL1_t {
    // Control Register 1
        UCSSEL: IUSCI_I2C.UCSSEL_0,
        UCTR: IUSCI_I2C.UCTR_OFF,
        UCTXNACK: IUSCI_I2C.UCTXNACK_OFF,
        UCTXSTP: IUSCI_I2C.UCTXSTP_OFF,
        UCTXSTT: IUSCI_I2C.UCTXSTT_OFF,
        UCSWRST: IUSCI.UCSWRST
    };
    params.UCB1I2CIE = USCI_B1_I2C_2xx.UCBxI2CIE_t {
    // USCI_Bx I2C Interrupt Enable Register
        UCNACKIE: USCI_B1_I2C_2xx.UCNACKIE_OFF,
        UCSTPIE: USCI_B1_I2C_2xx.UCSTPIE_OFF,
        UCSTTIE: USCI_B1_I2C_2xx.UCSTTIE_OFF,
        UCALIE: USCI_B1_I2C_2xx.UCALIE_OFF
    };
    params.UCB1I2COA = IUSCI_B1_I2C.UCBxI2COA_t {
    // I2C Own Address Register
        UCGCEN: IUSCI_I2C.UCGCEN_OFF,
        I2COA: 0
    };
    params.UCB1I2CSA = Bits8 0;
    // I2C Slave Address Register
    params.UCB1RXBUF = Bits8 0;
    // Receive Buffer Register
    params.UCB1STAT = IUSCI_B1_I2C.UCxSTAT_t {
    // Status Register
        UCSCLLOW: IUSCI_I2C.UCSCLLOW,
        UCGC: IUSCI_I2C.UCGC,
        UCBBUSY: IUSCI_I2C.UCBBUSY,
        UCNACKIFG: IUSCI_I2C.UCNACKIFG,
        UCSTPIFG: IUSCI_I2C.UCSTPIFG,
        UCSTTIFG: IUSCI_I2C.UCSTTIFG,
        UCALIFG: IUSCI_I2C.UCALIFG
    };
    params.UCB1TXBUF = Bits8 0;
    // Transmit Buffer Register
    params.UCLKHz = Float 1000000;
    // Stores the UCLK external clock frequency in float
    params.forceSetDefaultRegister = USCI_B1_I2C_2xx.ForceSetDefaultRegister_t[] [
    // Determine if each Register needs to be forced set or not
        {
            register: "UCB1CTL0",
            regForceSet: false
        },
        {
            register: "UCB1CTL1",
            regForceSet: false
        },
        {
            register: "UCB1BR0",
            regForceSet: false
        },
        {
            register: "UCB1BR1",
            regForceSet: false
        },
        {
            register: "UCB1STAT",
            regForceSet: false
        },
        {
            register: "UCB1RXBUF",
            regForceSet: false
        },
        {
            register: "UCB1TXBUF",
            regForceSet: false
        },
        {
            register: "UCB1I2COA",
            regForceSet: false
        },
        {
            register: "UCB1I2CSA",
            regForceSet: false
        },
        {
            register: "UCB1I2CIE",
            regForceSet: false
        },
        {
            register: "UC1IE",
            regForceSet: false
        }
    ];
    params.name = String undefined;
    // Specific peripheral name given by the device
    params.owner = String undefined;
    // String specifying the entity that manages the peripheral
 
config USCI_B1_I2C_2xx.UC1IE  // instance
index URL

USCI_B1 Interrupt Enable Register

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UC1IE = USCI_B1_I2C_2xx.UC1IE_t {
    UCB1TXIE: USCI_B1_I2C_2xx.UCB1TXIE_OFF,
    UCB1RXIE: USCI_B1_I2C_2xx.UCB1RXIE_OFF
};
 
 
config USCI_B1_I2C_2xx.UCB1BR0  // instance
index URL

Bit Rate Control Register 0

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1BR0 = Bits8 0;
 
 
config USCI_B1_I2C_2xx.UCB1BR1  // instance
index URL

Bit Rate Control Register 1

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1BR1 = Bits8 0;
 
 
config USCI_B1_I2C_2xx.UCB1CTL0  // instance
index URL

Control Register 0

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1CTL0 = IUSCI_B1_I2C.UCxCTL0_t {
    UCA10: IUSCI_I2C.UCA10_OFF,
    UCSLA10: IUSCI_I2C.UCSLA10_OFF,
    UCMM: IUSCI_I2C.UCMM_OFF,
    UCMST: IUSCI_I2C.UCMST_OFF,
    UCMODE: IUSCI.UCMODE_0,
    UCSYNC: IUSCI.UCSYNC
};
 
 
config USCI_B1_I2C_2xx.UCB1CTL1  // instance
index URL

Control Register 1

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1CTL1 = IUSCI_B1_I2C.UCxCTL1_t {
    UCSSEL: IUSCI_I2C.UCSSEL_0,
    UCTR: IUSCI_I2C.UCTR_OFF,
    UCTXNACK: IUSCI_I2C.UCTXNACK_OFF,
    UCTXSTP: IUSCI_I2C.UCTXSTP_OFF,
    UCTXSTT: IUSCI_I2C.UCTXSTT_OFF,
    UCSWRST: IUSCI.UCSWRST
};
 
 
config USCI_B1_I2C_2xx.UCB1I2CIE  // instance
index URL

USCI_Bx I2C Interrupt Enable Register

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1I2CIE = USCI_B1_I2C_2xx.UCBxI2CIE_t {
    UCNACKIE: USCI_B1_I2C_2xx.UCNACKIE_OFF,
    UCSTPIE: USCI_B1_I2C_2xx.UCSTPIE_OFF,
    UCSTTIE: USCI_B1_I2C_2xx.UCSTTIE_OFF,
    UCALIE: USCI_B1_I2C_2xx.UCALIE_OFF
};
 
 
config USCI_B1_I2C_2xx.UCB1I2COA  // instance
index URL

I2C Own Address Register

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1I2COA = IUSCI_B1_I2C.UCBxI2COA_t {
    UCGCEN: IUSCI_I2C.UCGCEN_OFF,
    I2COA: 0
};
 
 
config USCI_B1_I2C_2xx.UCB1I2CSA  // instance
index URL

I2C Slave Address Register

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1I2CSA = Bits8 0;
 
 
config USCI_B1_I2C_2xx.UCB1RXBUF  // instance
index URL

Receive Buffer Register

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1RXBUF = Bits8 0;
 
 
config USCI_B1_I2C_2xx.UCB1STAT  // instance
index URL

Status Register

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1STAT = IUSCI_B1_I2C.UCxSTAT_t {
    UCSCLLOW: IUSCI_I2C.UCSCLLOW,
    UCGC: IUSCI_I2C.UCGC,
    UCBBUSY: IUSCI_I2C.UCBBUSY,
    UCNACKIFG: IUSCI_I2C.UCNACKIFG,
    UCSTPIFG: IUSCI_I2C.UCSTPIFG,
    UCSTTIFG: IUSCI_I2C.UCSTTIFG,
    UCALIFG: IUSCI_I2C.UCALIFG
};
 
 
config USCI_B1_I2C_2xx.UCB1TXBUF  // instance
index URL

Transmit Buffer Register

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCB1TXBUF = Bits8 0;
 
 
config USCI_B1_I2C_2xx.UCLKHz  // instance
index URL

Stores the UCLK external clock frequency in float

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.UCLKHz = Float 1000000;
 
 
config USCI_B1_I2C_2xx.forceSetDefaultRegister  // instance
index URL

Determine if each Register needs to be forced set or not

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
const params.forceSetDefaultRegister = USCI_B1_I2C_2xx.ForceSetDefaultRegister_t[] [
    {
        register: "UCB1CTL0",
        regForceSet: false
    },
    {
        register: "UCB1CTL1",
        regForceSet: false
    },
    {
        register: "UCB1BR0",
        regForceSet: false
    },
    {
        register: "UCB1BR1",
        regForceSet: false
    },
    {
        register: "UCB1STAT",
        regForceSet: false
    },
    {
        register: "UCB1RXBUF",
        regForceSet: false
    },
    {
        register: "UCB1TXBUF",
        regForceSet: false
    },
    {
        register: "UCB1I2COA",
        regForceSet: false
    },
    {
        register: "UCB1I2CSA",
        regForceSet: false
    },
    {
        register: "UCB1I2CIE",
        regForceSet: false
    },
    {
        register: "UC1IE",
        regForceSet: false
    }
];
 
 
config USCI_B1_I2C_2xx.name  // instance
index URL

Specific peripheral name given by the device

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.name = String undefined;
 
DETAILS
Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.
 
config USCI_B1_I2C_2xx.owner  // instance
index URL

String specifying the entity that manages the peripheral

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
  ...
params.owner = String undefined;
 
Instance Creation
index URL

XDCscript usage meta-domain
var params = new USCI_B1_I2C_2xx.Params;
// Allocate instance config-params
params.config =   ...
// Assign individual configs
 
var inst = USCI_B1_I2C_2xx.create(IClock.Instance clock, params);
// Create an instance-object
 
USCI_B1_I2C_2xx.getUCALIE()  // instance
index URL

Gets UCALIE bit

XDCscript usage meta-domain
inst.getUCALIE() returns Bool
 
SEE
getUCALIE
 
USCI_B1_I2C_2xx.getUCBxI2CSA()  // instance
index URL

Returns UCBxI2CSA register value based on which module

XDCscript usage meta-domain
inst.getUCBxI2CSA() returns Bits8
 
SEE
getUCBxI2CSA
 
USCI_B1_I2C_2xx.getUCNACKIE()  // instance
index URL

Gets UCNACKIE bit

XDCscript usage meta-domain
inst.getUCNACKIE() returns Bool
 
SEE
getUCNACKIE
 
USCI_B1_I2C_2xx.getUCSTPIE()  // instance
index URL

Gets UCSTPIE bit

XDCscript usage meta-domain
inst.getUCSTPIE() returns Bool
 
SEE
getUCSTPIE
 
USCI_B1_I2C_2xx.getUCSTTIE()  // instance
index URL

Gets UCSTTIE bit

XDCscript usage meta-domain
inst.getUCSTTIE() returns Bool
 
SEE
getUCSTTIE
 
USCI_B1_I2C_2xx.getUCxxBR0()  // instance
index URL

Returns UCxxBR0 register value based on which module

XDCscript usage meta-domain
inst.getUCxxBR0() returns Bits8
 
SEE
getUCxxBR0
 
USCI_B1_I2C_2xx.getUCxxBR1()  // instance
index URL

Returns UCxxBR1 register value based on which module

XDCscript usage meta-domain
inst.getUCxxBR1() returns Bits8
 
SEE
getUCxxBR1
 
USCI_B1_I2C_2xx.getUCxxRXIE()  // instance
index URL

Gets UCxxRXIE bit

XDCscript usage meta-domain
inst.getUCxxRXIE() returns Bool
 
SEE
getUCxxRXIE
 
USCI_B1_I2C_2xx.getUCxxTXIE()  // instance
index URL

Gets UCxxTXIE bit

XDCscript usage meta-domain
inst.getUCxxTXIE() returns Bool
 
SEE
getUCxxTXIE
 
USCI_B1_I2C_2xx.setUCALIE()  // instance
index URL

Sets UCALIE bit

XDCscript usage meta-domain
inst.setUCALIE(Bool set) returns Bool
 
SEE
setUCALIE
 
USCI_B1_I2C_2xx.setUCBxI2CSA()  // instance
index URL

Sets UCxxI2CSA register value based on which module

XDCscript usage meta-domain
inst.setUCBxI2CSA(Bits8 value) returns Void
 
SEE
setUCBxI2CSA
 
USCI_B1_I2C_2xx.setUCNACKIE()  // instance
index URL

Sets UCNACKIE bit

XDCscript usage meta-domain
inst.setUCNACKIE(Bool set) returns Bool
 
SEE
setUCNACKIE
 
USCI_B1_I2C_2xx.setUCSTPIE()  // instance
index URL

Sets UCSTPIE bit

XDCscript usage meta-domain
inst.setUCSTPIE(Bool set) returns Bool
 
SEE
setUCSTPIE
 
USCI_B1_I2C_2xx.setUCSTTIE()  // instance
index URL

Sets UCSTTIE bit

XDCscript usage meta-domain
inst.setUCSTTIE(Bool set) returns Bool
 
SEE
setUCSTTIE
 
USCI_B1_I2C_2xx.setUCxxBR0()  // instance
index URL

Sets UCxxBR0 register value based on which module

XDCscript usage meta-domain
inst.setUCxxBR0(Bits8 value) returns Void
 
SEE
setUCxxBR0
 
USCI_B1_I2C_2xx.setUCxxBR1()  // instance
index URL

Sets UCxxBR1 register value based on which module

XDCscript usage meta-domain
inst.setUCxxBR1(Bits8 value) returns Void
 
SEE
setUCxxBR1
 
USCI_B1_I2C_2xx.setUCxxRXIE()  // instance
index URL

Sets UCxxRXIE bit

XDCscript usage meta-domain
inst.setUCxxRXIE(Bool set) returns Bool
 
SEE
setUCxxRXIE
 
USCI_B1_I2C_2xx.setUCxxTXIE()  // instance
index URL

Sets UCxxTXIE bit

XDCscript usage meta-domain
inst.setUCxxTXIE(Bool set) returns Bool
 
SEE
setUCxxTXIE
generated on Wed, 20 Jul 2011 20:35:12 GMT