metaonly interface ti.catalog.msp430.peripherals.communication.IUSI
index URL

Universal Serial Interface

XDCspec summary sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
metaonly interface IUSI {  ...
// inherits xdc.platform.IPeripheral
instance:  ...
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
package ti.catalog.msp430.peripherals.communication;
 
metaonly interface IUSI inherits IPeripheral {
module-wide constants & types
    enum USI16B_t// 16-bit shift register enable {
        USI16B_OFF// 8-bit shift register mode. Low byte register USISRL is used,
        USI16B// 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously
    };
 
    enum USIAL_t// Arbitration lost {
        USIAL_OFF// No arbitration lost condition,
        USIAL// Arbitration lost
    };
 
    enum USICKPH_t// Clock phase select {
        USICKPH_OFF// Data is changed on the first SCLK edge and captured on the following edge,
        USICKPH// Data is captured on the first SCLK edge and changed on the following edge
    };
 
    enum USICKPL_t// Clock polarity select {
        USICKPL_OFF// Inactive state is low,
        USICKPL// Inactive state is high
    };
 
    enum USICNT0_t// USI bit count - Bit0 {
        USICNT0_OFF// USI bit count,
        USICNT0// USI bit count
    };
 
    enum USICNT1_t// USI bit count - Bit1 {
        USICNT1_OFF// USI bit count,
        USICNT1// USI bit count
    };
 
    enum USICNT2_t// USI bit count - Bit2 {
        USICNT2_OFF// USI bit count,
        USICNT2// USI bit count
    };
 
    enum USICNT3_t// USI bit count - Bit3 {
        USICNT3_OFF// USI bit count,
        USICNT3// USI bit count
    };
 
    enum USICNT4_t// USI bit count - Bit4 {
        USICNT4_OFF// USI bit count,
        USICNT4// USI bit count
    };
 
    enum USIDIV_t// Clock divider select {
        USIDIV_0// Divide by 1,
        USIDIV_1// Divide by 2,
        USIDIV_2// Divide by 4,
        USIDIV_3// Divide by 8,
        USIDIV_4// Divide by 16,
        USIDIV_5// Divide by 32,
        USIDIV_6// Divide by 64,
        USIDIV_7// Divide by 128
    };
 
    enum USIGE_t// Output latch control {
        USIGE_OFF// Output latch enable depends on shift clock,
        USIGE// Output latch always enabled and transparent
    };
 
    enum USII2C_t// I2C mode enable {
        USII2C_OFF// I2C mode disabled,
        USII2C// I2C mode enabled
    };
 
    enum USIIE_t// USI counter interrupt enable {
        USIIE_OFF// Interrupt disabled,
        USIIE// Interrupt enabled
    };
 
    enum USIIFGCC_t// USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0 {
        USIIFGCC_OFF// USIIFG automatically cleared on USICNTx update,
        USIIFGCC// USIIFG is not cleared automatically
    };
 
    enum USIIFG_t// USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0 {
        USIIFG_OFF// No interrupt pending,
        USIIFG// Interrupt pending
    };
 
    enum USILSB_t// LSB first select. This bit controls the direction of the receive and transmit shift register {
        USILSB_OFF// MSB first,
        USILSB// LSB first
    };
 
    enum USIMST_t// Master select {
        USIMST_OFF// Slave mode,
        USIMST// Master mode
    };
 
    enum USIOE_t// Data output enable {
        USIOE_OFF// Output disabled,
        USIOE// Output enabled
    };
 
    enum USIPE5_t// USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode {
        USIPE5_OFF// USI function disabled,
        USIPE5// USI function enabled
    };
 
    enum USIPE6_t// USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode {
        USIPE6_OFF// USI function disabled,
        USIPE6// USI function enabled
    };
 
    enum USIPE7_t// USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode {
        USIPE7_OFF// USI function disabled,
        USIPE7// USI function enabled
    };
 
    enum USISCLREL_t// SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected {
        USISCLREL_OFF// SCL line is held low if USIIFG is set,
        USISCLREL// SCL line is released
    };
 
    enum USISSEL_t// Clock source select. Not used in slave mode {
        USISSEL_0// SCLK (Not used in SPI mode),
        USISSEL_1// ACLK,
        USISSEL_2// SMCLK,
        USISSEL_3// SMCLK,
        USISSEL_4// USISWCLK bit,
        USISSEL_5// TACCR0,
        USISSEL_6// TACCR1,
        USISSEL_7// TACCR2 (Reserved on MSP430F20xx devices)
    };
 
    enum USISTP_t// STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0 {
        USISTP_OFF// No STOP condition received,
        USISTP// STOP condition received
    };
 
    enum USISTTIE_t// START condition interrupt-enable {
        USISTTIE_OFF// Interrupt on START condition disabled,
        USISTTIE// Interrupt on START condition enabled
    };
 
    enum USISTTIFG_t// START condition interrupt flag {
        USISTTIFG_OFF// No START condition received. No interrupt pending,
        USISTTIFG// START condition received. Interrupt pending
    };
 
    enum USISWCLK_t// Software clock {
        USISWCLK_OFF// Input clock is low,
        USISWCLK// Input clock is high
    };
 
    enum USISWRST_t// USI software reset {
        USISWRST_OFF// USI released for operation,
        USISWRST// USI logic held in reset state
    };
 
    typedef IPeripheral.Instance IPeripheralArray// [];
    typedef String StringArray// [];
 
    metaonly struct ForceSetDefaultRegister_t// Force Set Default Register {
        String register;
        Bool regForceSet;
    };
 
    metaonly struct USICKCTL_t//  {
        IUSI.USIDIV_t USIDIV// Clock divider select 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128;
        IUSI.USISSEL_t USISSEL// Clock source select. Not used in slave mode. 000 SCLK (Not used in SPI mode) 001 ACLK 010 SMCLK 011 SMCLK 100 USISWCLK bit 101 TACCR0 110 TACCR1 111 TACCR2 (Reserved on MSP430F20xx devices);
        IUSI.USICKPL_t USICKPL// Clock polarity select 0 Inactive state is low 1 Inactive state is high;
        IUSI.USISWCLK_t USISWCLK// Software clock 0 Input clock is low 1 Input clock is high;
    };
 
    metaonly struct USICNT_t//  {
        IUSI.USISCLREL_t USISCLREL// SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected. 0 SCL line is held low if USIIFG is set 1 SCL line is released;
        IUSI.USI16B_t USI16B// 16-bit shift register enable 0 8-bit shift register mode. Low byte register USISRL is used. 1 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously;
        IUSI.USIIFGCC_t USIIFGCC// USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0. 0 USIIFG automatically cleared on USICNTx update 1 USIIFG is not cleared automatically;
        IUSI.USICNT4_t USICNT4// USI bit count bit 4 The USICNTx bits set the number of bits to be received or transmitted;
        IUSI.USICNT3_t USICNT3// USI bit count bit 3 The USICNTx bits set the number of bits to be received or transmitted;
        IUSI.USICNT2_t USICNT2// USI bit count bit 2 The USICNTx bits set the number of bits to be received or transmitted;
        IUSI.USICNT1_t USICNT1// USI bit count bit 1 The USICNTx bits set the number of bits to be received or transmitted;
        IUSI.USICNT0_t USICNT0// USI bit count bit 0 The USICNTx bits set the number of bits to be received or transmitted;
    };
 
    metaonly struct USICTL0_t//  {
        IUSI.USIPE7_t USIPE7// USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled;
        IUSI.USIPE6_t USIPE6// USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled;
        IUSI.USIPE5_t USIPE5// USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode. 0 USI function disabled 1 USI function enabled;
        IUSI.USILSB_t USILSB// LSB first select. This bit controls the direction of the receive and transmit shift register. 0 MSB first 1 LSB first;
        IUSI.USIMST_t USIMST// Master select 0 Slave mode 1 Master mode;
        IUSI.USIGE_t USIGE// Output latch control 0 Output latch enable depends on shift clock 1 Output latch always enabled and transparent;
        IUSI.USIOE_t USIOE// Data output enable 0 Output disabled 1 Output enabled;
        IUSI.USISWRST_t USISWRST// USI software reset 0 USI released for operation. 1 USI logic held in reset state;
    };
 
    metaonly struct USICTL1_t//  {
        IUSI.USICKPH_t USICKPH// Clock phase select 0 Data is changed on the first SCLK edge and captured on the following edge. 1 Data is captured on the first SCLK edge and changed on the following edge;
        IUSI.USII2C_t USII2C// I2C mode enable 0 I2C mode disabled 1 I2C mode enabled;
        IUSI.USISTTIE_t USISTTIE// START condition interrupt-enable 0 Interrupt on START condition disabled 1 Interrupt on START condition enabled;
        IUSI.USIIE_t USIIE// USI counter interrupt enable 0 Interrupt disabled 1 Interrupt enabled;
        IUSI.USIAL_t USIAL// Arbitration lost 0 No arbitration lost condition 1 Arbitration lost;
        IUSI.USISTP_t USISTP// STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No STOP condition received 1 STOP condition received;
        IUSI.USISTTIFG_t USISTTIFG// START condition interrupt flag 0 No START condition received. No interrupt pending. 1 START condition received. Interrupt pending;
        IUSI.USIIFG_t USIIFG// USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No interrupt pending 1 Interrupt pending;
    };
module-wide functions
    IPeripheral.IPeripheralArray getAll// Find all peripherals of a certain type();
    IPeripheral.StringArray getRegisters// Find all registers defined by the peripheral();
 
 
instance:
per-instance config parameters
    config String name// Specific peripheral name given by the device;
    config String owner// String specifying the entity that manages the peripheral;
per-instance functions
    Bool getUSIIE// Gets USIIE register();
    Bool getUSISTTIE// Gets USISTTIE register();
    Bool setUSIIE// Sets USIIE register(Bool set);
    Bool setUSISTTIE// Sets USISTTIE register(Bool set);
}
 
enum IUSI.USI16B_t
index URL

16-bit shift register enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USI16B_t {
    USI16B_OFF,
    // 8-bit shift register mode. Low byte register USISRL is used
    USI16B
    // 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously
};
 
 
enum IUSI.USIAL_t
index URL

Arbitration lost

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIAL_t {
    USIAL_OFF,
    // No arbitration lost condition
    USIAL
    // Arbitration lost
};
 
 
enum IUSI.USICKPH_t
index URL

Clock phase select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USICKPH_t {
    USICKPH_OFF,
    // Data is changed on the first SCLK edge and captured on the following edge
    USICKPH
    // Data is captured on the first SCLK edge and changed on the following edge
};
 
 
enum IUSI.USICKPL_t
index URL

Clock polarity select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USICKPL_t {
    USICKPL_OFF,
    // Inactive state is low
    USICKPL
    // Inactive state is high
};
 
 
enum IUSI.USICNT0_t
index URL

USI bit count - Bit0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USICNT0_t {
    USICNT0_OFF,
    // USI bit count
    USICNT0
    // USI bit count
};
 
 
enum IUSI.USICNT1_t
index URL

USI bit count - Bit1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USICNT1_t {
    USICNT1_OFF,
    // USI bit count
    USICNT1
    // USI bit count
};
 
 
enum IUSI.USICNT2_t
index URL

USI bit count - Bit2

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USICNT2_t {
    USICNT2_OFF,
    // USI bit count
    USICNT2
    // USI bit count
};
 
 
enum IUSI.USICNT3_t
index URL

USI bit count - Bit3

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USICNT3_t {
    USICNT3_OFF,
    // USI bit count
    USICNT3
    // USI bit count
};
 
 
enum IUSI.USICNT4_t
index URL

USI bit count - Bit4

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USICNT4_t {
    USICNT4_OFF,
    // USI bit count
    USICNT4
    // USI bit count
};
 
 
enum IUSI.USIDIV_t
index URL

Clock divider select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIDIV_t {
    USIDIV_0,
    // Divide by 1
    USIDIV_1,
    // Divide by 2
    USIDIV_2,
    // Divide by 4
    USIDIV_3,
    // Divide by 8
    USIDIV_4,
    // Divide by 16
    USIDIV_5,
    // Divide by 32
    USIDIV_6,
    // Divide by 64
    USIDIV_7
    // Divide by 128
};
 
 
enum IUSI.USIGE_t
index URL

Output latch control

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIGE_t {
    USIGE_OFF,
    // Output latch enable depends on shift clock
    USIGE
    // Output latch always enabled and transparent
};
 
 
enum IUSI.USII2C_t
index URL

I2C mode enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USII2C_t {
    USII2C_OFF,
    // I2C mode disabled
    USII2C
    // I2C mode enabled
};
 
 
enum IUSI.USIIE_t
index URL

USI counter interrupt enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIIE_t {
    USIIE_OFF,
    // Interrupt disabled
    USIIE
    // Interrupt enabled
};
 
 
enum IUSI.USIIFGCC_t
index URL

USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIIFGCC_t {
    USIIFGCC_OFF,
    // USIIFG automatically cleared on USICNTx update
    USIIFGCC
    // USIIFG is not cleared automatically
};
 
 
enum IUSI.USIIFG_t
index URL

USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIIFG_t {
    USIIFG_OFF,
    // No interrupt pending
    USIIFG
    // Interrupt pending
};
 
 
enum IUSI.USILSB_t
index URL

LSB first select. This bit controls the direction of the receive and transmit shift register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USILSB_t {
    USILSB_OFF,
    // MSB first
    USILSB
    // LSB first
};
 
 
enum IUSI.USIMST_t
index URL

Master select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIMST_t {
    USIMST_OFF,
    // Slave mode
    USIMST
    // Master mode
};
 
 
enum IUSI.USIOE_t
index URL

Data output enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIOE_t {
    USIOE_OFF,
    // Output disabled
    USIOE
    // Output enabled
};
 
 
enum IUSI.USIPE5_t
index URL

USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIPE5_t {
    USIPE5_OFF,
    // USI function disabled
    USIPE5
    // USI function enabled
};
 
 
enum IUSI.USIPE6_t
index URL

USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIPE6_t {
    USIPE6_OFF,
    // USI function disabled
    USIPE6
    // USI function enabled
};
 
 
enum IUSI.USIPE7_t
index URL

USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USIPE7_t {
    USIPE7_OFF,
    // USI function disabled
    USIPE7
    // USI function enabled
};
 
 
enum IUSI.USISCLREL_t
index URL

SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USISCLREL_t {
    USISCLREL_OFF,
    // SCL line is held low if USIIFG is set
    USISCLREL
    // SCL line is released
};
 
 
enum IUSI.USISSEL_t
index URL

Clock source select. Not used in slave mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USISSEL_t {
    USISSEL_0,
    // SCLK (Not used in SPI mode)
    USISSEL_1,
    // ACLK
    USISSEL_2,
    // SMCLK
    USISSEL_3,
    // SMCLK
    USISSEL_4,
    // USISWCLK bit
    USISSEL_5,
    // TACCR0
    USISSEL_6,
    // TACCR1
    USISSEL_7
    // TACCR2 (Reserved on MSP430F20xx devices)
};
 
 
enum IUSI.USISTP_t
index URL

STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USISTP_t {
    USISTP_OFF,
    // No STOP condition received
    USISTP
    // STOP condition received
};
 
 
enum IUSI.USISTTIE_t
index URL

START condition interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USISTTIE_t {
    USISTTIE_OFF,
    // Interrupt on START condition disabled
    USISTTIE
    // Interrupt on START condition enabled
};
 
 
enum IUSI.USISTTIFG_t
index URL

START condition interrupt flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USISTTIFG_t {
    USISTTIFG_OFF,
    // No START condition received. No interrupt pending
    USISTTIFG
    // START condition received. Interrupt pending
};
 
 
enum IUSI.USISWCLK_t
index URL

Software clock

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USISWCLK_t {
    USISWCLK_OFF,
    // Input clock is low
    USISWCLK
    // Input clock is high
};
 
 
enum IUSI.USISWRST_t
index URL

USI software reset

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
enum USISWRST_t {
    USISWRST_OFF,
    // USI released for operation
    USISWRST
    // USI logic held in reset state
};
 
 
typedef IUSI.IPeripheralArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
typedef IPeripheral.Instance IPeripheralArray[];
 
 
typedef IUSI.StringArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
typedef String StringArray[];
 
 
struct IUSI.ForceSetDefaultRegister_t
index URL

Force Set Default Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
metaonly struct ForceSetDefaultRegister_t {
    String register;
    Bool regForceSet;
};
 
DETAILS
Type to store if each register needs to be forced initialized even if the register is in default state.
SEE
ForceSetDefaultRegister_t
 
struct IUSI.USICKCTL_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
metaonly struct USICKCTL_t {
    IUSI.USIDIV_t USIDIV;
    // Clock divider select 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128
    IUSI.USISSEL_t USISSEL;
    // Clock source select. Not used in slave mode. 000 SCLK (Not used in SPI mode) 001 ACLK 010 SMCLK 011 SMCLK 100 USISWCLK bit 101 TACCR0 110 TACCR1 111 TACCR2 (Reserved on MSP430F20xx devices)
    IUSI.USICKPL_t USICKPL;
    // Clock polarity select 0 Inactive state is low 1 Inactive state is high
    IUSI.USISWCLK_t USISWCLK;
    // Software clock 0 Input clock is low 1 Input clock is high
};
 
 
struct IUSI.USICNT_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
metaonly struct USICNT_t {
    IUSI.USISCLREL_t USISCLREL;
    // SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected. 0 SCL line is held low if USIIFG is set 1 SCL line is released
    IUSI.USI16B_t USI16B;
    // 16-bit shift register enable 0 8-bit shift register mode. Low byte register USISRL is used. 1 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously
    IUSI.USIIFGCC_t USIIFGCC;
    // USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0. 0 USIIFG automatically cleared on USICNTx update 1 USIIFG is not cleared automatically
    IUSI.USICNT4_t USICNT4;
    // USI bit count bit 4 The USICNTx bits set the number of bits to be received or transmitted
    IUSI.USICNT3_t USICNT3;
    // USI bit count bit 3 The USICNTx bits set the number of bits to be received or transmitted
    IUSI.USICNT2_t USICNT2;
    // USI bit count bit 2 The USICNTx bits set the number of bits to be received or transmitted
    IUSI.USICNT1_t USICNT1;
    // USI bit count bit 1 The USICNTx bits set the number of bits to be received or transmitted
    IUSI.USICNT0_t USICNT0;
    // USI bit count bit 0 The USICNTx bits set the number of bits to be received or transmitted
};
 
 
struct IUSI.USICTL0_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
metaonly struct USICTL0_t {
    IUSI.USIPE7_t USIPE7;
    // USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled
    IUSI.USIPE6_t USIPE6;
    // USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled
    IUSI.USIPE5_t USIPE5;
    // USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode. 0 USI function disabled 1 USI function enabled
    IUSI.USILSB_t USILSB;
    // LSB first select. This bit controls the direction of the receive and transmit shift register. 0 MSB first 1 LSB first
    IUSI.USIMST_t USIMST;
    // Master select 0 Slave mode 1 Master mode
    IUSI.USIGE_t USIGE;
    // Output latch control 0 Output latch enable depends on shift clock 1 Output latch always enabled and transparent
    IUSI.USIOE_t USIOE;
    // Data output enable 0 Output disabled 1 Output enabled
    IUSI.USISWRST_t USISWRST;
    // USI software reset 0 USI released for operation. 1 USI logic held in reset state
};
 
 
struct IUSI.USICTL1_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
metaonly struct USICTL1_t {
    IUSI.USICKPH_t USICKPH;
    // Clock phase select 0 Data is changed on the first SCLK edge and captured on the following edge. 1 Data is captured on the first SCLK edge and changed on the following edge
    IUSI.USII2C_t USII2C;
    // I2C mode enable 0 I2C mode disabled 1 I2C mode enabled
    IUSI.USISTTIE_t USISTTIE;
    // START condition interrupt-enable 0 Interrupt on START condition disabled 1 Interrupt on START condition enabled
    IUSI.USIIE_t USIIE;
    // USI counter interrupt enable 0 Interrupt disabled 1 Interrupt enabled
    IUSI.USIAL_t USIAL;
    // Arbitration lost 0 No arbitration lost condition 1 Arbitration lost
    IUSI.USISTP_t USISTP;
    // STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No STOP condition received 1 STOP condition received
    IUSI.USISTTIFG_t USISTTIFG;
    // START condition interrupt flag 0 No START condition received. No interrupt pending. 1 START condition received. Interrupt pending
    IUSI.USIIFG_t USIIFG;
    // USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No interrupt pending 1 Interrupt pending
};
 
 
IUSI.getAll()  // module-wide
index URL

Find all peripherals of a certain type

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
IPeripheral.IPeripheralArray getAll();
 
DETAILS
The type of the peripherals returned is defined by the type of the caller.
RETURNS
Returns an array of IPeripheral instances
 
IUSI.getRegisters()  // module-wide
index URL

Find all registers defined by the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
IPeripheral.StringArray getRegisters();
 
RETURNS
Returns an array of register names
 
config IUSI.name  // instance
index URL

Specific peripheral name given by the device

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
config String name;
 
DETAILS
Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.
 
config IUSI.owner  // instance
index URL

String specifying the entity that manages the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
config String owner;
 
 
IUSI.getUSIIE()  // instance
index URL

Gets USIIE register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
Bool getUSIIE();
 
SEE
setUSIIE
 
IUSI.getUSISTTIE()  // instance
index URL

Gets USISTTIE register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
Bool getUSISTTIE();
 
SEE
getUSISTTIE
 
IUSI.setUSIIE()  // instance
index URL

Sets USIIE register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
Bool setUSIIE(Bool set);
 
SEE
setUSIIE
 
IUSI.setUSISTTIE()  // instance
index URL

Sets USISTTIE register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSI.xdc
Bool setUSISTTIE(Bool set);
 
SEE
setUSISTTIE
generated on Wed, 20 Jul 2011 20:35:11 GMT