metaonly interface ti.catalog.msp430.peripherals.communication.IUSCI_B0_I2C
index URL

Universal Serial Communication Interface B0 I2C 2xx

XDCspec summary sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
metaonly interface IUSCI_B0_I2C {  ...
// inherits ti.catalog.msp430.peripherals.communication.IUSCI_I2C
    // inherits ti.catalog.msp430.peripherals.communication.IUSCI
        // inherits xdc.platform.IPeripheral
instance:  ...
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
package ti.catalog.msp430.peripherals.communication;
 
metaonly interface IUSCI_B0_I2C inherits IUSCI_I2C {
module-wide constants & types
    enum UC7BIT_t// Character length. Selects 7-bit or 8-bit character length {
        UC7BIT_OFF// 8-bit,
        UC7BIT// 7-bit
    };
 
    enum UCA10_t// Own addressing mode select {
        UCA10_OFF// Own address is a 7-bit address,
        UCA10// Own address is a 10-bit address
    };
 
    enum UCADDR_t// Address received in address-bit multiprocessor mode {
        UCADDR_OFF// Received character is data,
        UCADDR// Received character is an address
    };
 
    enum UCALIFG_t// Arbitration lost interrupt flag {
        UCALIFG_OFF// No interrupt pending,
        UCALIFG// Interrupt pending
    };
 
    enum UCBBUSY_t// Bus busy {
        UCBBUSY_OFF// Bus inactive,
        UCBBUSY// Bus busy
    };
 
    enum UCBRKIE_t// Receive break character interrupt-enable {
        UCBRKIE_OFF// Received break characters do not set UCAxRXIFG,
        UCBRKIE// Received break characters set UCAxRXIFG
    };
 
    enum UCBRK_t// Break detect flag {
        UCBRK_OFF// No break condition,
        UCBRK// Break condition occurred
    };
 
    enum UCBUSY_t// USCI busy. This bit indicates if a transmit or receive operation is in progress {
        UCBUSY_OFF// USCI inactive,
        UCBUSY// USCI transmitting or receiving
    };
 
    enum UCDORM_t// Dormant. Puts USCI into sleep mode {
        UCDORM_OFF// Not dormant. All received characters will set UCAxRXIFG,
        UCDORM// Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
    };
 
    enum UCFE_t// Framing error flag {
        UCFE_OFF// 0 No error,
        UCFE// Character received with low stop bit
    };
 
    enum UCGCEN_t// General call response enable {
        UCGCEN_OFF// Do not respond to a general call,
        UCGCEN// Respond to a general call
    };
 
    enum UCGC_t// General call address received {
        UCGC_OFF// No general call address received,
        UCGC// General call address received
    };
 
    enum UCIDLE_t// Idle line detected in idle-line multiprocessor mode {
        UCIDLE_OFF// No idle line detected,
        UCIDLE// Idle line detected
    };
 
    enum UCLISTEN_t// Listen enable. The UCLISTEN bit selects loopback mode {
        UCLISTEN_OFF// Disabled,
        UCLISTEN// Enabled. UCAxTXD is internally fed back to the receiver
    };
 
    enum UCMM_t// Multi-master environment select {
        UCMM_OFF// Single master environment. There is no other master in the system. The address compare unit is disabled,
        UCMM// Multi master environment
    };
 
    enum UCMODE_SYNC_t// USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1 {
        UCMODE_0// 3-Pin SPI,
        UCMODE_1// 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1,
        UCMODE_2// 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0,
        UCMODE_3// I2C Mode
    };
 
    enum UCMSB_t// MSB first select. Controls the direction of the receive and transmit shift register {
        UCMSB_OFF// LSB first,
        UCMSB// MSB first
    };
 
    enum UCMST_t// Master mode select {
        UCMST_OFF// Slave mode,
        UCMST// Master mode
    };
 
    enum UCNACKIFG_t// Not-acknowledge received interrupt flag {
        UCNACKIFG_OFF// No interrupt pending,
        UCNACKIFG// Interrupt pending
    };
 
    enum UCOE_t// Overrun error flag {
        UCOE_OFF// No error,
        UCOE// Overrun error occurred
    };
 
    enum UCPE_t// Parity error flag. When UCPEN = 0, UCPE is read as 0 {
        UCPE_OFF// No error,
        UCPE// Character received with parity error
    };
 
    enum UCRXEIE_t// Receive erroneous-character interrupt-enable {
        UCRXEIE_OFF// Erroneous characters rejected and UCAxRXIFG is not set,
        UCRXEIE// Erroneous characters received will set UCAxRXIFG
    };
 
    enum UCRXERR_t// Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read {
        UCRXERR_OFF// No receive errors detected,
        UCRXERR// Receive error detected
    };
 
    enum UCSCLLOW_t// SCL low {
        UCSCLLOW_OFF// SCL is not held low,
        UCSCLLOW// SCL is held low
    };
 
    enum UCSLA10_t// Slave addressing mode select {
        UCSLA10_OFF// Address slave with 7-bit address,
        UCSLA10// Address slave with 10-bit address
    };
 
    enum UCSSEL_I2C_t// USCI clock source select. These bits select the BRCLK source clock {
        UCSSEL_0// UCLK,
        UCSSEL_1// ACLK,
        UCSSEL_2// SMCLK
    };
 
    enum UCSTPIFG_t// Stop condition interrupt flag {
        UCSTPIFG_OFF// No interrupt pending,
        UCSTPIFG// Interrupt pending
    };
 
    enum UCSTTIFG_t// Start condition interrupt flag {
        UCSTTIFG_OFF// No interrupt pending,
        UCSTTIFG// Interrupt pending
    };
 
    enum UCSWRST_t// Software reset enable {
        UCSWRST_OFF// Disabled. USCI reset released for operation,
        UCSWRST// Enabled. USCI logic held in reset state
    };
 
    enum UCSYNC_t// Synchronous mode enable {
        UCSYNC_OFF// Asynchronous mode,
        UCSYNC// Synchronous Mode
    };
 
    enum UCTR_t// Transmitter/Receiver {
        UCTR_OFF// Receiver,
        UCTR// Transmitter
    };
 
    enum UCTXADDR_t// Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode {
        UCTXADDR_OFF// Next frame transmitted is data,
        UCTXADDR// Next frame transmitted is an address
    };
 
    enum UCTXBRK_t// Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer {
        UCTXBRK_OFF// Next frame transmitted is not a break,
        UCTXBRK// Next frame transmitted is a break or a break/synch
    };
 
    enum UCTXNACK_t// Transmit a NACK {
        UCTXNACK_OFF// Acknowledge normally,
        UCTXNACK// Generate NACK
    };
 
    enum UCTXSTP_t// Transmit STOP condition in master mode {
        UCTXSTP_OFF// No STOP generated,
        UCTXSTP// Generate STOP
    };
 
    enum UCTXSTT_t// Transmit START condition in master mode {
        UCTXSTT_OFF// Do not generate START condition,
        UCTXSTT// Generate START condition
    };
 
    typedef IPeripheral.Instance IPeripheralArray// [];
    typedef String StringArray// [];
 
    metaonly struct ForceSetDefaultRegister_t// Force Set Default Register {
        String register;
        Bool regForceSet;
    };
 
    metaonly struct UCBxI2COA_t//  {
        IUSCI_I2C.UCGCEN_t UCGCEN// General call response enable 0 Do not respond to a general call 1 Respond to a general call;
        UChar I2COA// I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB;
    };
 
    metaonly struct UCxCTL0_t//  {
        IUSCI_I2C.UCA10_t UCA10// Own addressing mode select 0 Own address is a 7-bit address 1 Own address is a 10-bit address;
        IUSCI_I2C.UCSLA10_t UCSLA10// Slave addressing mode select 0 Address slave with 7-bit address 1 Address slave with 10-bit address;
        IUSCI_I2C.UCMM_t UCMM// Multi-master environment select 0 Single master environment. There is no other master in the system. The address compare unit is disabled. 1 Multi master environment;
        IUSCI_I2C.UCMST_t UCMST// Master mode select. When a master looses arbitration in a multi-master environment (UCMM = 1) the UCMST bit is automatically cleared and the module acts as slave. 0 Slave mode 1 Master mode;
        IUSCI_I2C.UCMODE_SYNC_t UCMODE// USCI Mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-pin SPI 01 4-pin SPI (master/slave enabled if STE = 1) 10 4-pin SPI (master/slave enabled if STE = 0) 11 I2C mode;
        IUSCI_I2C.UCSYNC_t UCSYNC// Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode;
    };
 
    metaonly struct UCxCTL1_t//  {
        IUSCI_I2C.UCSSEL_I2C_t UCSSEL// USCI clock source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK;
        IUSCI_I2C.UCTR_t UCTR// Transmitter/Receiver 0 Receiver 1 Transmitter;
        IUSCI_I2C.UCTXNACK_t UCTXNACK// Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted. 0 Acknowledge normally 1 Generate NACK;
        IUSCI_I2C.UCTXSTP_t UCTXSTP// Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode the STOP condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated. 0 No STOP generated 1 Generate STOP;
        IUSCI_I2C.UCTXSTT_t UCTXSTT// Transmit START condition in master mode. Ignored in slave mode. In master receiver mode a repeated START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and address information is transmitted. Ignored in slave mode. 0 Do not generate START condition 1 Generate START condition;
        IUSCI_I2C.UCSWRST_t UCSWRST// Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state;
    };
 
    metaonly struct UCxSTAT_t//  {
        IUSCI_I2C.UCSCLLOW_t UCSCLLOW// SCL low 0 SCL is not held low 1 SCL is held low;
        IUSCI_I2C.UCGC_t UCGC// General call address received. UCGC is automatically cleared when a START condition is received. 0 No general call address received 1 General call address received;
        IUSCI_I2C.UCBBUSY_t UCBBUSY// Bus busy 0 Bus inactive 1 Bus busy;
        IUSCI_I2C.UCNACKIFG_t UCNACKIFG// Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending;
        IUSCI_I2C.UCSTPIFG_t UCSTPIFG// Stop condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending;
        IUSCI_I2C.UCSTTIFG_t UCSTTIFG// Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received. 0 No interrupt pending 1 Interrupt pending;
        IUSCI_I2C.UCALIFG_t UCALIFG// Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending;
    };
module-wide functions
    IPeripheral.IPeripheralArray getAll// Find all peripherals of a certain type();
    IPeripheral.StringArray getRegisters// Find all registers defined by the peripheral();
 
 
instance:
per-instance config parameters
    config Bits8 UCB0BR0// Bit Rate Control Register 0 = 0;
    config Bits8 UCB0BR1// Bit Rate Control Register 1 = 0;
    config IUSCI_B0_I2C.UCxCTL0_t UCB0CTL0// Control Register 0 = {
        UCA10: IUSCI_I2C.UCA10_OFF,
        UCSLA10: IUSCI_I2C.UCSLA10_OFF,
        UCMM: IUSCI_I2C.UCMM_OFF,
        UCMST: IUSCI_I2C.UCMST_OFF,
        UCMODE: IUSCI.UCMODE_0,
        UCSYNC: IUSCI.UCSYNC
    };
    config IUSCI_B0_I2C.UCxCTL1_t UCB0CTL1// Control Register 1 = {
        UCSSEL: IUSCI_I2C.UCSSEL_0,
        UCTR: IUSCI_I2C.UCTR_OFF,
        UCTXNACK: IUSCI_I2C.UCTXNACK_OFF,
        UCTXSTP: IUSCI_I2C.UCTXSTP_OFF,
        UCTXSTT: IUSCI_I2C.UCTXSTT_OFF,
        UCSWRST: IUSCI.UCSWRST
    };
    config IUSCI_B0_I2C.UCBxI2COA_t UCB0I2COA// I2C Own Address Register = {
        UCGCEN: IUSCI_I2C.UCGCEN_OFF,
        I2COA: 0
    };
    config Bits8 UCB0I2CSA// I2C Slave Address Register = 0;
    config Bits8 UCB0RXBUF// Receive Buffer Register = 0;
    config IUSCI_B0_I2C.UCxSTAT_t UCB0STAT// Status Register = {
        UCSCLLOW: IUSCI_I2C.UCSCLLOW,
        UCGC: IUSCI_I2C.UCGC,
        UCBBUSY: IUSCI_I2C.UCBBUSY,
        UCNACKIFG: IUSCI_I2C.UCNACKIFG,
        UCSTPIFG: IUSCI_I2C.UCSTPIFG,
        UCSTTIFG: IUSCI_I2C.UCSTTIFG,
        UCALIFG: IUSCI_I2C.UCALIFG
    };
    config Bits8 UCB0TXBUF// Transmit Buffer Register = 0;
    config Float UCLKHz// Stores the UCLK external clock frequency in float = 1000000;
    config String name// Specific peripheral name given by the device;
    config String owner// String specifying the entity that manages the peripheral;
per-instance functions
    Bits8 getUCBxI2CSA// Returns UCBxI2CSA register value based on which module();
    Bits8 getUCxxBR0// Returns UCxxBR0 register value based on which module();
    Bits8 getUCxxBR1// Returns UCxxBR1 register value based on which module();
    Bool getUCxxRXIE// Gets UCxxRXIE bit();
    Bool getUCxxTXIE// Gets UCxxTXIE bit();
    Void setUCBxI2CSA// Sets UCxxI2CSA register value based on which module(Bits8 value);
    Void setUCxxBR0// Sets UCxxBR0 register value based on which module(Bits8 value);
    Void setUCxxBR1// Sets UCxxBR1 register value based on which module(Bits8 value);
    Bool setUCxxRXIE// Sets UCxxRXIE bit(Bool set);
    Bool setUCxxTXIE// Sets UCxxTXIE bit(Bool set);
}
 
enum IUSCI_B0_I2C.UC7BIT_t
index URL

Character length. Selects 7-bit or 8-bit character length

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UC7BIT_t {
    UC7BIT_OFF,
    // 8-bit
    UC7BIT
    // 7-bit
};
 
 
enum IUSCI_B0_I2C.UCA10_t
index URL

Own addressing mode select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCA10_t {
    UCA10_OFF,
    // Own address is a 7-bit address
    UCA10
    // Own address is a 10-bit address
};
 
 
enum IUSCI_B0_I2C.UCADDR_t
index URL

Address received in address-bit multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCADDR_t {
    UCADDR_OFF,
    // Received character is data
    UCADDR
    // Received character is an address
};
 
 
enum IUSCI_B0_I2C.UCALIFG_t
index URL

Arbitration lost interrupt flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCALIFG_t {
    UCALIFG_OFF,
    // No interrupt pending
    UCALIFG
    // Interrupt pending
};
 
 
enum IUSCI_B0_I2C.UCBBUSY_t
index URL

Bus busy

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCBBUSY_t {
    UCBBUSY_OFF,
    // Bus inactive
    UCBBUSY
    // Bus busy
};
 
 
enum IUSCI_B0_I2C.UCBRKIE_t
index URL

Receive break character interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCBRKIE_t {
    UCBRKIE_OFF,
    // Received break characters do not set UCAxRXIFG
    UCBRKIE
    // Received break characters set UCAxRXIFG
};
 
 
enum IUSCI_B0_I2C.UCBRK_t
index URL

Break detect flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCBRK_t {
    UCBRK_OFF,
    // No break condition
    UCBRK
    // Break condition occurred
};
 
 
enum IUSCI_B0_I2C.UCBUSY_t
index URL

USCI busy. This bit indicates if a transmit or receive operation is in progress

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCBUSY_t {
    UCBUSY_OFF,
    // USCI inactive
    UCBUSY
    // USCI transmitting or receiving
};
 
 
enum IUSCI_B0_I2C.UCDORM_t
index URL

Dormant. Puts USCI into sleep mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCDORM_t {
    UCDORM_OFF,
    // Not dormant. All received characters will set UCAxRXIFG
    UCDORM
    // Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG
};
 
 
enum IUSCI_B0_I2C.UCFE_t
index URL

Framing error flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCFE_t {
    UCFE_OFF,
    // 0 No error
    UCFE
    // Character received with low stop bit
};
 
 
enum IUSCI_B0_I2C.UCGCEN_t
index URL

General call response enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCGCEN_t {
    UCGCEN_OFF,
    // Do not respond to a general call
    UCGCEN
    // Respond to a general call
};
 
 
enum IUSCI_B0_I2C.UCGC_t
index URL

General call address received

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCGC_t {
    UCGC_OFF,
    // No general call address received
    UCGC
    // General call address received
};
 
 
enum IUSCI_B0_I2C.UCIDLE_t
index URL

Idle line detected in idle-line multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCIDLE_t {
    UCIDLE_OFF,
    // No idle line detected
    UCIDLE
    // Idle line detected
};
 
 
enum IUSCI_B0_I2C.UCLISTEN_t
index URL

Listen enable. The UCLISTEN bit selects loopback mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCLISTEN_t {
    UCLISTEN_OFF,
    // Disabled
    UCLISTEN
    // Enabled. UCAxTXD is internally fed back to the receiver
};
 
 
enum IUSCI_B0_I2C.UCMM_t
index URL

Multi-master environment select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCMM_t {
    UCMM_OFF,
    // Single master environment. There is no other master in the system. The address compare unit is disabled
    UCMM
    // Multi master environment
};
 
 
enum IUSCI_B0_I2C.UCMODE_SYNC_t
index URL

USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCMODE_SYNC_t {
    UCMODE_0,
    // 3-Pin SPI
    UCMODE_1,
    // 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1
    UCMODE_2,
    // 4-Pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0
    UCMODE_3
    // I2C Mode
};
 
 
enum IUSCI_B0_I2C.UCMSB_t
index URL

MSB first select. Controls the direction of the receive and transmit shift register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCMSB_t {
    UCMSB_OFF,
    // LSB first
    UCMSB
    // MSB first
};
 
 
enum IUSCI_B0_I2C.UCMST_t
index URL

Master mode select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCMST_t {
    UCMST_OFF,
    // Slave mode
    UCMST
    // Master mode
};
 
 
enum IUSCI_B0_I2C.UCNACKIFG_t
index URL

Not-acknowledge received interrupt flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCNACKIFG_t {
    UCNACKIFG_OFF,
    // No interrupt pending
    UCNACKIFG
    // Interrupt pending
};
 
 
enum IUSCI_B0_I2C.UCOE_t
index URL

Overrun error flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCOE_t {
    UCOE_OFF,
    // No error
    UCOE
    // Overrun error occurred
};
 
 
enum IUSCI_B0_I2C.UCPE_t
index URL

Parity error flag. When UCPEN = 0, UCPE is read as 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCPE_t {
    UCPE_OFF,
    // No error
    UCPE
    // Character received with parity error
};
 
 
enum IUSCI_B0_I2C.UCRXEIE_t
index URL

Receive erroneous-character interrupt-enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCRXEIE_t {
    UCRXEIE_OFF,
    // Erroneous characters rejected and UCAxRXIFG is not set
    UCRXEIE
    // Erroneous characters received will set UCAxRXIFG
};
 
 
enum IUSCI_B0_I2C.UCRXERR_t
index URL

Bit 2 Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCRXERR_t {
    UCRXERR_OFF,
    // No receive errors detected
    UCRXERR
    // Receive error detected
};
 
 
enum IUSCI_B0_I2C.UCSCLLOW_t
index URL

SCL low

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCSCLLOW_t {
    UCSCLLOW_OFF,
    // SCL is not held low
    UCSCLLOW
    // SCL is held low
};
 
 
enum IUSCI_B0_I2C.UCSLA10_t
index URL

Slave addressing mode select

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCSLA10_t {
    UCSLA10_OFF,
    // Address slave with 7-bit address
    UCSLA10
    // Address slave with 10-bit address
};
 
 
enum IUSCI_B0_I2C.UCSSEL_I2C_t
index URL

USCI clock source select. These bits select the BRCLK source clock

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCSSEL_I2C_t {
    UCSSEL_0,
    // UCLK
    UCSSEL_1,
    // ACLK
    UCSSEL_2
    // SMCLK
};
 
 
enum IUSCI_B0_I2C.UCSTPIFG_t
index URL

Stop condition interrupt flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCSTPIFG_t {
    UCSTPIFG_OFF,
    // No interrupt pending
    UCSTPIFG
    // Interrupt pending
};
 
 
enum IUSCI_B0_I2C.UCSTTIFG_t
index URL

Start condition interrupt flag

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCSTTIFG_t {
    UCSTTIFG_OFF,
    // No interrupt pending
    UCSTTIFG
    // Interrupt pending
};
 
 
enum IUSCI_B0_I2C.UCSWRST_t
index URL

Software reset enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCSWRST_t {
    UCSWRST_OFF,
    // Disabled. USCI reset released for operation
    UCSWRST
    // Enabled. USCI logic held in reset state
};
 
 
enum IUSCI_B0_I2C.UCSYNC_t
index URL

Synchronous mode enable

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCSYNC_t {
    UCSYNC_OFF,
    // Asynchronous mode
    UCSYNC
    // Synchronous Mode
};
 
 
enum IUSCI_B0_I2C.UCTR_t
index URL

Transmitter/Receiver

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCTR_t {
    UCTR_OFF,
    // Receiver
    UCTR
    // Transmitter
};
 
 
enum IUSCI_B0_I2C.UCTXADDR_t
index URL

Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCTXADDR_t {
    UCTXADDR_OFF,
    // Next frame transmitted is data
    UCTXADDR
    // Next frame transmitted is an address
};
 
 
enum IUSCI_B0_I2C.UCTXBRK_t
index URL

Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCTXBRK_t {
    UCTXBRK_OFF,
    // Next frame transmitted is not a break
    UCTXBRK
    // Next frame transmitted is a break or a break/synch
};
 
 
enum IUSCI_B0_I2C.UCTXNACK_t
index URL

Transmit a NACK

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCTXNACK_t {
    UCTXNACK_OFF,
    // Acknowledge normally
    UCTXNACK
    // Generate NACK
};
 
 
enum IUSCI_B0_I2C.UCTXSTP_t
index URL

Transmit STOP condition in master mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCTXSTP_t {
    UCTXSTP_OFF,
    // No STOP generated
    UCTXSTP
    // Generate STOP
};
 
 
enum IUSCI_B0_I2C.UCTXSTT_t
index URL

Transmit START condition in master mode

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
enum UCTXSTT_t {
    UCTXSTT_OFF,
    // Do not generate START condition
    UCTXSTT
    // Generate START condition
};
 
 
typedef IUSCI_B0_I2C.IPeripheralArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
typedef IPeripheral.Instance IPeripheralArray[];
 
 
typedef IUSCI_B0_I2C.StringArray
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
typedef String StringArray[];
 
 
struct IUSCI_B0_I2C.ForceSetDefaultRegister_t
index URL

Force Set Default Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
metaonly struct ForceSetDefaultRegister_t {
    String register;
    Bool regForceSet;
};
 
DETAILS
Type to store if each register needs to be forced initialized even if the register is in default state.
SEE
ForceSetDefaultRegister_t
 
struct IUSCI_B0_I2C.UCBxI2COA_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
metaonly struct UCBxI2COA_t {
    IUSCI_I2C.UCGCEN_t UCGCEN;
    // General call response enable 0 Do not respond to a general call 1 Respond to a general call
    UChar I2COA;
    // I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller. The address is right-justified. In 7-bit addressing mode Bit 6 is the MSB, Bits 9-7 are ignored. In 10-bit addressing mode Bit 9 is the MSB
};
 
 
struct IUSCI_B0_I2C.UCxCTL0_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
metaonly struct UCxCTL0_t {
    IUSCI_I2C.UCA10_t UCA10;
    // Own addressing mode select 0 Own address is a 7-bit address 1 Own address is a 10-bit address
    IUSCI_I2C.UCSLA10_t UCSLA10;
    // Slave addressing mode select 0 Address slave with 7-bit address 1 Address slave with 10-bit address
    IUSCI_I2C.UCMM_t UCMM;
    // Multi-master environment select 0 Single master environment. There is no other master in the system. The address compare unit is disabled. 1 Multi master environment
    IUSCI_I2C.UCMST_t UCMST;
    // Master mode select. When a master looses arbitration in a multi-master environment (UCMM = 1) the UCMST bit is automatically cleared and the module acts as slave. 0 Slave mode 1 Master mode
    IUSCI_I2C.UCMODE_SYNC_t UCMODE;
    // USCI Mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-pin SPI 01 4-pin SPI (master/slave enabled if STE = 1) 10 4-pin SPI (master/slave enabled if STE = 0) 11 I2C mode
    IUSCI_I2C.UCSYNC_t UCSYNC;
    // Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode
};
 
 
struct IUSCI_B0_I2C.UCxCTL1_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
metaonly struct UCxCTL1_t {
    IUSCI_I2C.UCSSEL_I2C_t UCSSEL;
    // USCI clock source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK
    IUSCI_I2C.UCTR_t UCTR;
    // Transmitter/Receiver 0 Receiver 1 Transmitter
    IUSCI_I2C.UCTXNACK_t UCTXNACK;
    // Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted. 0 Acknowledge normally 1 Generate NACK
    IUSCI_I2C.UCTXSTP_t UCTXSTP;
    // Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode the STOP condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated. 0 No STOP generated 1 Generate STOP
    IUSCI_I2C.UCTXSTT_t UCTXSTT;
    // Transmit START condition in master mode. Ignored in slave mode. In master receiver mode a repeated START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and address information is transmitted. Ignored in slave mode. 0 Do not generate START condition 1 Generate START condition
    IUSCI_I2C.UCSWRST_t UCSWRST;
    // Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state
};
 
 
struct IUSCI_B0_I2C.UCxSTAT_t
index URL
XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
metaonly struct UCxSTAT_t {
    IUSCI_I2C.UCSCLLOW_t UCSCLLOW;
    // SCL low 0 SCL is not held low 1 SCL is held low
    IUSCI_I2C.UCGC_t UCGC;
    // General call address received. UCGC is automatically cleared when a START condition is received. 0 No general call address received 1 General call address received
    IUSCI_I2C.UCBBUSY_t UCBBUSY;
    // Bus busy 0 Bus inactive 1 Bus busy
    IUSCI_I2C.UCNACKIFG_t UCNACKIFG;
    // Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending
    IUSCI_I2C.UCSTPIFG_t UCSTPIFG;
    // Stop condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending
    IUSCI_I2C.UCSTTIFG_t UCSTTIFG;
    // Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received. 0 No interrupt pending 1 Interrupt pending
    IUSCI_I2C.UCALIFG_t UCALIFG;
    // Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending
};
 
 
IUSCI_B0_I2C.getAll()  // module-wide
index URL

Find all peripherals of a certain type

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
IPeripheral.IPeripheralArray getAll();
 
DETAILS
The type of the peripherals returned is defined by the type of the caller.
RETURNS
Returns an array of IPeripheral instances
 
IUSCI_B0_I2C.getRegisters()  // module-wide
index URL

Find all registers defined by the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
IPeripheral.StringArray getRegisters();
 
RETURNS
Returns an array of register names
 
config IUSCI_B0_I2C.UCB0BR0  // instance
index URL

Bit Rate Control Register 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config Bits8 UCB0BR0 = 0;
 
 
config IUSCI_B0_I2C.UCB0BR1  // instance
index URL

Bit Rate Control Register 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config Bits8 UCB0BR1 = 0;
 
 
config IUSCI_B0_I2C.UCB0CTL0  // instance
index URL

Control Register 0

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config IUSCI_B0_I2C.UCxCTL0_t UCB0CTL0 = {
    UCA10: IUSCI_I2C.UCA10_OFF,
    UCSLA10: IUSCI_I2C.UCSLA10_OFF,
    UCMM: IUSCI_I2C.UCMM_OFF,
    UCMST: IUSCI_I2C.UCMST_OFF,
    UCMODE: IUSCI.UCMODE_0,
    UCSYNC: IUSCI.UCSYNC
};
 
 
config IUSCI_B0_I2C.UCB0CTL1  // instance
index URL

Control Register 1

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config IUSCI_B0_I2C.UCxCTL1_t UCB0CTL1 = {
    UCSSEL: IUSCI_I2C.UCSSEL_0,
    UCTR: IUSCI_I2C.UCTR_OFF,
    UCTXNACK: IUSCI_I2C.UCTXNACK_OFF,
    UCTXSTP: IUSCI_I2C.UCTXSTP_OFF,
    UCTXSTT: IUSCI_I2C.UCTXSTT_OFF,
    UCSWRST: IUSCI.UCSWRST
};
 
 
config IUSCI_B0_I2C.UCB0I2COA  // instance
index URL

I2C Own Address Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config IUSCI_B0_I2C.UCBxI2COA_t UCB0I2COA = {
    UCGCEN: IUSCI_I2C.UCGCEN_OFF,
    I2COA: 0
};
 
 
config IUSCI_B0_I2C.UCB0I2CSA  // instance
index URL

I2C Slave Address Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config Bits8 UCB0I2CSA = 0;
 
 
config IUSCI_B0_I2C.UCB0RXBUF  // instance
index URL

Receive Buffer Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config Bits8 UCB0RXBUF = 0;
 
 
config IUSCI_B0_I2C.UCB0STAT  // instance
index URL

Status Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config IUSCI_B0_I2C.UCxSTAT_t UCB0STAT = {
    UCSCLLOW: IUSCI_I2C.UCSCLLOW,
    UCGC: IUSCI_I2C.UCGC,
    UCBBUSY: IUSCI_I2C.UCBBUSY,
    UCNACKIFG: IUSCI_I2C.UCNACKIFG,
    UCSTPIFG: IUSCI_I2C.UCSTPIFG,
    UCSTTIFG: IUSCI_I2C.UCSTTIFG,
    UCALIFG: IUSCI_I2C.UCALIFG
};
 
 
config IUSCI_B0_I2C.UCB0TXBUF  // instance
index URL

Transmit Buffer Register

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config Bits8 UCB0TXBUF = 0;
 
 
config IUSCI_B0_I2C.UCLKHz  // instance
index URL

Stores the UCLK external clock frequency in float

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config Float UCLKHz = 1000000;
 
 
config IUSCI_B0_I2C.name  // instance
index URL

Specific peripheral name given by the device

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config String name;
 
DETAILS
Devices can have more than one peripheral of the same type. In such cases, device data sheets give different names to the instances of a same peripheral. For example, the name for a timer module could be TimerA3, and a device that has two such timers can name them TA0 and TA1.
 
config IUSCI_B0_I2C.owner  // instance
index URL

String specifying the entity that manages the peripheral

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
config String owner;
 
 
IUSCI_B0_I2C.getUCBxI2CSA()  // instance
index URL

Returns UCBxI2CSA register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Bits8 getUCBxI2CSA();
 
SEE
getUCBxI2CSA
 
IUSCI_B0_I2C.getUCxxBR0()  // instance
index URL

Returns UCxxBR0 register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Bits8 getUCxxBR0();
 
SEE
getUCxxBR0
 
IUSCI_B0_I2C.getUCxxBR1()  // instance
index URL

Returns UCxxBR1 register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Bits8 getUCxxBR1();
 
SEE
getUCxxBR1
 
IUSCI_B0_I2C.getUCxxRXIE()  // instance
index URL

Gets UCxxRXIE bit

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Bool getUCxxRXIE();
 
SEE
getUCxxRXIE
 
IUSCI_B0_I2C.getUCxxTXIE()  // instance
index URL

Gets UCxxTXIE bit

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Bool getUCxxTXIE();
 
SEE
getUCxxTXIE
 
IUSCI_B0_I2C.setUCBxI2CSA()  // instance
index URL

Sets UCxxI2CSA register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Void setUCBxI2CSA(Bits8 value);
 
SEE
setUCBxI2CSA
 
IUSCI_B0_I2C.setUCxxBR0()  // instance
index URL

Sets UCxxBR0 register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Void setUCxxBR0(Bits8 value);
 
SEE
setUCxxBR0
 
IUSCI_B0_I2C.setUCxxBR1()  // instance
index URL

Sets UCxxBR1 register value based on which module

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Void setUCxxBR1(Bits8 value);
 
SEE
setUCxxBR1
 
IUSCI_B0_I2C.setUCxxRXIE()  // instance
index URL

Sets UCxxRXIE bit

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Bool setUCxxRXIE(Bool set);
 
SEE
setUCxxRXIE
 
IUSCI_B0_I2C.setUCxxTXIE()  // instance
index URL

Sets UCxxTXIE bit

XDCspec declarations sourced in ti/catalog/msp430/peripherals/communication/IUSCI_B0_I2C.xdc
Bool setUCxxTXIE(Bool set);
 
SEE
setUCxxTXIE
generated on Thu, 16 Jun 2011 22:54:47 GMT