enum IUSI.USI16B_t |
![](../../../../../Arrow_up.png) |
16-bit shift register enable
enum USI16B_t {
USI16B_OFF,
// 8-bit shift register mode. Low byte register USISRL is used
USI16B
// 16-bit shift register mode. Both high and low byte registers USISRL
and USISRH are used. USISR addresses all 16 bits simultaneously
};
enum IUSI.USIAL_t |
![](../../../../../Arrow_up.png) |
Arbitration lost
enum USIAL_t {
USIAL_OFF,
// No arbitration lost condition
USIAL
// Arbitration lost
};
enum IUSI.USICKPH_t |
![](../../../../../Arrow_up.png) |
Clock phase select
enum USICKPH_t {
USICKPH_OFF,
// Data is changed on the first SCLK edge and captured on the following edge
USICKPH
// Data is captured on the first SCLK edge and changed on the following edge
};
enum IUSI.USICKPL_t |
![](../../../../../Arrow_up.png) |
Clock polarity select
enum USICKPL_t {
USICKPL_OFF,
// Inactive state is low
USICKPL
// Inactive state is high
};
enum IUSI.USICNT0_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit0
enum USICNT0_t {
USICNT0_OFF,
// USI bit count
USICNT0
// USI bit count
};
enum IUSI.USICNT1_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit1
enum USICNT1_t {
USICNT1_OFF,
// USI bit count
USICNT1
// USI bit count
};
enum IUSI.USICNT2_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit2
enum USICNT2_t {
USICNT2_OFF,
// USI bit count
USICNT2
// USI bit count
};
enum IUSI.USICNT3_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit3
enum USICNT3_t {
USICNT3_OFF,
// USI bit count
USICNT3
// USI bit count
};
enum IUSI.USICNT4_t |
![](../../../../../Arrow_up.png) |
USI bit count - Bit4
enum USICNT4_t {
USICNT4_OFF,
// USI bit count
USICNT4
// USI bit count
};
enum IUSI.USIDIV_t |
![](../../../../../Arrow_up.png) |
Clock divider select
enum USIDIV_t {
USIDIV_0,
// Divide by 1
USIDIV_1,
// Divide by 2
USIDIV_2,
// Divide by 4
USIDIV_3,
// Divide by 8
USIDIV_4,
// Divide by 16
USIDIV_5,
// Divide by 32
USIDIV_6,
// Divide by 64
USIDIV_7
// Divide by 128
};
enum IUSI.USIGE_t |
![](../../../../../Arrow_up.png) |
Output latch control
enum USIGE_t {
USIGE_OFF,
// Output latch enable depends on shift clock
USIGE
// Output latch always enabled and transparent
};
enum IUSI.USII2C_t |
![](../../../../../Arrow_up.png) |
I2C mode enable
enum USII2C_t {
USII2C_OFF,
// I2C mode disabled
USII2C
// I2C mode enabled
};
enum IUSI.USIIE_t |
![](../../../../../Arrow_up.png) |
USI counter interrupt enable
enum USIIE_t {
USIIE_OFF,
// Interrupt disabled
USIIE
// Interrupt enabled
};
enum IUSI.USIIFGCC_t |
![](../../../../../Arrow_up.png) |
USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be
cleared automatically when USICNTx is written with a value > 0
enum USIIFGCC_t {
USIIFGCC_OFF,
// USIIFG automatically cleared on USICNTx update
USIIFGCC
// USIIFG is not cleared automatically
};
enum IUSI.USIIFG_t |
![](../../../../../Arrow_up.png) |
USI counter interrupt flag. Set when the USICNTx = 0. Automatically
cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0
enum USIIFG_t {
USIIFG_OFF,
// No interrupt pending
USIIFG
// Interrupt pending
};
enum IUSI.USILSB_t |
![](../../../../../Arrow_up.png) |
LSB first select. This bit controls the direction of the receive and transmit shift register
enum USILSB_t {
USILSB_OFF,
// MSB first
USILSB
// LSB first
};
enum IUSI.USIMST_t |
![](../../../../../Arrow_up.png) |
Master select
enum USIMST_t {
USIMST_OFF,
// Slave mode
USIMST
// Master mode
};
enum IUSI.USIOE_t |
![](../../../../../Arrow_up.png) |
Data output enable
enum USIOE_t {
USIOE_OFF,
// Output disabled
USIOE
// Output enabled
};
enum IUSI.USIPE5_t |
![](../../../../../Arrow_up.png) |
USI SCLK port enable.
Input in SPI slave mode, or I2C mode, output in SPI master mode
enum USIPE5_t {
USIPE5_OFF,
// USI function disabled
USIPE5
// USI function enabled
};
enum IUSI.USIPE6_t |
![](../../../../../Arrow_up.png) |
USI SDO/SCL port enable.
Output in SPI mode, input or open drain output in I2C mode
enum USIPE6_t {
USIPE6_OFF,
// USI function disabled
USIPE6
// USI function enabled
};
enum IUSI.USIPE7_t |
![](../../../../../Arrow_up.png) |
USI SDI/SDA port enable.
Input in SPI mode, input or open drain output in I2C mode
enum USIPE7_t {
USIPE7_OFF,
// USI function disabled
USIPE7
// USI function enabled
};
enum IUSI.USISCLREL_t |
![](../../../../../Arrow_up.png) |
SCL release. The SCL line is released from low to idle. USISCLREL is
cleared if a START condition is detected
enum USISCLREL_t {
USISCLREL_OFF,
// SCL line is held low if USIIFG is set
USISCLREL
// SCL line is released
};
enum IUSI.USISSEL_t |
![](../../../../../Arrow_up.png) |
Clock source select. Not used in slave mode
enum USISSEL_t {
USISSEL_0,
// SCLK (Not used in SPI mode)
USISSEL_1,
// ACLK
USISSEL_2,
// SMCLK
USISSEL_3,
// SMCLK
USISSEL_4,
// USISWCLK bit
USISSEL_5,
// TACCR0
USISSEL_6,
// TACCR1
USISSEL_7
// TACCR2 (Reserved on MSP430F20xx devices)
};
enum IUSI.USISTP_t |
![](../../../../../Arrow_up.png) |
STOP condition received. USISTP is automatically cleared if USICNTx is
loaded with a value > 0 when USIIFGCC = 0
enum USISTP_t {
USISTP_OFF,
// No STOP condition received
USISTP
// STOP condition received
};
enum IUSI.USISTTIE_t |
![](../../../../../Arrow_up.png) |
START condition interrupt-enable
enum USISTTIE_t {
USISTTIE_OFF,
// Interrupt on START condition disabled
USISTTIE
// Interrupt on START condition enabled
};
enum IUSI.USISTTIFG_t |
![](../../../../../Arrow_up.png) |
START condition interrupt flag
enum USISTTIFG_t {
USISTTIFG_OFF,
// No START condition received. No interrupt pending
USISTTIFG
// START condition received. Interrupt pending
};
enum IUSI.USISWCLK_t |
![](../../../../../Arrow_up.png) |
Software clock
enum USISWCLK_t {
USISWCLK_OFF,
// Input clock is low
USISWCLK
// Input clock is high
};
enum IUSI.USISWRST_t |
![](../../../../../Arrow_up.png) |
USI software reset
enum USISWRST_t {
USISWRST_OFF,
// USI released for operation
USISWRST
// USI logic held in reset state
};
typedef IUSI.IPeripheralArray |
![](../../../../../Arrow_up.png) |
typedef IUSI.StringArray |
![](../../../../../Arrow_up.png) |
typedef String StringArray[];
struct IUSI.ForceSetDefaultRegister_t |
![](../../../../../Arrow_up.png) |
Force Set Default Register
metaonly struct ForceSetDefaultRegister_t {
String register;
Bool regForceSet;
};
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct IUSI.USICKCTL_t |
![](../../../../../Arrow_up.png) |
metaonly struct USICKCTL_t {
// Clock divider select
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
// Clock source select. Not used in slave mode.
000 SCLK (Not used in SPI mode)
001 ACLK
010 SMCLK
011 SMCLK
100 USISWCLK bit
101 TACCR0
110 TACCR1
111 TACCR2 (Reserved on MSP430F20xx devices)
// Clock polarity select
0 Inactive state is low
1 Inactive state is high
// Software clock
0 Input clock is low
1 Input clock is high
};
struct IUSI.USICNT_t |
![](../../../../../Arrow_up.png) |
metaonly struct USICNT_t {
// SCL release. The SCL line is released from low to idle. USISCLREL is
cleared if a START condition is detected.
0 SCL line is held low if USIIFG is set
1 SCL line is released
// 16-bit shift register enable
0 8-bit shift register mode. Low byte register USISRL is used.
1 16-bit shift register mode. Both high and low byte registers USISRL
and USISRH are used. USISR addresses all 16 bits simultaneously
// USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be
cleared automatically when USICNTx is written with a value > 0.
0 USIIFG automatically cleared on USICNTx update
1 USIIFG is not cleared automatically
// USI bit count bit 4
The USICNTx bits set the number of bits to be received or transmitted
// USI bit count bit 3
The USICNTx bits set the number of bits to be received or transmitted
// USI bit count bit 2
The USICNTx bits set the number of bits to be received or transmitted
// USI bit count bit 1
The USICNTx bits set the number of bits to be received or transmitted
// USI bit count bit 0
The USICNTx bits set the number of bits to be received or transmitted
};
struct IUSI.USICTL0_t |
![](../../../../../Arrow_up.png) |
metaonly struct USICTL0_t {
// USI SDI/SDA port enable.
Input in SPI mode, input or open drain output in I2C mode.
0 USI function disabled
1 USI function enabled
// USI SDO/SCL port enable.
Output in SPI mode, input or open drain output in I2C mode.
0 USI function disabled
1 USI function enabled
// USI SCLK port enable.
Input in SPI slave mode, or I2C mode, output in SPI master mode.
0 USI function disabled
1 USI function enabled
// LSB first select. This bit controls the direction of the receive and transmit shift register.
0 MSB first
1 LSB first
// Master select
0 Slave mode
1 Master mode
// Output latch control
0 Output latch enable depends on shift clock
1 Output latch always enabled and transparent
// Data output enable
0 Output disabled
1 Output enabled
// USI software reset
0 USI released for operation.
1 USI logic held in reset state
};
struct IUSI.USICTL1_t |
![](../../../../../Arrow_up.png) |
metaonly struct USICTL1_t {
// Clock phase select
0 Data is changed on the first SCLK edge and captured on the
following edge.
1 Data is captured on the first SCLK edge and changed on the
following edge
// I2C mode enable
0 I2C mode disabled
1 I2C mode enabled
// START condition interrupt-enable
0 Interrupt on START condition disabled
1 Interrupt on START condition enabled
// USI counter interrupt enable
0 Interrupt disabled
1 Interrupt enabled
// Arbitration lost
0 No arbitration lost condition
1 Arbitration lost
// STOP condition received. USISTP is automatically cleared if USICNTx is
loaded with a value > 0 when USIIFGCC = 0.
0 No STOP condition received
1 STOP condition received
// START condition interrupt flag
0 No START condition received. No interrupt pending.
1 START condition received. Interrupt pending
// USI counter interrupt flag. Set when the USICNTx = 0. Automatically
cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0.
0 No interrupt pending
1 Interrupt pending
};
IUSI.getAll() // module-wide |
![](../../../../../Arrow_up.png) |
Find all peripherals of a certain type
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
IUSI.getRegisters() // module-wide |
![](../../../../../Arrow_up.png) |
Find all registers defined by the peripheral
RETURNS
Returns an array of register names
config IUSI.name // instance |
![](../../../../../Arrow_up.png) |
Specific peripheral name given by the device
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config IUSI.owner // instance |
![](../../../../../Arrow_up.png) |
String specifying the entity that manages the peripheral
IUSI.getUSIIE() // instance |
![](../../../../../Arrow_up.png) |
Gets USIIE register
SEE
IUSI.getUSISTTIE() // instance |
![](../../../../../Arrow_up.png) |
Gets USISTTIE register
SEE
IUSI.setUSIIE() // instance |
![](../../../../../Arrow_up.png) |
Sets USIIE register
SEE
IUSI.setUSISTTIE() // instance |
![](../../../../../Arrow_up.png) |
Sets USISTTIE register
Bool setUSISTTIE(Bool set);
SEE