metaonly module ti.catalog.msp430.MSP430F227x
index URL

MSP430F227x Cpu definition

This device has 32KB + 256B of Flash Memory and 1KB RAM. The MSP430F2274 has two op-amps (OA) whereas the MSP430F2272 has none.
XDCspec summary sourced in ti/catalog/msp430/MSP430F227x.xdc
metaonly module MSP430F227x {  ...
// inherits ti.catalog.msp430.IMSP430x22xx
    // inherits ti.catalog.msp430.IMSP430
        // inherits ti.catalog.ICpuDataSheet
            // inherits xdc.platform.ICpuDataSheet
instance:  ...
XDCscript usage meta-domain
var MSP430F227x = xdc.useModule('ti.catalog.msp430.MSP430F227x');
module-wide constants & types
    var obj = new MSP430F227x.Timer// ;
        obj.name = String  ...
        obj.baseAddr = UInt  ...
        obj.intNum = UInt  ...
per-instance config parameters
    var params = new MSP430F227x.Params// Instance config-params object;
        params.commonMap// Memory map elements shared by all MSP430x22xx devices = IPlatform.Memory[string] [
        [
            "PERIPHERALS_8BIT",
            {
                comment: "Memory mapped I/O registers",
                name: "PERIPHERALS_8BIT",
                base: 0x0010,
                len: 0x00F0,
                space: "io",
                access: "RW"
            }
        ],
        [
            "PERIPHERALS_16BIT",
            {
                comment: "Memory mapped I/O registers",
                name: "PERIPHERALS_16BIT",
                base: 0x0100,
                len: 0x0100,
                space: "io",
                access: "RW"
            }
        ],
        [
            "BSLSKEY",
            {
                comment: "Boot loader security key",
                name: "BSLSKEY",
                base: 0xFFDE,
                len: 0x0002,
                space: "data",
                access: "RI"
            }
        ],
        [
            "INT00",
            {
                comment: "Reserved Vector (int00)",
                name: "INT00",
                base: 0xFFE0,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT01",
            {
                comment: "Reserved Vector (int01)",
                name: "INT01",
                base: 0xFFE2,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "IOPORT1",
            {
                comment: "I/O Port P1 Vector (int02)",
                name: "IOPORT1",
                base: 0xFFE4,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "IOPORT2",
            {
                comment: "I/O Port P2 Vector (int03)",
                name: "IOPORT2",
                base: 0xFFE6,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT04",
            {
                comment: "Reserved Vector (int04)",
                name: "INT04",
                base: 0xFFE8,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "ADC10",
            {
                comment: "ADC10 Vector (int05)",
                name: "ADC10",
                base: 0xFFEA,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "USCI_TX",
            {
                comment: "USCI_A0/B0 Transmit Vector (int06)",
                name: "USCI_TX",
                base: 0xFFEC,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "USCI_RX",
            {
                comment: "USCI_A0/B0 Receive Vector (int07)",
                name: "USCI_RX",
                base: 0xFFEE,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "TIMER_A1",
            {
                comment: "Timer_A3 TBCCR1 Vector (int08)",
                name: "TIMER_A1",
                base: 0xFFF0,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "TIMER_A0",
            {
                comment: "Timer_A3 TBCCR0 Vector (int09)",
                name: "TIMER_A0",
                base: 0xFFF2,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT10",
            {
                comment: "Watchdog Vector (int10)",
                name: "INT10",
                base: 0xFFF4,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT11",
            {
                comment: "Reserved Vector (int11)",
                name: "INT11",
                base: 0xFFF6,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "TIMER_B1",
            {
                comment: "Timer_B3 TBCCR1 Vector (int12)",
                name: "TIMER_B1",
                base: 0xFFF8,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "TIMER_B0",
            {
                comment: "Timer_B3 TBCCR0 Vector (int13)",
                name: "TIMER_B0",
                base: 0xFFFA,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "NMI",
            {
                comment: "NMI Vector (int14)",
                name: "NMI",
                base: 0xFFFC,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "RESET",
            {
                comment: "Reset Vector (int15)",
                name: "RESET",
                base: 0xFFFE,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INFO",
            {
                comment: "Information FLASH",
                name: "INFO",
                base: 0x1000,
                len: 0x0100,
                space: "data",
                access: "RW"
            }
        ]
    ];
        params.cpuCore// A string identifying the CPU Core = String "MSP430";
        params.cpuCoreRevision// A string that uniquely identifies a revision of the core = String "1.0";
        params.dataWordSize// The size of an int on the target in 8-bit bytes = Int 2;
        params.isa//  = String "430";
        params.memMap// The default memory map for this device = IPlatform.Memory[string] [
        [
            "RAM",
            {
                comment: "Data RAM",
                name: "RAM",
                base: 0x200,
                len: 0x400,
                space: "code/data",
                access: "RWX"
            }
        ],
        [
            "FLASH",
            {
                comment: "Program FLASH",
                name: "FLASH",
                base: 0x8000,
                len: 0x7FDE,
                space: "code",
                access: "RWX"
            }
        ]
    ];
        params.minDataUnitSize// The minimum addressable data unit size in 8-bit bytes = Int 1;
        params.minProgUnitSize// The minimum addressable program unit size in 8-bit bytes = Int 1;
        params.timers//  = IMSP430x22xx.Timer[2] [
        {
            name: "Timer_A3",
            baseAddr: 0x160,
            intNum: 25
        },
        {
            name: "Timer_B3",
            baseAddr: 0x180,
            intNum: 29
        }
    ];
per-instance creation
    var inst = MSP430F227x.create// Create an instance-object( String revision, params );
per-instance functions
    inst.getMemoryMap// Get the memory map that corresponds to the values of the specified registers( Any registers ) returns Any
    inst.getRegisterSet// The set of valid register names for this CPU( ) returns Any
 
XDCspec declarations sourced in ti/catalog/msp430/MSP430F227x.xdc
package ti.catalog.msp430;
 
metaonly module MSP430F227x inherits IMSP430x22xx {
module-wide constants & types
    metaonly struct Timer//  {
        String name;
        UInt baseAddr;
        UInt intNum;
    };
 
 
instance:
per-instance config parameters
    config IPlatform.Memory commonMap// Memory map elements shared by all MSP430x22xx devices[string] = [
        [
            "PERIPHERALS_8BIT",
            {
                comment: "Memory mapped I/O registers",
                name: "PERIPHERALS_8BIT",
                base: 0x0010,
                len: 0x00F0,
                space: "io",
                access: "RW"
            }
        ],
        [
            "PERIPHERALS_16BIT",
            {
                comment: "Memory mapped I/O registers",
                name: "PERIPHERALS_16BIT",
                base: 0x0100,
                len: 0x0100,
                space: "io",
                access: "RW"
            }
        ],
        [
            "BSLSKEY",
            {
                comment: "Boot loader security key",
                name: "BSLSKEY",
                base: 0xFFDE,
                len: 0x0002,
                space: "data",
                access: "RI"
            }
        ],
        [
            "INT00",
            {
                comment: "Reserved Vector (int00)",
                name: "INT00",
                base: 0xFFE0,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT01",
            {
                comment: "Reserved Vector (int01)",
                name: "INT01",
                base: 0xFFE2,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "IOPORT1",
            {
                comment: "I/O Port P1 Vector (int02)",
                name: "IOPORT1",
                base: 0xFFE4,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "IOPORT2",
            {
                comment: "I/O Port P2 Vector (int03)",
                name: "IOPORT2",
                base: 0xFFE6,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT04",
            {
                comment: "Reserved Vector (int04)",
                name: "INT04",
                base: 0xFFE8,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "ADC10",
            {
                comment: "ADC10 Vector (int05)",
                name: "ADC10",
                base: 0xFFEA,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "USCI_TX",
            {
                comment: "USCI_A0/B0 Transmit Vector (int06)",
                name: "USCI_TX",
                base: 0xFFEC,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "USCI_RX",
            {
                comment: "USCI_A0/B0 Receive Vector (int07)",
                name: "USCI_RX",
                base: 0xFFEE,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "TIMER_A1",
            {
                comment: "Timer_A3 TBCCR1 Vector (int08)",
                name: "TIMER_A1",
                base: 0xFFF0,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "TIMER_A0",
            {
                comment: "Timer_A3 TBCCR0 Vector (int09)",
                name: "TIMER_A0",
                base: 0xFFF2,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT10",
            {
                comment: "Watchdog Vector (int10)",
                name: "INT10",
                base: 0xFFF4,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INT11",
            {
                comment: "Reserved Vector (int11)",
                name: "INT11",
                base: 0xFFF6,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "TIMER_B1",
            {
                comment: "Timer_B3 TBCCR1 Vector (int12)",
                name: "TIMER_B1",
                base: 0xFFF8,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "TIMER_B0",
            {
                comment: "Timer_B3 TBCCR0 Vector (int13)",
                name: "TIMER_B0",
                base: 0xFFFA,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "NMI",
            {
                comment: "NMI Vector (int14)",
                name: "NMI",
                base: 0xFFFC,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "RESET",
            {
                comment: "Reset Vector (int15)",
                name: "RESET",
                base: 0xFFFE,
                len: 0x0002,
                space: "data",
                access: "RW"
            }
        ],
        [
            "INFO",
            {
                comment: "Information FLASH",
                name: "INFO",
                base: 0x1000,
                len: 0x0100,
                space: "data",
                access: "RW"
            }
        ]
    ];
    override config String cpuCore// A string identifying the CPU Core = "MSP430";
    override config String cpuCoreRevision// A string that uniquely identifies a revision of the core = "1.0";
    override config Int dataWordSize// The size of an int on the target in 8-bit bytes = 2;
    config IPlatform.Memory memMap// The default memory map for this device[string] = [
        [
            "RAM",
            {
                comment: "Data RAM",
                name: "RAM",
                base: 0x200,
                len: 0x400,
                space: "code/data",
                access: "RWX"
            }
        ],
        [
            "FLASH",
            {
                comment: "Program FLASH",
                name: "FLASH",
                base: 0x8000,
                len: 0x7FDE,
                space: "code",
                access: "RWX"
            }
        ]
    ];
    override config Int minDataUnitSize// The minimum addressable data unit size in 8-bit bytes = 1;
    override config Int minProgUnitSize// The minimum addressable program unit size in 8-bit bytes = 1;
    config IMSP430x22xx.Timer timers// [2] = [
        {
            name: "Timer_A3",
            baseAddr: 0x160,
            intNum: 25
        },
        {
            name: "Timer_B3",
            baseAddr: 0x180,
            intNum: 29
        }
    ];
per-instance creation
    create// Create an instance-object( String revision );
per-instance functions
    function getMemoryMap// Get the memory map that corresponds to the values of the specified registers( registers );
    function getRegisterSet// The set of valid register names for this CPU( );
}
 
struct MSP430F227x.Timer
index URL
XDCscript usage meta-domain
var obj = new MSP430F227x.Timer;
 
    obj.name = String  ...
    obj.baseAddr = UInt  ...
    obj.intNum = UInt  ...
 
 
per-instance config parameters
index URL

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
// Instance config-params object
    params.commonMap = IPlatform.Memory[string] [
    // Memory map elements shared by all MSP430x22xx devices
    [
        "PERIPHERALS_8BIT",
        {
            comment: "Memory mapped I/O registers",
            name: "PERIPHERALS_8BIT",
            base: 0x0010,
            len: 0x00F0,
            space: "io",
            access: "RW"
        }
    ],
    [
        "PERIPHERALS_16BIT",
        {
            comment: "Memory mapped I/O registers",
            name: "PERIPHERALS_16BIT",
            base: 0x0100,
            len: 0x0100,
            space: "io",
            access: "RW"
        }
    ],
    [
        "BSLSKEY",
        {
            comment: "Boot loader security key",
            name: "BSLSKEY",
            base: 0xFFDE,
            len: 0x0002,
            space: "data",
            access: "RI"
        }
    ],
    [
        "INT00",
        {
            comment: "Reserved Vector (int00)",
            name: "INT00",
            base: 0xFFE0,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT01",
        {
            comment: "Reserved Vector (int01)",
            name: "INT01",
            base: 0xFFE2,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "IOPORT1",
        {
            comment: "I/O Port P1 Vector (int02)",
            name: "IOPORT1",
            base: 0xFFE4,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "IOPORT2",
        {
            comment: "I/O Port P2 Vector (int03)",
            name: "IOPORT2",
            base: 0xFFE6,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT04",
        {
            comment: "Reserved Vector (int04)",
            name: "INT04",
            base: 0xFFE8,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "ADC10",
        {
            comment: "ADC10 Vector (int05)",
            name: "ADC10",
            base: 0xFFEA,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "USCI_TX",
        {
            comment: "USCI_A0/B0 Transmit Vector (int06)",
            name: "USCI_TX",
            base: 0xFFEC,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "USCI_RX",
        {
            comment: "USCI_A0/B0 Receive Vector (int07)",
            name: "USCI_RX",
            base: 0xFFEE,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "TIMER_A1",
        {
            comment: "Timer_A3 TBCCR1 Vector (int08)",
            name: "TIMER_A1",
            base: 0xFFF0,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "TIMER_A0",
        {
            comment: "Timer_A3 TBCCR0 Vector (int09)",
            name: "TIMER_A0",
            base: 0xFFF2,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT10",
        {
            comment: "Watchdog Vector (int10)",
            name: "INT10",
            base: 0xFFF4,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT11",
        {
            comment: "Reserved Vector (int11)",
            name: "INT11",
            base: 0xFFF6,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "TIMER_B1",
        {
            comment: "Timer_B3 TBCCR1 Vector (int12)",
            name: "TIMER_B1",
            base: 0xFFF8,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "TIMER_B0",
        {
            comment: "Timer_B3 TBCCR0 Vector (int13)",
            name: "TIMER_B0",
            base: 0xFFFA,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "NMI",
        {
            comment: "NMI Vector (int14)",
            name: "NMI",
            base: 0xFFFC,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "RESET",
        {
            comment: "Reset Vector (int15)",
            name: "RESET",
            base: 0xFFFE,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INFO",
        {
            comment: "Information FLASH",
            name: "INFO",
            base: 0x1000,
            len: 0x0100,
            space: "data",
            access: "RW"
        }
    ]
];
    params.cpuCore = String "MSP430";
    // A string identifying the CPU Core
    params.cpuCoreRevision = String "1.0";
    // A string that uniquely identifies a revision of the core
    params.dataWordSize = Int 2;
    // The size of an int on the target in 8-bit bytes
    params.isa = String "430";
    // 
    params.memMap = IPlatform.Memory[string] [
    // The default memory map for this device
    [
        "RAM",
        {
            comment: "Data RAM",
            name: "RAM",
            base: 0x200,
            len: 0x400,
            space: "code/data",
            access: "RWX"
        }
    ],
    [
        "FLASH",
        {
            comment: "Program FLASH",
            name: "FLASH",
            base: 0x8000,
            len: 0x7FDE,
            space: "code",
            access: "RWX"
        }
    ]
];
    params.minDataUnitSize = Int 1;
    // The minimum addressable data unit size in 8-bit bytes
    params.minProgUnitSize = Int 1;
    // The minimum addressable program unit size in 8-bit bytes
    params.timers = IMSP430x22xx.Timer[2] [
    // 
    {
        name: "Timer_A3",
        baseAddr: 0x160,
        intNum: 25
    },
    {
        name: "Timer_B3",
        baseAddr: 0x180,
        intNum: 29
    }
];
 
config MSP430F227x.commonMap  // per-instance
index URL

Memory map elements shared by all MSP430x22xx devices

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
  ...
params.commonMap = IPlatform.Memory[string] [
    [
        "PERIPHERALS_8BIT",
        {
            comment: "Memory mapped I/O registers",
            name: "PERIPHERALS_8BIT",
            base: 0x0010,
            len: 0x00F0,
            space: "io",
            access: "RW"
        }
    ],
    [
        "PERIPHERALS_16BIT",
        {
            comment: "Memory mapped I/O registers",
            name: "PERIPHERALS_16BIT",
            base: 0x0100,
            len: 0x0100,
            space: "io",
            access: "RW"
        }
    ],
    [
        "BSLSKEY",
        {
            comment: "Boot loader security key",
            name: "BSLSKEY",
            base: 0xFFDE,
            len: 0x0002,
            space: "data",
            access: "RI"
        }
    ],
    [
        "INT00",
        {
            comment: "Reserved Vector (int00)",
            name: "INT00",
            base: 0xFFE0,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT01",
        {
            comment: "Reserved Vector (int01)",
            name: "INT01",
            base: 0xFFE2,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "IOPORT1",
        {
            comment: "I/O Port P1 Vector (int02)",
            name: "IOPORT1",
            base: 0xFFE4,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "IOPORT2",
        {
            comment: "I/O Port P2 Vector (int03)",
            name: "IOPORT2",
            base: 0xFFE6,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT04",
        {
            comment: "Reserved Vector (int04)",
            name: "INT04",
            base: 0xFFE8,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "ADC10",
        {
            comment: "ADC10 Vector (int05)",
            name: "ADC10",
            base: 0xFFEA,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "USCI_TX",
        {
            comment: "USCI_A0/B0 Transmit Vector (int06)",
            name: "USCI_TX",
            base: 0xFFEC,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "USCI_RX",
        {
            comment: "USCI_A0/B0 Receive Vector (int07)",
            name: "USCI_RX",
            base: 0xFFEE,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "TIMER_A1",
        {
            comment: "Timer_A3 TBCCR1 Vector (int08)",
            name: "TIMER_A1",
            base: 0xFFF0,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "TIMER_A0",
        {
            comment: "Timer_A3 TBCCR0 Vector (int09)",
            name: "TIMER_A0",
            base: 0xFFF2,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT10",
        {
            comment: "Watchdog Vector (int10)",
            name: "INT10",
            base: 0xFFF4,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INT11",
        {
            comment: "Reserved Vector (int11)",
            name: "INT11",
            base: 0xFFF6,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "TIMER_B1",
        {
            comment: "Timer_B3 TBCCR1 Vector (int12)",
            name: "TIMER_B1",
            base: 0xFFF8,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "TIMER_B0",
        {
            comment: "Timer_B3 TBCCR0 Vector (int13)",
            name: "TIMER_B0",
            base: 0xFFFA,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "NMI",
        {
            comment: "NMI Vector (int14)",
            name: "NMI",
            base: 0xFFFC,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "RESET",
        {
            comment: "Reset Vector (int15)",
            name: "RESET",
            base: 0xFFFE,
            len: 0x0002,
            space: "data",
            access: "RW"
        }
    ],
    [
        "INFO",
        {
            comment: "Information FLASH",
            name: "INFO",
            base: 0x1000,
            len: 0x0100,
            space: "data",
            access: "RW"
        }
    ]
];
 
 
config MSP430F227x.cpuCore  // per-instance
index URL

A string identifying the CPU Core

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
  ...
params.cpuCore = String "MSP430";
 
DETAILS
This uniquely identifies the instruction set that the CPU can decode and execute.
 
config MSP430F227x.cpuCoreRevision  // per-instance
index URL

A string that uniquely identifies a revision of the core

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
  ...
params.cpuCoreRevision = String "1.0";
 
 
config MSP430F227x.dataWordSize  // per-instance
index URL

The size of an int on the target in 8-bit bytes

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
  ...
params.dataWordSize = Int 2;
 
 
config MSP430F227x.memMap  // per-instance
index URL

The default memory map for this device

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
  ...
params.memMap = IPlatform.Memory[string] [
    [
        "RAM",
        {
            comment: "Data RAM",
            name: "RAM",
            base: 0x200,
            len: 0x400,
            space: "code/data",
            access: "RWX"
        }
    ],
    [
        "FLASH",
        {
            comment: "Program FLASH",
            name: "FLASH",
            base: 0x8000,
            len: 0x7FDE,
            space: "code",
            access: "RWX"
        }
    ]
];
 
 
config MSP430F227x.minDataUnitSize  // per-instance
index URL

The minimum addressable data unit size in 8-bit bytes

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
  ...
params.minDataUnitSize = Int 1;
 
 
config MSP430F227x.minProgUnitSize  // per-instance
index URL

The minimum addressable program unit size in 8-bit bytes

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
  ...
params.minProgUnitSize = Int 1;
 
 
config MSP430F227x.timers  // per-instance
index URL
XDCscript usage meta-domain
var params = new MSP430F227x.Params;
  ...
params.timers = IMSP430x22xx.Timer[2] [
    {
        name: "Timer_A3",
        baseAddr: 0x160,
        intNum: 25
    },
    {
        name: "Timer_B3",
        baseAddr: 0x180,
        intNum: 29
    }
];
 
 
per-instance creation
index URL

XDCscript usage meta-domain
var params = new MSP430F227x.Params;
// Allocate instance config-params
params.config =   ...
// Assign individual configs
 
var inst = MSP430F227x.create( String revision, params );
// Create an instance-object
ARGUMENTS
revision — a string that identifies revision of the CPU to be created.
DETAILS
A "data sheet" for a CPU allows one to get specific attributes for a CPU programatically; e.g., the memory map of the CPU.
Notice that we don't specify CPU registers when we create a a data-sheet; registers are provided as necessary to the other functions defined in this interface. This allows one to more easily get memory maps for several different setting of the registers, for example.
 
MSP430F227x.getMemoryMap( )  // per-instance
index URL

Get the memory map that corresponds to the values of the specified registers

XDCscript usage meta-domain
inst.getMemoryMap( Any registers ) returns Any
 
ARGUMENTS
registers — a hash of named registers to values at the time an executable is to be loaded (for example)
DETAILS
If a register is not specified and this register can affect the memory map, the register is assumed to be set to its reset value (the value of the register immediately after a CPU reset).
RETURNS
Returns an array of xdc.platform.IPlatform.Memory objects that represent the memory visible to an executable running on the CPU.
 
MSP430F227x.getRegisterSet( )  // per-instance
index URL

The set of valid register names for this CPU

XDCscript usage meta-domain
inst.getRegisterSet( ) returns Any
 
DETAILS
This function returns the complete set of register names that may be passed to the getMemoryMap() function. This function is only used to enable one to write a "requires contract" for the getMemoryMap() function.
RETURNS
Returns an array of valid register names (strings) for this device; only names from this array are valid keys for the registers argument to getMemoryMap().
generated on Fri, 25 Jun 2010 00:02:39 GMT