This device has 8KB + 256B of Flash Memory and 512B RAM. The
MSP430F2234 has two op-amps (OA) whereas the MSP430F2232 has none.
var MSP430F223x = xdc.useModule('ti.catalog.c430.MSP430F223x');
per-instance config parameters
[
"PERIPHERALS_8BIT",
{
comment: "Memory mapped I/O registers",
name: "PERIPHERALS_8BIT",
base: 0x0010,
len: 0x00F0,
space: "io",
access: "RW"
}
],
[
"PERIPHERALS_16BIT",
{
comment: "Memory mapped I/O registers",
name: "PERIPHERALS_16BIT",
base: 0x0100,
len: 0x0100,
space: "io",
access: "RW"
}
],
[
"BSLSKEY",
{
comment: "Boot loader security key",
name: "BSLSKEY",
base: 0xFFDE,
len: 0x0002,
space: "data",
access: "RI"
}
],
[
"INT00",
{
comment: "Reserved Vector (int00)",
name: "INT00",
base: 0xFFE0,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT01",
{
comment: "Reserved Vector (int01)",
name: "INT01",
base: 0xFFE2,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"IOPORT1",
{
comment: "I/O Port P1 Vector (int02)",
name: "IOPORT1",
base: 0xFFE4,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"IOPORT2",
{
comment: "I/O Port P2 Vector (int03)",
name: "IOPORT2",
base: 0xFFE6,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT04",
{
comment: "Reserved Vector (int04)",
name: "INT04",
base: 0xFFE8,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"ADC10",
{
comment: "ADC10 Vector (int05)",
name: "ADC10",
base: 0xFFEA,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"USCI_TX",
{
comment: "USCI_A0/B0 Transmit Vector (int06)",
name: "USCI_TX",
base: 0xFFEC,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"USCI_RX",
{
comment: "USCI_A0/B0 Receive Vector (int07)",
name: "USCI_RX",
base: 0xFFEE,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_A1",
{
comment: "Timer_A3 TBCCR1 Vector (int08)",
name: "TIMER_A1",
base: 0xFFF0,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_A0",
{
comment: "Timer_A3 TBCCR0 Vector (int09)",
name: "TIMER_A0",
base: 0xFFF2,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT10",
{
comment: "Watchdog Vector (int10)",
name: "INT10",
base: 0xFFF4,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT11",
{
comment: "Reserved Vector (int11)",
name: "INT11",
base: 0xFFF6,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_B1",
{
comment: "Timer_B3 TBCCR1 Vector (int12)",
name: "TIMER_B1",
base: 0xFFF8,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_B0",
{
comment: "Timer_B3 TBCCR0 Vector (int13)",
name: "TIMER_B0",
base: 0xFFFA,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"NMI",
{
comment: "NMI Vector (int14)",
name: "NMI",
base: 0xFFFC,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"RESET",
{
comment: "Reset Vector (int15)",
name: "RESET",
base: 0xFFFE,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INFO",
{
comment: "Information FLASH",
name: "INFO",
base: 0x1000,
len: 0x0100,
space: "data",
access: "RW"
}
]
];
[
"RAM",
{
comment: "Data RAM",
name: "RAM",
base: 0x200,
len: 0x200,
space: "code/data",
access: "RWX"
}
],
[
"FLASH",
{
comment: "Program FLASH",
name: "FLASH",
base: 0xE000,
len: 0x1FDE,
space: "code",
access: "RWX"
}
]
];
params.
isa// =
String "430";
per-instance creation
per-instance functions
instance:
per-instance config parameters
[
"PERIPHERALS_8BIT",
{
comment: "Memory mapped I/O registers",
name: "PERIPHERALS_8BIT",
base: 0x0010,
len: 0x00F0,
space: "io",
access: "RW"
}
],
[
"PERIPHERALS_16BIT",
{
comment: "Memory mapped I/O registers",
name: "PERIPHERALS_16BIT",
base: 0x0100,
len: 0x0100,
space: "io",
access: "RW"
}
],
[
"BSLSKEY",
{
comment: "Boot loader security key",
name: "BSLSKEY",
base: 0xFFDE,
len: 0x0002,
space: "data",
access: "RI"
}
],
[
"INT00",
{
comment: "Reserved Vector (int00)",
name: "INT00",
base: 0xFFE0,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT01",
{
comment: "Reserved Vector (int01)",
name: "INT01",
base: 0xFFE2,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"IOPORT1",
{
comment: "I/O Port P1 Vector (int02)",
name: "IOPORT1",
base: 0xFFE4,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"IOPORT2",
{
comment: "I/O Port P2 Vector (int03)",
name: "IOPORT2",
base: 0xFFE6,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT04",
{
comment: "Reserved Vector (int04)",
name: "INT04",
base: 0xFFE8,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"ADC10",
{
comment: "ADC10 Vector (int05)",
name: "ADC10",
base: 0xFFEA,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"USCI_TX",
{
comment: "USCI_A0/B0 Transmit Vector (int06)",
name: "USCI_TX",
base: 0xFFEC,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"USCI_RX",
{
comment: "USCI_A0/B0 Receive Vector (int07)",
name: "USCI_RX",
base: 0xFFEE,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_A1",
{
comment: "Timer_A3 TBCCR1 Vector (int08)",
name: "TIMER_A1",
base: 0xFFF0,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_A0",
{
comment: "Timer_A3 TBCCR0 Vector (int09)",
name: "TIMER_A0",
base: 0xFFF2,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT10",
{
comment: "Watchdog Vector (int10)",
name: "INT10",
base: 0xFFF4,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT11",
{
comment: "Reserved Vector (int11)",
name: "INT11",
base: 0xFFF6,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_B1",
{
comment: "Timer_B3 TBCCR1 Vector (int12)",
name: "TIMER_B1",
base: 0xFFF8,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_B0",
{
comment: "Timer_B3 TBCCR0 Vector (int13)",
name: "TIMER_B0",
base: 0xFFFA,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"NMI",
{
comment: "NMI Vector (int14)",
name: "NMI",
base: 0xFFFC,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"RESET",
{
comment: "Reset Vector (int15)",
name: "RESET",
base: 0xFFFE,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INFO",
{
comment: "Information FLASH",
name: "INFO",
base: 0x1000,
len: 0x0100,
space: "data",
access: "RW"
}
]
];
[
"RAM",
{
comment: "Data RAM",
name: "RAM",
base: 0x200,
len: 0x200,
space: "code/data",
access: "RWX"
}
],
[
"FLASH",
{
comment: "Program FLASH",
name: "FLASH",
base: 0xE000,
len: 0x1FDE,
space: "code",
access: "RWX"
}
]
];
per-instance creation
per-instance functions
}
per-instance config parameters |
![](../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new MSP430F223x.Params;
// Instance config-params object
// Memory map elements shared by all MSP430x22xx devices
[
"PERIPHERALS_8BIT",
{
comment: "Memory mapped I/O registers",
name: "PERIPHERALS_8BIT",
base: 0x0010,
len: 0x00F0,
space: "io",
access: "RW"
}
],
[
"PERIPHERALS_16BIT",
{
comment: "Memory mapped I/O registers",
name: "PERIPHERALS_16BIT",
base: 0x0100,
len: 0x0100,
space: "io",
access: "RW"
}
],
[
"BSLSKEY",
{
comment: "Boot loader security key",
name: "BSLSKEY",
base: 0xFFDE,
len: 0x0002,
space: "data",
access: "RI"
}
],
[
"INT00",
{
comment: "Reserved Vector (int00)",
name: "INT00",
base: 0xFFE0,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT01",
{
comment: "Reserved Vector (int01)",
name: "INT01",
base: 0xFFE2,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"IOPORT1",
{
comment: "I/O Port P1 Vector (int02)",
name: "IOPORT1",
base: 0xFFE4,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"IOPORT2",
{
comment: "I/O Port P2 Vector (int03)",
name: "IOPORT2",
base: 0xFFE6,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT04",
{
comment: "Reserved Vector (int04)",
name: "INT04",
base: 0xFFE8,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"ADC10",
{
comment: "ADC10 Vector (int05)",
name: "ADC10",
base: 0xFFEA,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"USCI_TX",
{
comment: "USCI_A0/B0 Transmit Vector (int06)",
name: "USCI_TX",
base: 0xFFEC,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"USCI_RX",
{
comment: "USCI_A0/B0 Receive Vector (int07)",
name: "USCI_RX",
base: 0xFFEE,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_A1",
{
comment: "Timer_A3 TBCCR1 Vector (int08)",
name: "TIMER_A1",
base: 0xFFF0,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_A0",
{
comment: "Timer_A3 TBCCR0 Vector (int09)",
name: "TIMER_A0",
base: 0xFFF2,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT10",
{
comment: "Watchdog Vector (int10)",
name: "INT10",
base: 0xFFF4,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT11",
{
comment: "Reserved Vector (int11)",
name: "INT11",
base: 0xFFF6,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_B1",
{
comment: "Timer_B3 TBCCR1 Vector (int12)",
name: "TIMER_B1",
base: 0xFFF8,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_B0",
{
comment: "Timer_B3 TBCCR0 Vector (int13)",
name: "TIMER_B0",
base: 0xFFFA,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"NMI",
{
comment: "NMI Vector (int14)",
name: "NMI",
base: 0xFFFC,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"RESET",
{
comment: "Reset Vector (int15)",
name: "RESET",
base: 0xFFFE,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INFO",
{
comment: "Information FLASH",
name: "INFO",
base: 0x1000,
len: 0x0100,
space: "data",
access: "RW"
}
]
];
params.cpuCore = String "MSP430";
// A string identifying the CPU Core
params.cpuCoreRevision = String undefined;
// A string that uniquely identifies a revision of the core
params.dataWordSize = Int 2;
// The size of an int on the target in 8-bit bytes
// Device specific memory blocks
[
"RAM",
{
comment: "Data RAM",
name: "RAM",
base: 0x200,
len: 0x200,
space: "code/data",
access: "RWX"
}
],
[
"FLASH",
{
comment: "Program FLASH",
name: "FLASH",
base: 0xE000,
len: 0x1FDE,
space: "code",
access: "RWX"
}
]
];
params.isa = String "430";
//
params.minDataUnitSize = Int 1;
// The minimum addressable data unit size in 8-bit bytes
params.minProgUnitSize = Int 1;
// The minimum addressable program unit size in 8-bit bytes
config MSP430F223x.commonMap // per-instance |
![](../../../Arrow_up.png) |
Memory map elements shared by all MSP430x22xx devices
XDCscript usage |
meta-domain |
var params = new MSP430F223x.Params;
...
[
"PERIPHERALS_8BIT",
{
comment: "Memory mapped I/O registers",
name: "PERIPHERALS_8BIT",
base: 0x0010,
len: 0x00F0,
space: "io",
access: "RW"
}
],
[
"PERIPHERALS_16BIT",
{
comment: "Memory mapped I/O registers",
name: "PERIPHERALS_16BIT",
base: 0x0100,
len: 0x0100,
space: "io",
access: "RW"
}
],
[
"BSLSKEY",
{
comment: "Boot loader security key",
name: "BSLSKEY",
base: 0xFFDE,
len: 0x0002,
space: "data",
access: "RI"
}
],
[
"INT00",
{
comment: "Reserved Vector (int00)",
name: "INT00",
base: 0xFFE0,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT01",
{
comment: "Reserved Vector (int01)",
name: "INT01",
base: 0xFFE2,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"IOPORT1",
{
comment: "I/O Port P1 Vector (int02)",
name: "IOPORT1",
base: 0xFFE4,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"IOPORT2",
{
comment: "I/O Port P2 Vector (int03)",
name: "IOPORT2",
base: 0xFFE6,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT04",
{
comment: "Reserved Vector (int04)",
name: "INT04",
base: 0xFFE8,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"ADC10",
{
comment: "ADC10 Vector (int05)",
name: "ADC10",
base: 0xFFEA,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"USCI_TX",
{
comment: "USCI_A0/B0 Transmit Vector (int06)",
name: "USCI_TX",
base: 0xFFEC,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"USCI_RX",
{
comment: "USCI_A0/B0 Receive Vector (int07)",
name: "USCI_RX",
base: 0xFFEE,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_A1",
{
comment: "Timer_A3 TBCCR1 Vector (int08)",
name: "TIMER_A1",
base: 0xFFF0,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_A0",
{
comment: "Timer_A3 TBCCR0 Vector (int09)",
name: "TIMER_A0",
base: 0xFFF2,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT10",
{
comment: "Watchdog Vector (int10)",
name: "INT10",
base: 0xFFF4,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INT11",
{
comment: "Reserved Vector (int11)",
name: "INT11",
base: 0xFFF6,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_B1",
{
comment: "Timer_B3 TBCCR1 Vector (int12)",
name: "TIMER_B1",
base: 0xFFF8,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"TIMER_B0",
{
comment: "Timer_B3 TBCCR0 Vector (int13)",
name: "TIMER_B0",
base: 0xFFFA,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"NMI",
{
comment: "NMI Vector (int14)",
name: "NMI",
base: 0xFFFC,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"RESET",
{
comment: "Reset Vector (int15)",
name: "RESET",
base: 0xFFFE,
len: 0x0002,
space: "data",
access: "RW"
}
],
[
"INFO",
{
comment: "Information FLASH",
name: "INFO",
base: 0x1000,
len: 0x0100,
space: "data",
access: "RW"
}
]
];
config MSP430F223x.cpuCore // per-instance |
![](../../../Arrow_up.png) |
A string identifying the CPU Core
XDCscript usage |
meta-domain |
var params = new MSP430F223x.Params;
...
params.cpuCore = String "MSP430";
DETAILS
This uniquely identifies the instruction set that the CPU can
decode and execute.
config MSP430F223x.cpuCoreRevision // per-instance |
![](../../../Arrow_up.png) |
A string that uniquely identifies a revision of the core
XDCscript usage |
meta-domain |
var params = new MSP430F223x.Params;
...
params.cpuCoreRevision = String undefined;
config MSP430F223x.dataWordSize // per-instance |
![](../../../Arrow_up.png) |
The size of an int on the target in 8-bit bytes
XDCscript usage |
meta-domain |
var params = new MSP430F223x.Params;
...
params.dataWordSize = Int 2;
config MSP430F223x.deviceMap // per-instance |
![](../../../Arrow_up.png) |
Device specific memory blocks
XDCscript usage |
meta-domain |
var params = new MSP430F223x.Params;
...
[
"RAM",
{
comment: "Data RAM",
name: "RAM",
base: 0x200,
len: 0x200,
space: "code/data",
access: "RWX"
}
],
[
"FLASH",
{
comment: "Program FLASH",
name: "FLASH",
base: 0xE000,
len: 0x1FDE,
space: "code",
access: "RWX"
}
]
];
DETAILS
This memory together with the common family memory forms the
complete memory map retuned by getMemoryMap().
config MSP430F223x.minDataUnitSize // per-instance |
![](../../../Arrow_up.png) |
The minimum addressable data unit size in 8-bit bytes
XDCscript usage |
meta-domain |
var params = new MSP430F223x.Params;
...
params.minDataUnitSize = Int 1;
config MSP430F223x.minProgUnitSize // per-instance |
![](../../../Arrow_up.png) |
The minimum addressable program unit size in 8-bit bytes
XDCscript usage |
meta-domain |
var params = new MSP430F223x.Params;
...
params.minProgUnitSize = Int 1;
per-instance creation |
![](../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params =
new MSP430F223x.
Params;
// Allocate instance config-params
params.config = ...
// Assign individual configs
var inst = MSP430F223x.create( String revision, params );
// Create an instance-object
ARGUMENTS
revision
a string that identifies revision of the CPU to be
created.
DETAILS
A "data sheet" for a CPU allows one to get specific attributes
for a CPU programatically; e.g., the memory map of the CPU.
Notice that we don't specify CPU registers when we create a
a data-sheet; registers are provided as necessary to the other
functions defined in this interface. This allows one to more easily
get memory maps for several different setting of the registers,
for example.
MSP430F223x.getMemoryMap( ) // per-instance |
![](../../../Arrow_up.png) |
Get the memory map that corresponds to the values of the specified
registers
XDCscript usage |
meta-domain |
inst.getMemoryMap( Any registers ) returns Any
ARGUMENTS
registers
a hash of named registers to values at the time
an executable is to be loaded (for example)
DETAILS
If a register is not specified and this register can affect the
memory map, the register is assumed to be set to its reset
value (the value of the register immediately after a CPU reset).
RETURNS
Returns an array of
xdc.platform.IPlatform.Memory
objects that represent the memory visible to an
executable running on the CPU.
MSP430F223x.getRegisterSet( ) // per-instance |
![](../../../Arrow_up.png) |
The set of valid register names for this CPU
XDCscript usage |
meta-domain |
inst.getRegisterSet( ) returns Any
DETAILS
This function returns the complete set of register names that may be
passed to the
getMemoryMap() function. This function is
only used to enable one to write a "requires contract" for the
getMemoryMap() function.
RETURNS
Returns an array of valid register names (strings) for
this device; only names from this array are valid keys
for the registers argument to
getMemoryMap().