The Cache module provide APIs to allow applications to maintain cache
coherency.
This module will use an OS specific delegate (back-end) to manipulate the
cache.
This module has a module wide config parameter
Proxy which needs to
be bound to an OS specific delegate before this module can be used.
Here is an example showing how the proxy is bound to an BIOS 6.x specific
delegate
var Cache = xdc.useModule('xdc.runtime.knl.Cache');
Cache.Proxy = xdc.useModule('ti.sysbios.xdcruntime.CacheSupport');
Typically the package containing the delegates have a Settings module that
will bind all
xdc.runtime.knl proxies. The following
example sets up all the xdc.runtime.knl proxies.
proxy Cache.Proxy |
|
ICacheSupport proxy
XDCscript usage |
meta-domain |
// explicit access to the currently bound delegate module
DETAILS
Cache will use this proxy to access the cache hardware using
OS specific APIs.
metaonly config Cache.common$ // module-wide |
|
Common module configuration parameters
XDCscript usage |
meta-domain |
DETAILS
All modules have this configuration parameter. Its name
contains the '$' character to ensure it does not conflict with
configuration parameters declared by the module. This allows
new configuration parameters to be added in the future without
any chance of breaking existing modules.
Cache.inv( ) // module-wide |
|
Invalidate range of memory for all cache(s)
Bool Cache_inv(
Ptr blockPtr,
SizeT byteCnt,
Bool wait,
Error_Block *
eb );
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
wait
wait until the operation is completed
eb
error block
DETAILS
Invalidate the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
in range are invalidated for all cache types.
RETURNS
true for success; false for error.
Cache.wait( ) // module-wide |
|
Wait for a previous cache operation to complete
ARGUMENTS
eb
error block
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache
operation is not truly complete until it has worked its way
through all buffering and all memory writes have landed in the
source memory.
RETURNS
true for success; false for error.
Cache.wb( ) // module-wide |
|
Writes back a range of memory from all cache(s)
Bool Cache_wb(
Ptr blockPtr,
SizeT byteCnt,
Bool wait,
Error_Block *
eb );
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
wait
wait until the operation is completed
eb
error block
DETAILS
Writes back the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
within the range are left valid in all caches and the data
within the range will be written back to the source memory.
RETURNS
true for success; false for error.
Cache.wbInv( ) // module-wide |
|
Write back and invalidate range of memory
Bool Cache_wbInv(
Ptr blockPtr,
SizeT byteCnt,
Bool wait,
Error_Block *
eb );
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
wait
wait until the operation is completed
eb
error block
DETAILS
Writes back and invalidates the range of memory within the
specified starting address and byte count. The range of
addresses operated on gets quantized to whole cache lines in
each cache. All lines within the range are written back to the
source memory and then invalidated for all cache types.
RETURNS
true for success; false for error.
module-wide built-ins |
|
// Get this module's unique id
Bool Cache_Module_startupDone( );
// Test if this module has completed startup
// The heap from which this module allocates memory