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TI-RTOS Drivers
tidrivers_full_2_20_01_10
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UDMACC3200 Hardware attributes. More...
#include <UDMACC3200.h>
Data Fields | |
void * | controlBaseAddr |
UDMACC3200_ErrorFxn | dmaErrorFxn |
uint8_t | intNum |
uint8_t | intPriority |
UDMACC3200 Hardware attributes.
This structure contains the base address of the uDMA control table, and uDMA error interrupt attributes.
The control table is used by the uDMA controller to store channel control structures. The control table can be located anywhere in system memory, but must be contiguous and aligned on a 1024-byte boundary.
dmaErrorFxn is the uDMA peripheral's error interrupt handler.
intPriority is priority of the uDMA peripheral's error interrupt, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.drivers.ports interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().
A sample structure is shown below:
void* UDMACC3200_HWAttrs::controlBaseAddr |
uDMA control registers base address
UDMACC3200_ErrorFxn UDMACC3200_HWAttrs::dmaErrorFxn |
uDMA error interrupt handler
uint8_t UDMACC3200_HWAttrs::intNum |
uDMA error interrupt number
uint8_t UDMACC3200_HWAttrs::intPriority |
uDMA error interrupt priority.