49 #define RF_MODE_BLE 0x01
50 #define RF_MODE_IEEE_15_4 0x02
51 #define RF_MODE_PROPRIETARY_2_4 0x03
52 #define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4
53 #define RF_MODE_MULTIPLE 0x05
73 #define IRQN_COMMAND_DONE 0
74 #define IRQN_LAST_COMMAND_DONE 1
75 #define IRQN_FG_COMMAND_DONE 2
76 #define IRQN_LAST_FG_COMMAND_DONE 3
77 #define IRQN_TX_DONE 4
79 #define IRQN_TX_CTRL 6
80 #define IRQN_TX_CTRL_ACK 7
81 #define IRQN_TX_CTRL_ACK_ACK 8
82 #define IRQN_TX_RETRANS 9
83 #define IRQN_TX_ENTRY_DONE 10
84 #define IRQN_TX_BUFFER_CHANGED 11
86 #define IRQN_RX_NOK 17
87 #define IRQN_RX_IGNORED 18
88 #define IRQN_RX_EMPTY 19
89 #define IRQN_RX_CTRL 20
90 #define IRQN_RX_CTRL_ACK 21
91 #define IRQN_RX_BUF_FULL 22
92 #define IRQN_RX_ENTRY_DONE 23
93 #define IRQN_RX_DATA_WRITTEN 24
94 #define IRQN_RX_N_DATA_WRITTEN 25
95 #define IRQN_RX_ABORTED 26
96 #define IRQN_RX_COLLISION_DETECTED 27
97 #define IRQN_SYNTH_NO_LOCK 28
98 #define IRQN_MODULES_UNLOCKED 29
99 #define IRQN_BOOT_DONE 30
101 #define IRQN_INTERNAL_ERROR 31
103 #define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE)
104 #define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE)
105 #define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE)
106 #define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE)
108 #define IRQ_TX_DONE (1U << IRQN_TX_DONE)
109 #define IRQ_TX_ACK (1U << IRQN_TX_ACK)
110 #define IRQ_TX_CTRL (1U << IRQN_TX_CTRL)
111 #define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK)
112 #define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK)
113 #define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS)
115 #define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE)
116 #define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED)
118 #define IRQ_RX_OK (1U << IRQN_RX_OK)
119 #define IRQ_RX_NOK (1U << IRQN_RX_NOK)
120 #define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED)
121 #define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY)
122 #define IRQ_RX_CTRL (1U << IRQN_RX_CTRL)
123 #define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK)
124 #define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL)
125 #define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE)
126 #define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN)
127 #define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN)
128 #define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED)
129 #define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED)
130 #define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK)
131 #define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED)
132 #define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE)
133 #define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR)
141 #define CMDSTA_Pending 0x00
142 #define CMDSTA_Done 0x01
144 #define CMDSTA_IllegalPointer 0x81
145 #define CMDSTA_UnknownCommand 0x82
146 #define CMDSTA_UnknownDirCommand 0x83
147 #define CMDSTA_ContextError 0x85
149 #define CMDSTA_SchedulingError 0x86
151 #define CMDSTA_ParError 0x87
153 #define CMDSTA_QueueError 0x88
155 #define CMDSTA_QueueBusy 0x89
165 #define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1)
168 #define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1)
171 #define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1)
181 #define TRIG_ABSTIME 2
182 #define TRIG_REL_SUBMIT 3
183 #define TRIG_REL_START 4
184 #define TRIG_REL_PREVSTART 5
185 #define TRIG_REL_FIRSTSTART 6
186 #define TRIG_REL_PREVEND 7
187 #define TRIG_REL_EVT1 8
188 #define TRIG_REL_EVT2 9
189 #define TRIG_EXTERNAL 10
190 #define TRIG_PAST_BM 0x80
197 #define COND_ALWAYS 0
199 #define COND_STOP_ON_FALSE 2
200 #define COND_STOP_ON_TRUE 3
202 #define COND_SKIP_ON_FALSE 4
204 #define COND_SKIP_ON_TRUE 5
216 #define PENDING 0x0001
217 #define ACTIVE 0x0002
218 #define SKIPPED 0x0003
219 #define DONE_OK 0x0400
223 #define DONE_COUNTDOWN 0x0401
224 #define DONE_RXERR 0x0402
225 #define DONE_TIMEOUT 0x0403
226 #define DONE_STOPPED 0x0404
227 #define DONE_ABORT 0x0405
228 #define DONE_FAILED 0x0406
229 #define ERROR_PAST_START 0x0800
233 #define ERROR_START_TRIG 0x0801
234 #define ERROR_CONDITION 0x0802
235 #define ERROR_PAR 0x0803
236 #define ERROR_POINTER 0x0804
237 #define ERROR_CMDID 0x0805
238 #define ERROR_WRONG_BG 0x0806
240 #define ERROR_NO_SETUP 0x0807
241 #define ERROR_NO_FS 0x0808
242 #define ERROR_SYNTH_PROG 0x0809
243 #define ERROR_TXUNF 0x080A
244 #define ERROR_RXOVF 0x080B
245 #define ERROR_NO_RX 0x080C
246 #define ERROR_PENDING 0x080D
253 #define DATA_ENTRY_TYPE_GEN 0
254 #define DATA_ENTRY_TYPE_MULTI 1
255 #define DATA_ENTRY_TYPE_PTR 2
256 #define DATA_ENTRY_TYPE_PARTIAL 3
262 #define DATA_ENTRY_PENDING 0
263 #define DATA_ENTRY_ACTIVE 1
264 #define DATA_ENTRY_BUSY 2
265 #define DATA_ENTRY_FINISHED 3
266 #define DATA_ENTRY_UNFINISHED 4
274 #define ADI_VAL_MASK(addr, mask, value) \
275 (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \
276 ((((mask) & 0x0F) << 4) | ((value) & 0x0F)))
277 #define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16))
279 #define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \
281 (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
282 #define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \
284 (2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \
285 (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
286 #define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \
288 (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
289 #define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \
291 (2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \
292 (ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
295 #define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16))
296 #define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \
298 (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16))
299 #define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \
301 ((uint32_t)(val) << 16))
302 #define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \
304 (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24))
305 #define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
306 #define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \
307 ((uint32_t)(length) << 16) | (1U << 30))
308 #define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \
309 ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30))
310 #define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \
311 ((uint32_t)(length) << 16) | (3U << 30))
312 #define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \
313 (7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \
314 (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24))
315 #define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \
316 (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \
317 (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \
318 (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \
319 (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \
320 (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \
321 (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \
322 (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \
323 (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \
324 0x09) << 4)) // Use illegal value for illegal address range
325 #define END_OVERRIDE 0xFFFFFFFF
330 #define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF))
331 #define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value))
334 #define LOWORD(value) ((value) & 0xFFFF)
335 #define HIWORD(value) ((value) >> 16)
uint8_t * pCurrEntry
Pointer to the data queue entry to be used, NULL for an empty queue.
uint8_t * pLastEntry
Pointer to the last entry in the queue, NULL for a circular queue.
uint32_t ratmr_t
Type definition for RAT.
Type definition for a data queue.