rf_mailbox.h

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/******************************************************************************
*  Filename:       rf_mailbox.h
*  Revised:        $ $
*  Revision:       $ $
*
*  Description:    Definitions for interface between system and radio CPU
*
*  Copyright (c) 2015 - 2016, Texas Instruments Incorporated
*  All rights reserved.
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions are met:
*
*  1) Redistributions of source code must retain the above copyright notice,
*     this list of conditions and the following disclaimer.
*
*  2) Redistributions in binary form must reproduce the above copyright notice,
*     this list of conditions and the following disclaimer in the documentation
*     and/or other materials provided with the distribution.
*
*  3) Neither the name of the ORGANIZATION nor the names of its contributors may
*     be used to endorse or promote products derived from this software without
*     specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
*  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
*  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
*  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
*  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
*  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
*  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
*  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
*  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
*  POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/

#ifndef _MAILBOX_H
#define _MAILBOX_H

#include <stdint.h>
#include <string.h>


#define RF_MODE_PROPRIETARY_SUB_1  0x00
#define RF_MODE_BLE                0x01
#define RF_MODE_IEEE_15_4          0x02
#define RF_MODE_PROPRIETARY_2_4    0x03
#define RF_MODE_PROPRIETARY        RF_MODE_PROPRIETARY_2_4
#define RF_MODE_MULTIPLE           0x05


typedef uint32_t ratmr_t;



typedef struct {
   uint8_t *pCurrEntry;   
   uint8_t *pLastEntry;   
} dataQueue_t;



#define IRQN_COMMAND_DONE           0           
#define IRQN_LAST_COMMAND_DONE      1           
#define IRQN_FG_COMMAND_DONE        2           
#define IRQN_LAST_FG_COMMAND_DONE   3           
#define IRQN_TX_DONE                4           
#define IRQN_TX_ACK                 5           
#define IRQN_TX_CTRL                6           
#define IRQN_TX_CTRL_ACK            7           
#define IRQN_TX_CTRL_ACK_ACK        8           
#define IRQN_TX_RETRANS             9           
#define IRQN_TX_ENTRY_DONE          10          
#define IRQN_TX_BUFFER_CHANGED      11          
#define IRQN_RX_OK                  16          
#define IRQN_RX_NOK                 17          
#define IRQN_RX_IGNORED             18          
#define IRQN_RX_EMPTY               19          
#define IRQN_RX_CTRL                20          
#define IRQN_RX_CTRL_ACK            21          
#define IRQN_RX_BUF_FULL            22          
#define IRQN_RX_ENTRY_DONE          23          
#define IRQN_RX_DATA_WRITTEN        24          
#define IRQN_RX_N_DATA_WRITTEN      25          
#define IRQN_RX_ABORTED             26          
#define IRQN_RX_COLLISION_DETECTED  27          
#define IRQN_SYNTH_NO_LOCK          28          
#define IRQN_MODULES_UNLOCKED       29          
#define IRQN_BOOT_DONE              30          

#define IRQN_INTERNAL_ERROR         31          

#define IRQ_COMMAND_DONE            (1U << IRQN_COMMAND_DONE)
#define IRQ_LAST_COMMAND_DONE       (1U << IRQN_LAST_COMMAND_DONE)
#define IRQ_FG_COMMAND_DONE         (1U << IRQN_FG_COMMAND_DONE)
#define IRQ_LAST_FG_COMMAND_DONE    (1U << IRQN_LAST_FG_COMMAND_DONE)

#define IRQ_TX_DONE                 (1U << IRQN_TX_DONE)
#define IRQ_TX_ACK                  (1U << IRQN_TX_ACK)
#define IRQ_TX_CTRL                 (1U << IRQN_TX_CTRL)
#define IRQ_TX_CTRL_ACK             (1U << IRQN_TX_CTRL_ACK)
#define IRQ_TX_CTRL_ACK_ACK         (1U << IRQN_TX_CTRL_ACK_ACK)
#define IRQ_TX_RETRANS              (1U << IRQN_TX_RETRANS)

#define IRQ_TX_ENTRY_DONE           (1U << IRQN_TX_ENTRY_DONE)
#define IRQ_TX_BUFFER_CHANGED       (1U << IRQN_TX_BUFFER_CHANGED)

#define IRQ_RX_OK                   (1U << IRQN_RX_OK)
#define IRQ_RX_NOK                  (1U << IRQN_RX_NOK)
#define IRQ_RX_IGNORED              (1U << IRQN_RX_IGNORED)
#define IRQ_RX_EMPTY                (1U << IRQN_RX_EMPTY)
#define IRQ_RX_CTRL                 (1U << IRQN_RX_CTRL)
#define IRQ_RX_CTRL_ACK             (1U << IRQN_RX_CTRL_ACK)
#define IRQ_RX_BUF_FULL             (1U << IRQN_RX_BUF_FULL)
#define IRQ_RX_ENTRY_DONE           (1U << IRQN_RX_ENTRY_DONE)
#define IRQ_RX_DATA_WRITTEN         (1U << IRQN_RX_DATA_WRITTEN)
#define IRQ_RX_N_DATA_WRITTEN       (1U << IRQN_RX_N_DATA_WRITTEN)
#define IRQ_RX_ABORTED              (1U << IRQN_RX_ABORTED)
#define IRQ_RX_COLLISION_DETECTED   (1U << IRQN_RX_COLLISION_DETECTED)
#define IRQ_SYNTH_NO_LOCK           (1U << IRQN_SYNTH_NO_LOCK)
#define IRQ_MODULES_UNLOCKED        (1U << IRQN_MODULES_UNLOCKED)
#define IRQ_BOOT_DONE               (1U << IRQN_BOOT_DONE)
#define IRQ_INTERNAL_ERROR          (1U << IRQN_INTERNAL_ERROR)



#define CMDSTA_Pending 0x00              
#define CMDSTA_Done 0x01                 

#define CMDSTA_IllegalPointer 0x81       
#define CMDSTA_UnknownCommand 0x82       
#define CMDSTA_UnknownDirCommand 0x83    
#define CMDSTA_ContextError 0x85         
#define CMDSTA_SchedulingError 0x86      
#define CMDSTA_ParError 0x87             
#define CMDSTA_QueueError 0x88           
#define CMDSTA_QueueBusy 0x89            



#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1)

#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1)

#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1)




#define TRIG_NOW 0            
#define TRIG_NEVER 1          
#define TRIG_ABSTIME 2        
#define TRIG_REL_SUBMIT 3     
#define TRIG_REL_START 4      
#define TRIG_REL_PREVSTART 5  
#define TRIG_REL_FIRSTSTART 6 
#define TRIG_REL_PREVEND 7    
#define TRIG_REL_EVT1 8       
#define TRIG_REL_EVT2 9       
#define TRIG_EXTERNAL 10      
#define TRIG_PAST_BM 0x80     


#define COND_ALWAYS 0         
#define COND_NEVER 1          
#define COND_STOP_ON_FALSE 2  
#define COND_STOP_ON_TRUE 3   
#define COND_SKIP_ON_FALSE 4  
#define COND_SKIP_ON_TRUE 5   



#define IDLE             0x0000   
#define PENDING          0x0001   
#define ACTIVE           0x0002   
#define SKIPPED          0x0003   
#define DONE_OK          0x0400   
#define DONE_COUNTDOWN   0x0401   
#define DONE_RXERR       0x0402   
#define DONE_TIMEOUT     0x0403   
#define DONE_STOPPED     0x0404   
#define DONE_ABORT       0x0405   
#define DONE_FAILED      0x0406   
#define ERROR_PAST_START 0x0800   
#define ERROR_START_TRIG 0x0801   
#define ERROR_CONDITION  0x0802   
#define ERROR_PAR        0x0803   
#define ERROR_POINTER    0x0804   
#define ERROR_CMDID      0x0805   
#define ERROR_WRONG_BG   0x0806   
#define ERROR_NO_SETUP   0x0807   
#define ERROR_NO_FS      0x0808   
#define ERROR_SYNTH_PROG 0x0809   
#define ERROR_TXUNF      0x080A   
#define ERROR_RXOVF      0x080B   
#define ERROR_NO_RX      0x080C   
#define ERROR_PENDING    0x080D   


#define DATA_ENTRY_TYPE_GEN 0     
#define DATA_ENTRY_TYPE_MULTI 1   
#define DATA_ENTRY_TYPE_PTR 2     
#define DATA_ENTRY_TYPE_PARTIAL 3 


#define DATA_ENTRY_PENDING 0      
#define DATA_ENTRY_ACTIVE 1       
#define DATA_ENTRY_BUSY 2         
#define DATA_ENTRY_FINISHED 3     
#define DATA_ENTRY_UNFINISHED 4   



#define ADI_VAL_MASK(addr, mask, value) \
(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \
 ((((mask) & 0x0F) << 4) | ((value) & 0x0F)))
#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16))
#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \
(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \
(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \
(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \
(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \
(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \
(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))

#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16))
#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \
(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16))
#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \
((uint32_t)(val) << 16))
#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \
                                                       (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24))
#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \
((uint32_t)(length) << 16) | (1U << 30))
#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \
((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30))
#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \
((uint32_t)(length) << 16) | (3U << 30))
#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \
   (7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \
    (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24))
#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \
   (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \
     (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \
     (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \
     (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \
     (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \
     (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \
     (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \
     (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \
     0x09) << 4)) // Use illegal value for illegal address range
#define END_OVERRIDE 0xFFFFFFFF


#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF))
#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value))

#define LOWORD(value) ((value) & 0xFFFF)
#define HIWORD(value) ((value) >> 16)


#endif