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ti
sdo
fc
ires
edma3chan
ires_edma3Chan.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2012, Texas Instruments Incorporated
3
* All rights reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions
7
* are met:
8
*
9
* * Redistributions of source code must retain the above copyright
10
* notice, this list of conditions and the following disclaimer.
11
*
12
* * Redistributions in binary form must reproduce the above copyright
13
* notice, this list of conditions and the following disclaimer in the
14
* documentation and/or other materials provided with the distribution.
15
*
16
* * Neither the name of Texas Instruments Incorporated nor the names of
17
* its contributors may be used to endorse or promote products derived
18
* from this software without specific prior written permission.
19
*
20
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31
*
32
*/
48
#ifndef ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
49
#define ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
50
53
54
#ifdef __cplusplus
55
extern
"C"
{
56
#endif
57
58
#include <
ti/xdais/xdas.h
>
59
#include <
ti/xdais/ires_common.h
>
60
64
#define IRES_EDMA3CHAN_PROTOCOLNAME "ti.sdo.fc.ires.edma3chan"
65
76
#define EDMA3CHAN_MODNAME "ti.sdo.fc.ires.edma3chan"
77
78
/*
79
* Note, we wrap the PROTOCOLVERSION in an ifdef so the
80
* resource managers and algs get this version data placed in their object
81
* files. Apps, which include rman.h, will have this 'NOPROTOCOLREV' defined.
82
*/
83
#ifndef ti_sdo_fc_ires_NOPROTOCOLREV
84
89
static
IRES_ProtocolRevision
IRES_EDMA3CHAN_PROTOCOLREVISION = {1, 0, 0};
90
91
#endif
92
96
#define IRES_EDMA3CHAN_PROTOCOLREVISION_1_0_0 {1, 0, 0}
97
#define IRES_EDMA3CHAN_SETPROTOCOLREVISION_1_0_0(rev) {(rev)->Major = 1; \
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(rev)->Source = 0; (rev)->Radius = 0;}
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103
#define IRES_EDMA3CHAN_PROTOCOLREVISION_2_0_0 {2, 0, 0}
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#define IRES_EDMA3CHAN_SETPROTOCOLREVISION_2_0_0(rev) {(rev)->Major = 2; \
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(rev)->Source = 0; (rev)->Radius = 0;}
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111
#define IRES_EDMA3CHAN_MAXPARAMS 512
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#define IRES_EDMA3CHAN_MAXTCCS 32
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#define IRES_EDMA3CHAN_NUMDESTTYPES 8
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118
#define IRES_EDMA3CHAN_PARAM_ANY 512
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#define IRES_EDMA3CHAN_PARAM_NONE 513
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#define IRES_EDMA3CHAN_TCC_ANY 514
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#define IRES_EDMA3CHAN_TCC_NONE 515
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#define IRES_EDMA3CHAN_EDMACHAN_ANY 516
123
#define IRES_EDMA3CHAN_QDMACHAN_ANY 516
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#define IRES_EDMA3CHAN_CHAN_NONE 518
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129
typedef
struct
IRES_EDMA3CHAN_Obj
*
IRES_EDMA3CHAN_Handle
;
130
134
typedef
struct
IRES_EDMA3CHAN2_Obj
*
IRES_EDMA3CHAN2_Handle
;
135
141
/* Note that the field descriptions were originally taken from SPRU996. */
142
typedef
struct
IRES_EDMA3CHAN_PaRamStruct
{
143
unsigned
int
opt
;
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unsigned
int
src
;
153
unsigned
short
acnt
;
164
unsigned
short
bcnt
;
174
unsigned
int
dst
;
179
unsigned
short
srcElementIndex
;
189
unsigned
short
dstElementIndex
;
200
unsigned
short
link
;
211
unsigned
short
bCntrld
;
222
unsigned
short
srcFrameIndex
;
248
unsigned
short
dstFrameIndex
;
276
unsigned
short
ccnt
;
287
unsigned
short
rsvd
;
288
}
IRES_EDMA3CHAN_PaRamStruct
;
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290
309
typedef
struct
IRES_EDMA3CHAN_ProtocolArgs
{
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int
size
;
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IRES_RequestMode
mode
;
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short
numPaRams
;
321
short
paRamIndex
;
330
short
numTccs
;
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short
tccIndex
;
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short
qdmaChan
;
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short
edmaChan
;
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short
contiguousAllocation
;
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short
shadowPaRamsAllocation
;
373
}
IRES_EDMA3CHAN_ProtocolArgs
;
374
385
typedef
struct
IRES_EDMA3CHAN_Obj
{
386
387
IRES_Obj
ires
;
388
IRES_EDMA3CHAN_PaRamStruct
*
shadowPaRams
;
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unsigned
int
*
assignedPaRamAddresses
;
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short
*
assignedPaRamIndices
;
395
short
*
assignedTccIndices
;
396
short
assignedNumPaRams
;
397
short
assignedNumTccs
;
398
short
assignedQdmaChannelIndex
;
406
short
assignedEdmaChannelIndex
;
414
unsigned
int
esrBitMaskL
;
423
unsigned
int
esrBitMaskH
;
432
unsigned
int
iprBitMaskL
;
441
unsigned
int
iprBitMaskH
;
450
}
IRES_EDMA3CHAN_Obj
;
451
455
typedef
struct
IRES_EDMA3CHAN_EDMA3ShadowRegister
{
456
volatile
unsigned
int
ER
;
457
volatile
unsigned
int
ERH
;
458
volatile
unsigned
int
ECR
;
459
volatile
unsigned
int
ECRH
;
460
volatile
unsigned
int
ESR
;
461
volatile
unsigned
int
ESRH
;
462
volatile
unsigned
int
CER
;
463
volatile
unsigned
int
CERH
;
464
volatile
unsigned
int
EER
;
465
volatile
unsigned
int
EERH
;
466
volatile
unsigned
int
EECR
;
467
volatile
unsigned
int
EECRH
;
468
volatile
unsigned
int
EESR
;
469
volatile
unsigned
int
EESRH
;
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volatile
unsigned
int
SER
;
471
volatile
unsigned
int
SERH
;
472
volatile
unsigned
int
SECR
;
473
volatile
unsigned
int
SECRH
;
474
volatile
unsigned
char
RSVD0
[8];
475
volatile
unsigned
int
IER
;
476
volatile
unsigned
int
IERH
;
477
volatile
unsigned
int
IECR
;
478
volatile
unsigned
int
IECRH
;
479
volatile
unsigned
int
IESR
;
480
volatile
unsigned
int
IESRH
;
481
volatile
unsigned
int
IPR
;
482
volatile
unsigned
int
IPRH
;
483
volatile
unsigned
int
ICR
;
484
volatile
unsigned
int
ICRH
;
485
volatile
unsigned
int
IEVAL
;
486
volatile
unsigned
char
RSVD1
[4];
487
volatile
unsigned
int
QER
;
488
volatile
unsigned
int
QEER
;
489
volatile
unsigned
int
QEECR
;
490
volatile
unsigned
int
QEESR
;
491
volatile
unsigned
int
QSER
;
492
volatile
unsigned
int
QSECR
;
493
volatile
unsigned
char
RSVD2
[360];
494
495
}
IRES_EDMA3CHAN_EDMA3ShadowRegister
;
496
501
typedef
struct
IRES_EDMA3CHAN_EDMA3DraeRegister
{
502
volatile
unsigned
int
DRAE
;
503
volatile
unsigned
int
DRAEH
;
504
}
IRES_EDMA3CHAN_EDMA3DraeRegister
;
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typedef
struct
IRES_EDMA3CHAN_EDMA3RegisterLayer
{
510
volatile
unsigned
int
REV
;
511
volatile
unsigned
int
CCCFG
;
512
volatile
unsigned
char
RSVD0
[248];
513
volatile
unsigned
int
DCHMAP
[64];
514
volatile
unsigned
int
QCHMAP
[8];
515
volatile
unsigned
char
RSVD1
[32];
516
volatile
unsigned
int
DMAQNUM
[8];
517
volatile
unsigned
int
QDMAQNUM
;
518
volatile
unsigned
char
RSVD2
[28];
519
volatile
unsigned
int
QUETCMAP
;
520
volatile
unsigned
int
QUEPRI
;
521
volatile
unsigned
char
RSVD3
[120];
522
volatile
unsigned
int
EMR
;
523
volatile
unsigned
int
EMRH
;
524
volatile
unsigned
int
EMCR
;
525
volatile
unsigned
int
EMCRH
;
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volatile
unsigned
int
QEMR
;
527
volatile
unsigned
int
QEMCR
;
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volatile
unsigned
int
CCERR
;
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volatile
unsigned
int
CCERRCLR
;
530
volatile
unsigned
int
EEVAL
;
531
volatile
unsigned
char
RSVD4
[28];
532
IRES_EDMA3CHAN_EDMA3DraeRegister
DRA
[8];
533
volatile
unsigned
int
QRAE
[8];
534
volatile
unsigned
char
RSVD5
[96];
535
volatile
unsigned
int
QUEEVTENTRY
[8][16];
536
volatile
unsigned
int
QSTAT
[8];
537
volatile
unsigned
int
QWMTHRA
;
538
volatile
unsigned
int
QWMTHRB
;
539
volatile
unsigned
char
RSVD6
[24];
540
volatile
unsigned
int
CCSTAT
;
541
volatile
unsigned
char
RSVD7
[188];
542
volatile
unsigned
int
AETCTL
;
543
volatile
unsigned
int
AETSTAT
;
544
volatile
unsigned
int
AETCMD
;
545
volatile
unsigned
char
RSVD8
[244];
546
volatile
unsigned
int
MPFAR
;
547
volatile
unsigned
int
MPFSR
;
548
volatile
unsigned
int
MPFCR
;
549
volatile
unsigned
int
MPPAG
;
550
volatile
unsigned
int
MPPA
[8];
551
volatile
unsigned
char
RSVD9
[2000];
552
volatile
unsigned
int
ER
;
553
volatile
unsigned
int
ERH
;
554
volatile
unsigned
int
ECR
;
555
volatile
unsigned
int
ECRH
;
556
volatile
unsigned
int
ESR
;
557
volatile
unsigned
int
ESRH
;
558
volatile
unsigned
int
CER
;
559
volatile
unsigned
int
CERH
;
560
volatile
unsigned
int
EER
;
561
volatile
unsigned
int
EERH
;
562
volatile
unsigned
int
EECR
;
563
volatile
unsigned
int
EECRH
;
564
volatile
unsigned
int
EESR
;
565
volatile
unsigned
int
EESRH
;
566
volatile
unsigned
int
SER
;
567
volatile
unsigned
int
SERH
;
568
volatile
unsigned
int
SECR
;
569
volatile
unsigned
int
SECRH
;
570
volatile
unsigned
char
RSVD10
[8];
571
volatile
unsigned
int
IER
;
572
volatile
unsigned
int
IERH
;
573
volatile
unsigned
int
IECR
;
574
volatile
unsigned
int
IECRH
;
575
volatile
unsigned
int
IESR
;
576
volatile
unsigned
int
IESRH
;
577
volatile
unsigned
int
IPR
;
578
volatile
unsigned
int
IPRH
;
579
volatile
unsigned
int
ICR
;
580
volatile
unsigned
int
ICRH
;
581
volatile
unsigned
int
IEVAL
;
582
volatile
unsigned
char
RSVD11
[4];
583
volatile
unsigned
int
QER
;
584
volatile
unsigned
int
QEER
;
585
volatile
unsigned
int
QEECR
;
586
volatile
unsigned
int
QEESR
;
587
volatile
unsigned
int
QSER
;
588
volatile
unsigned
int
QSECR
;
589
volatile
unsigned
char
RSVD12
[3944];
590
IRES_EDMA3CHAN_EDMA3ShadowRegister
SHADOW
[8];
591
volatile
unsigned
char
RSVD13
[4096];
592
IRES_EDMA3CHAN_PaRamStruct
PARAMENTRY
[512];
593
}
IRES_EDMA3CHAN_EDMA3RegisterLayer
;
594
598
typedef
struct
IRES_EDMA3CHAN_Properties
{
599
600
unsigned
int
numDmaChannels
;
603
unsigned
int
numQdmaChannels
;
607
unsigned
int
numTccs
;
610
unsigned
int
numPaRAMSets
;
613
unsigned
int
numEvtQueue
;
616
unsigned
int
numTcs
;
620
unsigned
int
numRegions
;
631
unsigned
short
dmaChPaRAMMapExists
;
632
633
unsigned
short
memProtectionExists
;
637
IRES_EDMA3CHAN_EDMA3RegisterLayer
*
globalRegs
;
641
}
IRES_EDMA3CHAN_Properties
;
642
650
typedef
enum
IRES_EDMA3CHAN_DmaDestType
{
651
INTMEMORY0
= 0,
652
INTMEMORY1
= 1,
653
INTMEMORY2
= 2,
654
EXTMEMORY0
= 3,
655
EXTMEMORY1
= 4,
656
EXTMEMORY2
= 5,
657
OTHER0
= 6,
658
OTHER1
= 7
659
}
IRES_EDMA3CHAN_DmaDestType
;
660
679
typedef
struct
IRES_EDMA3CHAN2_Obj
{
680
681
IRES_Obj
ires
;
682
684
IRES_EDMA3CHAN_PaRamStruct
*
shadowPaRams
;
685
687
unsigned
int
*
assignedPaRamAddresses
;
688
690
short
*
assignedPaRamIndices
;
691
693
short
*
assignedTccIndices
;
694
696
short
assignedNumPaRams
;
697
699
short
assignedNumTccs
;
700
702
short
assignedQdmaChannelIndex
;
703
705
short
assignedEdmaChannelIndex
;
706
708
unsigned
int
esrBitMaskL
;
709
711
unsigned
int
esrBitMaskH
;
712
714
unsigned
int
iprBitMaskL
;
715
717
unsigned
int
iprBitMaskH
;
718
719
XDAS_Int32
*
queueMap
;
733
}
IRES_EDMA3CHAN2_Obj
;
734
735
#ifdef __cplusplus
736
}
737
#endif
/* extern "C" */
738
741
#endif
Copyright 2014, Texas Instruments Incorporated